Intel Corporation patent applications on January 25th, 2024
Patent Applications by Intel Corporation on January 25th, 2024
Intel Corporation: 65 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (9), H01L23/538 (7), G06N3/084 (6), H01L23/5386 (5), H01L24/16 (5)
With keywords such as: device, data, layer, circuit, integrated, include, based, glass, interconnect, and substrate in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): David Gonzalez Aguirre of Portland OR (US) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Rafael De La Guardia Gonzalez of Teuchitlan (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, David Gomez Gutierrez of Tlaquepaque (MX) for intel corporation, Edgar Macias Garcia of Jalisco (MX) for intel corporation, Javier Turek of Beaverton OR (US) for intel corporation, Julio Zamora Esquivel of West Sacramento CA (US) for intel corporation
IPC Code(s): B25J9/16
Abstract: a component of a robotic system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: train a neuro-capability map plugin, which is a continuous or semi-continuous resolution neural network component encoded with kinematic capability attributes with respect to an action to be performed by a robot in a workspace; and publish the neuro-capability map plugin to a robotic skills repository where it is obtainable by robotic controller circuitry for embedding within a neural network usable perform one or more inferences to control the robot to perform the action.
Inventor(s): Krishnakumar Varadarajan of Bangalore (IN) for intel corporation, Aurelien Mozipo of Portland OR (US) for intel corporation, Juan Cevallos Palomeque of Portland OR (US) for intel corporation, Teik Wah Lim of Bayan Lepas (MY) for intel corporation, Aanandh Balasubramanian of Bangalore (IN) for intel corporation
IPC Code(s): G01K1/02, G01K1/024, G01K3/08
Abstract: a method is provided for thermally monitoring an integrated circuit during operation of the integrated circuit. the method includes receiving a measurement of a temperature in a circuit design for the integrated circuit from a temperature sensor, and determining a hottest temperature in the circuit design based on the measurement of the temperature. a non-transitory computer readable storage medium includes computer readable instructions stored thereon for causing a computing system to receive a measurement of a first temperature in a circuit design for an integrated circuit from a temperature sensor, and determine a second temperature of a cold spot in an active region of the circuit design by adjusting the measurement of the first temperature generated by the temperature sensor by an offset.
Inventor(s): Wesley B. Morgan of Lake Oswego OR (US) for intel corporation, Mohanraj Prabhugoud of Beaverton OR (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Eric J. M. Moret of Beaverton OR (US) for intel corporation, Pooya Tadayon of Portland OR (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation
IPC Code(s): G02B6/38
Abstract: optical connectors with alignment features, and methods of forming the same, are disclosed herein. in one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. the optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.
Inventor(s): Nicholas D. Psaila of Lanark (GB) for intel corporation, Pooya Tadayon of Portland OR (US) for intel corporation
IPC Code(s): G02B6/42
Abstract: technologies for beam expansion in glass substrates are disclosed. in the illustrative embodiment, light in a waveguide defined in a glass substrate is allowed to expand towards a curved mirror defined in the glass substrate. the light is collimated to a beam as it is reflected off the mirror. in the illustrative embodiment, the light is reflected upwards toward the top surface of the glass substrate. a photonic integrated circuit (pic) die may be mounted on the glass substrate. a micromirror lens fixed to the pic die can focus the collimated beam into a waveguide defined in the pic die. in some embodiments, an interface for an optical connector may be formed in the glass substrate, allowing the optical connector to be removably plugged into the glass substrate.
Inventor(s): Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/42
Abstract: technologies for beam expansion for vertically-emitting photonic integrated circuits are disclosed. in the illustrative embodiment, waveguides in a photonic integrated circuit (pic) die guide light to vertical couplers, which direct the light from the waveguides out of the top surface of the pic die. a glass microoptic substrate is mounted on the top surface of the pic die, positioned over the vertical couplers. a mirror in the glass microoptic substrate reflects the light from the vertical couplers to propagate in a direction parallel to the top surface of the pic die. another set of mirrors in the glass microoptic substrate focus the light from each waveguide into a collimated beam directed out of the top surface of the glass microoptic substrate.
20240027706.PHOTONICS INTEGRATED CIRCUIT DEVICE PACKAGING_simplified_abstract_(intel corporation)
Inventor(s): Pooya Tadayon of Portland OR (US) for intel corporation, Eric J. M. Moret of Beaverton OR (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, David Shia of Portland OR (US) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation, Russell Childs of Edinburgh (GB) for intel corporation
IPC Code(s): G02B6/42, G02B6/43
Abstract: in one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (eic), a photonics integrated circuit (pic) electrically coupled to the eic, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. the glass block defines an optical path with one or more optical elements to direct light between the pic and a fiber array unit (fau) when attached to the glass block.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
Abstract: in one embodiment, an integrated circuit package includes a package substrate comprising a glass core layer, an optical path at least partially in the glass core layer, and a photonics integrated circuit (pic) at least partially embedded in the glass core layer and in optical connection with the optical path. the optical path may include a waveguide in the glass core layer and/or a microlens. the integrated circuit package may also include an electronic integrated circuit (eic) in electrical connection with the pic, and a processor in electrical connection with the eic.
Inventor(s): Jonathan Doylend of Savannah MO (US) for intel corporation, Amit Mizrahi of San Jose CA (US) for intel corporation, Faraz Monifi of Mountain View CA (US) for intel corporation, Saeed Fathololoumi of Los Gatos CA (US) for intel corporation
IPC Code(s): G02F1/313, G02F1/29, G01S7/481
Abstract: a multi-wavelength transmitter suitable for use in lidar applications where an array of output beams comprising a plurality of wavelengths is spatially modulated with low amplification requirements. the optical transmitter comprises one or more light sources, such as a plurality of laser emitters operable at different wavelengths. the light source(s) are coupled, for example through one or more planar waveguides, to an optical switch network comprising one or more switches. the switch network is to route, in a time divided manner, source beams to individual ones of a plurality of switch output ports thereby modulating the wavelength of a beam exiting each of the output ports. a plurality of output couplers, for example comprising edge coupled spot size convertors, are coupled to separate ones of the switch output ports, for example through one or more planar waveguides and/or one or more beam splitters.
Inventor(s): Anupama Suryanarayanan of Hillsboro CO (US) for intel corporation, Avinash N. Ananthakrishnan of Portland OR (US) for intel corporation, Chinmay Ashok of Beaverton OR (US) for intel corporation, Jeremy J. Shrall of Portland OR (US) for intel corporation
IPC Code(s): G06F1/26, G06F1/3287, G06F13/42, G06F1/32, G06F1/3203, G06F1/3296, G06F9/46, G06F1/3234, G06F30/00
Abstract: in one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. the power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. other embodiments are described and claimed.
Inventor(s): Jianwei Dai of Portland OR (US) for intel corporation, David Pawlowski of Portland OR (US) for intel corporation, Adwait Purandare of Hillsboro OR (US) for intel corporation, Ankush Varma of Portland OR (US) for intel corporation
IPC Code(s): G06F1/3234, G06F1/324, G06F1/3206
Abstract: in one embodiment, a processor includes a plurality of intellectual property (ip) circuits, each to execute instructions and including a local control circuit to enable the ip circuit to operate at a level above a local current budget for the ip circuit, unless the processor is undergoing a global violation. the processor may further include a power controller coupled to the plurality of ip circuits. the power controller may include a control circuit to receive request information from the plurality of ip circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. other embodiments are described and claimed.
Inventor(s): Sadegh Yazdanshenas of Toronto (CA) for intel corporation, Tim Vanderhoek of East York (CA) for intel corporation
IPC Code(s): G06F7/523, G06F1/03
Abstract: an integrated circuit includes a logic block configured to perform multiplication operations. the logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
Inventor(s): Erdinc OZTURK of Paris (FR) for intel corporation, Kirk S. YAP of Westborough MA (US) for intel corporation, Tomasz KANTECKI of Ennis (IE) for intel corporation
IPC Code(s): G06F9/38
Abstract: examples described herein relate to a non-transitory computer-readable medium comprising instructions, that if executed by circuitry, cause the circuitry to: configure circuitry to perform cryptographic operations on packets based on advanced encryption standard with galois/counter mode (aes-gcm) hash (ghash), wherein the cryptographic operations comprise a reduction operation and wherein the reduction operation comprises a single galois territory multiplication 64 bit operation. the circuitry can include one or more of: a central processing unit (cpu), cpu-executed microcode, an accelerator, or a network interface device.
20240028381.VIRTUAL I/O DEVICE MANAGEMENT_simplified_abstract_(intel corporation)
Inventor(s): Shaopeng He of Shanghai (CN) for intel corporation, Yadong Li of Portland OR (US) for intel corporation, Anjali Singhai Jain of Portland OR (US) for intel corporation, Eliel Louzoun of Jerusalem (IL) for intel corporation, Israel Ben-Shahar of Jerusalem (IL) for intel corporation, Brad A. Burres of Newton MA (US) for intel corporation, Bartosz Pawlowski of Gdansk (PL) for intel corporation, Anton Nadezhdin of Gdansk (PL) for intel corporation, Rashmi Hanagal Nagabhushana of Bangalore (IN) for intel corporation, Rupin H. Vakharwala of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/455
Abstract: a network interface device executes an input/output (i/o) virtualization manager to identify a virtual device defined to include resources of a particular virtual functions in a plurality of virtual functions associated with a physical function of a device. an operation is identified to be performed between the virtual device and a system image hosted by a host system coupled to the network interface device. the network interface device emulates the virtual device in the operation using the i/o virtualization manager.
20240028404.THREAD GROUP SCHEDULING FOR GRAPHICS PROCESSING_simplified_abstract_(intel corporation)
Inventor(s): Ben Ashbaugh of Folsom CA (US) for intel corporation, Jonathan Pearce of Hillsboro OR (US) for intel corporation, Murali Ramadoss of Folsom CA (US) for intel corporation, Vikranth Vemulapalli of Folsom CA (US) for intel corporation, William B. Sadler of Folsom CA (US) for intel corporation, Sungye Kim of Folsom CA (US) for intel corporation, Marian Alin Petre of San Mateo CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06F9/54, G06F12/0837, G06F9/48, G06F9/345
Abstract: embodiments are generally directed to thread group scheduling for graphics processing. an embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.
20240028409.DECENTRALIZED COMPUTE INFRASTRUCTURE_simplified_abstract_(intel corporation)
Inventor(s): Muthaiah Venkatachalam of Beaverton OR (US) for intel corporation, Gautam Singh of Morrisville NC (US) for intel corporation, Geoffrey Gustafson of Saint Johns FL (US) for intel corporation
IPC Code(s): G06F9/50
Abstract: embodiments described herein are generally directed to decentralized compute infrastructure (dci). according to one embodiment, a determination is made by a recommendation engine running on a client computer system to offload a particular non-containerized workload associated with a host application from a saas cloud to the client computing system on which the host application is also running. after the determination, a unit of execution in which the particular workload is packaged may be fetched and the non-containerized workload may be caused to be run locally on the client computing system. in some examples, a metric indicative of cost savings accrued by a vendor of the host application due to offloading may be tracked and at least a portion of the cost savings may be distributed to one or both of a subscriber of the host application and one or more third party stakeholders.
20240028449.MULTI-PROTOCOL SUPPORT ON COMMON PHYSICAL LAYER_simplified_abstract_(intel corporation)
Inventor(s): Debendra Das Sharma of Saratoga CA (US) for intel corporation
IPC Code(s): G06F11/10, G06F13/40
Abstract: systems and devices can include a physical layer (phy) that includes a logical phy to support multiple interconnect protocols. the logical phy can include a first set of cyclic redundancy check (crc) encoders corresponding to a first interconnect protocol, and a second set of crc encoders corresponding to a second interconnect protocol. a multiplexer can direct data to the first set or the second set of crc encoders based on a selected interconnect protocol. the logical phy can include a first set of error correcting code (ecc) encoders corresponding to the first interconnect protocol and a second set of ecc encoders corresponding to the second interconnect protocol. the multiplexer can direct data to the first set or the second set of ecc encoders based on the selected interconnect protocol. in embodiments, different crc/ecc combinations can be used based on the interconnect protocol and the link operational conditions.
20240028505.MEMORY ALLOCATION BASED ON TIME_simplified_abstract_(intel corporation)
Inventor(s): Sharanyan SRIKANTHAN of Portland OR (US) for intel corporation, Thomas WILLHALM of Sandhausen (DE) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation, Marcos E. CARRANZA of Portland OR (US) for intel corporation
IPC Code(s): G06F12/02
Abstract: examples described herein relate to allocation of an amount of memory for a time duration based on receipt of a request to allocate an amount of memory for a time duration. the request can include a configuration that requests an allocation of the amount of memory and the configuration specifies a time tier and/or the time duration. the request can specify one or more of: a request identifier, the amount of memory to allocate, or a requested time duration to reserve the amount of memory.
20240028531.DYNAMIC SWITCH FOR MEMORY DEVICES_simplified_abstract_(intel corporation)
Inventor(s): John R. DREW of Aloha OR (US) for intel corporation, James A. McCALL of Portland OR (US) for intel corporation, Tongyan ZHAI of Portland OR (US) for intel corporation, Jun LIAO of Portland OR (US) for intel corporation, Min Suet LIM of Gelugor (MY) for intel corporation, Shigeki TOMISHIMA of Portland OR (US) for intel corporation
IPC Code(s): G06F13/16, G06F13/40
Abstract: a memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. a switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. a memory controller can toggle a chip select signal as a single control signal to drive the switch. each switch includes pairs of field effect transistors (fets), including any of cmos, nmos and pmos fets. the switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.
Inventor(s): Sharath Raghava of Los Gatos CA (US) for intel corporation, Dheeraj Subbareddy of Portland OR (US) for intel corporation, Kavitha Prasad of San Jose CA (US) for intel corporation, Ankireddy Nalamalpu of Portland OR (US) for intel corporation, Harsha Gupta of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F13/40, G06F13/42
Abstract: an integrated circuit device may include a first network on chip (noc) circuit configured to receive a set of data and transfer the set of data to a first node of the first noc circuitry. the first node is configured to transfer the set of data to a second noc circuit of an additional integrated circuit device separate from the integrated circuit device.
20240028550.LAN PCIE BANDWIDTH OPTIMIZATION_simplified_abstract_(intel corporation)
Inventor(s): Dekel SHIRIZLY of Binyamina (IL) for intel corporation
IPC Code(s): G06F13/42, G06F13/28
Abstract: methods and apparatus for lan pcie bandwidth optimization. packets to be sent outbound onto a network are generated and buffered in memory on a host computing device. transmit (tx) descriptors associated with respective packets are generated comprising descriptor data and at least a portion of the packet data for the packet, where the descriptor data are configured to be processed by a network apparatus coupled to the network, such as a network interface controller (nic) or network adapter. tx descriptors are transferred from host memory to the network apparatus over a peripheral component internet express (pcie) interconnect using a single respective transaction level packet (tlp) per tx descriptor. this increases bandwidth utilization for the pcie interconnect by reducing the number of tlps that are used to transfer tx descriptors and packet data to the network apparatus. the novel tx descriptors may be used for lan and wireless lans.
20240028551.TRANSACTION LAYER PACKET FORMAT_simplified_abstract_(intel corporation)
Inventor(s): David J. Harriman of Portland OR (US) for intel corporation
IPC Code(s): G06F13/42
Abstract: a device includes protocol logic to determine a packet type for a packet and generate and send the corresponding packet. the packet includes a packet header with a header base, the header base including a type field and a header content field. the type field indicates the packet type and the header content field indicates which of a plurality of header content blocks is to be included in the packet header with the header base. information in fields of the header base indicate a total length of the packet.
20240028577.HARDWARE ACCELERATED STRING FILTER_simplified_abstract_(intel corporation)
Inventor(s): Jixing Gu of Shanghai (CN) for intel corporation, Vinodh Gopal of Westborough MA (US) for intel corporation, Fang Xie of Santa Clara CA (US) for intel corporation, David Cohen of Hull MA (US) for intel corporation, Wajdi Feghali of Boston MA (US) for intel corporation
IPC Code(s): G06F16/22
Abstract: an apparatus may include an accelerator and a processor. the processor may receive an input string targeting a data buffer comprising a plurality of strings. the processor may receive, from the accelerator, a fixed-length data buffer based on the data buffer, respective ones of a plurality of entries of the fixed-length data buffer based on respective ones of the strings. the processor may receive, from the accelerator, a plurality of streams, respective ones of the plurality of streams to comprise a portion of respective entries in the fixed-length data buffer. the processor may generate, based on the input string, a plurality of target portions of the input string. the processor may receive, from the accelerator, indexes of the plurality of streams based on respective target portions of the input string matching respective entries of the plurality of streams. the processor may aggregate the indexes received from the accelerator.
Inventor(s): Xiangyong Wang of San Jose CA (US) for intel corporation, David Kehlet of Los Altos Hills CA (US) for intel corporation, Diana Cristina Ojeda Aristizabal of Toronto (CA) for intel corporation, Ian Kuon of Toronto (CA) for intel corporation, Mehmet Avci of Toronto (CA) for intel corporation
IPC Code(s): G06F30/398
Abstract: integrated circuit devices, methods, and circuitry are provided for performing timing analysis for chip-to-chip connections between integrated circuits in a multichip package. a system may include an integrated circuit package and a computing system. the integrated circuit package may have a first integrated circuit connected to a second integrated circuit via a chip-to-chip connection. the chip-to-chip connection may also be connected to a package ball. the computing system may perform timing analysis on a circuit design for the first integrated circuit with respect the chip-to-chip connection based on user-specified parasitic data relating to the connection to the package ball.
Inventor(s): Anthony Rhodes of Portland OR (US) for intel corporation, Hong Lu of Santa Clara CA (US) for intel corporation, Lama Nachman of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/047, G06N3/084
Abstract: example apparatus disclosed include interface circuitry, machine readable instruction, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to access source input data and target input data, identify a domain shift prediction based on at least one of a feature decorrelation of the source input data or a feature decorrelation of the target input data, the domain shift prediction a source domain prediction or a target domain prediction, initiate gradient propagation of a domain loss to determine data features for the domain shift prediction, and rank input data features for the domain shift prediction.
Inventor(s): Tomer Schwartz of Even Yehuda (IL) for intel corporation, Ehud Cohen of Kiryat Motskin (IL) for intel corporation, Uzi Sarel of Zichron-Yaakov (IL) for intel corporation, Amitai Armon of Tel-Aviv (IL) for intel corporation, Yaniv Fais of Tel-Aviv (IL) for intel corporation, Lev Faivishevsky of Kfar Saba (IL) for intel corporation, Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Yahav Shadmiy of Ramat Gan (IL) for intel corporation, Jacob Subag of Kiryat Haim (IL) for intel corporation
IPC Code(s): G06N3/063, G06N3/084, G06N3/044, G06N3/045
Abstract: a mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. a method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. the method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.
Inventor(s): Krishnakumar Nair of Santa Clara CA (US) for intel corporation, Andrew Yang of Cupertino CA (US) for intel corporation, Brian Morris of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/084, G06N3/063, G06N3/045
Abstract: thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of fp16 values and a plurality of bits that define an exponent shared by some or all of the fp16 values included in the tensor. the fp16 values may include ieee 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. the tensor may include a shared exponent and fp16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. the tensor may include a shared exponent and fp16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the fp16 value exponent with the shared exponent.
Inventor(s): Xuesong Shi of Beijing (CN) for intel corporation, Zhigang Wang of Beijing (CN) for intel corporation
IPC Code(s): G06N3/094, G06N3/0475
Abstract: training data generators and methods for machine learning are disclosed. an example method to generate training data for machine learning by generating simulated training data for a target neural network, transforming, with a training data transformer, the simulated training data form transformed training data, the training data transformer trained to increase a conformance of the transformed training data and the simulated training data, and training the target neural network with the transformed training data.
Inventor(s): Anthony Rhodes of Portland OR (US) for intel corporation, Manan Goel of Portland OR (US) for intel corporation
IPC Code(s): G06T1/20, G06T7/11, G06T7/174, G06T3/40, G06T9/00, G06F18/241, G06V10/764, G06V10/26, G06V20/40
Abstract: techniques related to automatically segmenting video frames into per pixel fidelity object of interest and background regions are discussed. such techniques include applying tessellation to a video frame to generate feature frames corresponding to the video frame and applying a segmentation network implementing context aware skip connections to an input volume including the feature frames and a context feature volume corresponding to the video frame to generate a segmentation for the video frame.
20240029300.RE-LOCALIZATION OF ROBOT_simplified_abstract_(intel corporation)
Inventor(s): Xuesong SHI of Beijing (CN) for intel corporation, Yuxin TIAN of Beijing (CN) for intel corporation, Sangeeta GHANGAM of Chandler AZ (US) for intel corporation, Dawei WANG of Beijing (CN) for intel corporation
IPC Code(s): G06T7/73, G06T7/60, G06T3/00, G06T1/00
Abstract: a method for re-localization of the robot may include retrieving, for each of keyframes in a keyframe database of the robot, image features and a pose of the keyframe, the image features of the keyframe comprising a global descriptor and local descriptors of the keyframe (); extracting image features of a current frame captured by the robot, the image features of the current frame comprising a global descriptor and local descriptors of the current frame (); determining one or more rough matching frames from the keyframes based on comparison between the global descriptor of each keyframe and the global descriptor of the current frame (); determining a final matching frame from the one or more rough matching frames based on comparison between the local descriptors of each rough matching frame and the local descriptors of the current frame (); and calculating a pose of the current frame based on a pose of the current frame based on a pose of the final matching frame ().
Inventor(s): Peixi Xiong of Hillsboro OR (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, Ravishankar Iyer of Portland OR (US) for intel corporation, Mrutunjayya Mrutunjayya of Santa Clara CA (US) for intel corporation
IPC Code(s): G06V20/64, G06V20/70, G06T15/20, G06V10/56, G06V10/774
Abstract: systems, apparatuses and methods may provide for technology that encodes multi-view visual data into latent features via an aggregator encoder, decodes the latent features into one or more novel target views different from views of the multi-view visual data via a rendering decoder, and decodes the latent features into an object label via a label decoder. the operation to decode the latent features via the rendering decoder and to decode the latent features via the label decoder occur at least partially at the same time. the operation to encode, via the aggregator encoder, the multi-view visual data into the latent features further includes operations to: perform, via the aggregator encoder, semantic object recognition operations based on radiance field view synthesis operations, and perform, via the aggregator encoder, radiance field view synthesis operations based on semantic object recognition operations.
Inventor(s): Prabhakar Subrahmanyam of San Jose CA (US) for intel corporation, Viktor Polyanko of San Jose CA (US) for intel corporation, Vishnu Prasadh Sugumar of Santa Clara CA (US) for intel corporation, Ying-Feng Pang of San Jose CA (US) for intel corporation, Mark Lawrence Bianco of Mountain View CA (US) for intel corporation, Sandeep Ahuja of Portland OR (US) for intel corporation, Tejas Shah of Austin TX (US) for intel corporation
IPC Code(s): G08B21/18, H05K7/20
Abstract: methods, systems, apparatus, and articles of manufacture to monitor heat exchangers and associated reservoirs are disclosed. an example apparatus includes programmable circuitry to detect, based on outputs of a sensor associated with a first reservoir, a coolant level of the first reservoir, the first reservoir removably coupled to a second reservoir, the first reservoir to supply coolant to the second reservoir, predict, based on the coolant level, a characteristic associated with operation of a cooling device fluidly coupled to the second reservoir, and cause an output to be presented at a user device based on the predicted characteristic.
20240029942.CHIP MULTI-LAYER TRANSFORMER AND INDUCTOR_simplified_abstract_(intel corporation)
Inventor(s): Chuanzhao Yu of Phoenix AZ (US) for intel corporation, Qiang Li of Gilbert AZ (US) for intel corporation, David Newman of Tempe AZ (US) for intel corporation
IPC Code(s): H01F27/28, H01F41/04
Abstract: a stacked transformer or inductor apparatus including a first layer with a first layer wire element extending around a center axis and a second layer with a second layer wire element. the second layer element includes side by side first and second wire sections in parallel spaced relation extending around the center axis and the first wire section is connected to the first layer wire element to form a primary turn winding. a third layer includes a third layer wire element extending around the center axis and connected to the second wire section of the second layer wire element to form a secondary turn winding partially overlapping with the primary turn winding.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Hamid R. Azimi of Paradise Valley AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/768, H05K7/20, H05K1/11, H01L23/528, H01L23/15
Abstract: panel-level high performance computing (hpc) computing architectures and methods for making the same are disclosed. panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. the glass reinforcement layer can have interconnect structures and a local interconnect component. panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.
20240030067.SELF-ALIGNED CONTACTS_simplified_abstract_(intel corporation)
Inventor(s): Mark T. BOHR of Aloha OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Nadia M. RAHHAL-ORABI of Lake Oswego OR (US) for intel corporation, Subhash M. JOSHI of Hillsboro OR (US) for intel corporation, Joseph M. STEIGERWALD of Forest Grove OR (US) for intel corporation, Jason W. KLAUS of Portland OR (US) for intel corporation, Jack HWANG of Portland OR (US) for intel corporation, Ryan MACKIEWICZ of Beaverton OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L29/78, H01L29/49, H01L29/66, H01L29/51, H01L21/28, H01L21/283, H01L21/311, H01L23/522, H01L23/528, H01L29/08, H01L29/423, H01L29/16, H01L29/45, H01L21/285, H01L23/535
Abstract: a transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. the insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. the insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
Inventor(s): Rajasekaran SWAMINATHAN of Chandler AZ (US) for intel corporation, Mukul RENAVIKAR of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/367, H01L23/373, H01L23/00
Abstract: embodiments include semiconductor packages and methods of forming such packages. a semiconductor package includes a die on a package substrate, an integrated heat spreader (ihs) on the package substrate and above the die, and a solder thermal interface material (stim) coupling the die to the ihs. the semiconductor package includes a low-temperature solder (lts) paste comprising an alloy of tin and bismuth (bi), and the lts paste on a bottom surface of the package substrate having a ball grid array. the lts paste may have a weight percentage of bi greater than 35% and a melting point less than or equal to a melting point of the stim, where the stim includes indium. the weight percentage of bi may be between approximately 35% to 58%. the semiconductor package may include a solder ball coupling the lts paste on the package substrate to the lts paste on a second package substrate.
Inventor(s): Feras Eid of Chandler AZ (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/427, H01L23/38, H01L23/373, H01L23/31, H01L23/48, H03H9/46, H01L23/66
Abstract: disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (ic) packages.
20240030116.ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES_simplified_abstract_(intel corporation)
Inventor(s): Debendra MALLIK of Chandler AZ (US) for intel corporation, Robert L. SANKMAN of Phoenix AZ (US) for intel corporation, Robert NICKERSON of Chandler AZ (US) for intel corporation, Mitul MODI of Phoenix AZ (US) for intel corporation, Sanka GANESAN of Chandler AZ (US) for intel corporation, Rajasekaran SWAMINATHAN of Chandler AZ (US) for intel corporation, Omkar KARHADE of Chandler AZ (US) for intel corporation, Shawna M. LIFF of Scottsdale AZ (US) for intel corporation, Amruthavalli ALUR of Tempe AZ (US) for intel corporation, Sri Chaitra J. CHAVALI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/31, H01L23/538, H01L23/00
Abstract: ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. an exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 �m, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (bga) metallurgy. other embodiments are described.
Inventor(s): Sanka Ganesan of Chandler AZ (US) for intel corporation, Ram Viswanath of Phoenix AZ (US) for intel corporation, Xavier Francois Brun of Hillsboro OR (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Jason M. Gamba of Gilbert AZ (US) for intel corporation, Manish Dubey of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/367, H01L23/31, H01L23/00
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (tsv); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (tmv) conductively coupled to the tsv; and a second mold material region at the second face, wherein the second mold material region includes a second tmv conductively coupled to the tsv.
Inventor(s): Kemal AYGUN of Tempe AZ (US) for intel corporation, Zhiguo QIAN of Chandler AZ (US) for intel corporation, Jianyong XIE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/48, H01L23/498, H01L23/31, H01L23/00, H01L23/522, H01L23/532
Abstract: methods/structures of joining package structures are described. those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Hamid R. Azimi of Paradise Valley AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L25/065, H01L23/473, H01L25/00, H01L25/10, H01L21/48, H10B80/00, G02B6/12
Abstract: panel-level high performance computing (hpc) computing architectures and methods for making the same are disclosed. panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. the glass reinforcement layer can have interconnect structures and a local interconnect component. panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.
20240030150.MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Aleksandar ALEKSOV of Chandler AZ (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L25/065, H01L25/16, H01L23/498, H01L23/367, H01L23/13, H01L23/00
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
Inventor(s): Debendra Das Sharma of Saratoga (US) for intel corporation, Peter Z. Onufryk of Flanders NJ (US) for intel corporation, Gerald S. Pasdast of San Jose (US) for intel corporation, Sathya Narasimman Tiagaraj of San Jose (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/065
Abstract: methods and apparatus relating to a universal chiplet interconnect express™ (ucie™)-three dimensional (ucie-3d™) interconnect which may be utilized as an on-package interconnect are described. in one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. a first network-on-chip controller (noc) logic circuitry controls the first physical layer module. a second noc logic circuitry controls the second physical layer module. other embodiments are also claimed and disclosed.
Inventor(s): Gianni SIGNORINI of Garching bei Muenchen (DE) for intel corporation, Veronica SCIRIHA of Muenchen (DE) for intel corporation, Thomas WAGNER of Regelsbach (DE) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/538
Abstract: in accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. one example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.
Inventor(s): Anup PANCHOLI of Hillsboro OR (US) for intel corporation, Kimin JUN of Portland OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L21/56, H01L21/683, H01L23/00, H01L25/00
Abstract: an apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
Inventor(s): Gang Duan of Chandler AZ (US) for intel corporation, Hamid R. Azimi of Paradise Valley AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/16, H01L23/427, H01L23/538, G02B6/12
Abstract: panel-level high performance computing (hpc) computing architectures and methods for making the same are disclosed. panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. the glass reinforcement layer can have interconnect structures and a local interconnect component. panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.
Inventor(s): Wilfred Gomes of Portland OR (US) for intel corporation, Abhishek A. Sharma of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation, Doug B. Ingerly of Portland OR (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/528, H01L23/522, H01L23/00
Abstract: microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. as used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two ic structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. for example, a microelectronic assembly may include a first ic structure that includes first interconnects and a second ic structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.
Inventor(s): Biswajeet GUHA of Hillsboro OR (US) for intel corporation, William HSU of Hillsboro OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Dax M. CRUM of Beaverton OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L21/8234, H01L23/522, H01L29/06, H01L29/08, H01L29/423
Abstract: self-aligned gate endcap (sage) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (sage) architectures with gate-all-around devices, are described. in an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. a nanowire is over the semiconductor fin. a gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. a pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
Inventor(s): ANAND S. KONANUR of SAN JOSE CA (US) for intel corporation, SONGNAN YANG of SAN JOSE CA (US) for intel corporation, ULUN KARACAOGLU of SAN DIEGO CA (US) for intel corporation, JIANCHENG TAO of SHANGHAI (CN) for intel corporation, FARID ADRANGI of LAKE OSWEGO OR (US) for intel corporation
IPC Code(s): H01Q7/00, H04W4/80, H01Q1/22, H01Q3/24, H04B5/00, H02J50/10, G06F1/16, G06F3/044, H02J50/80, H02J7/00, G06F3/039, G06F3/041, H02J50/40
Abstract: apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer electromagnetic energy; a sensor coupled to a processor, to select a coil from among the plurality of electrically conductive coils; a switch to energize the selected coil; and a switch controller coupled to the switch and to the processor. in some embodiments, the plurality of coils may comprise an inductive charging interface. some embodiments may further include a communication interface between the processor to the plurality of electrically conductive coils, the plurality of coils comprising an interface for near-field communications (nfc). the antenna coils may be arranged to provide improved nfc coverage when the computing device is in a respective predetermined physical configuration. sensors may be used to detect the configuration and switch nfc communications to use a preferred antenna coil for the detected configuration.
Inventor(s): Qinghua Li of San Ramon CA (US) for intel corporation, Xiaogang Chen of Portland OR (US) for intel corporation, Assaf Gurevitz of Ramat Hasharon (IL) for intel corporation, Feng Jiang of Santa Clara CA (US) for intel corporation, Jonathan Segev of Sunnyvale CA (US) for intel corporation, Gadi Shor of Tel Aviv (IL) for intel corporation
IPC Code(s): H04L5/00, H04L27/26
Abstract: this disclosure describes systems, methods, and devices related to enhanced sounding for secure mode wireless communications. a device may generate a channel sounding symbol comprising a first subcarrier and a second subcarrier, wherein a first amplitude of the first subcarrier is different than a second amplitude of the second subcarrier. the device may generate a channel sounding signal comprising the channel sounding symbol. the device may send the channel sounding signal to a second device.
Inventor(s): ANDREA BASSO of London (GB) for intel corporation, DUMITRU-DANIEL DINU of Chandler AZ (US) for intel corporation, SANTOSH GHOSH of Hillsboro OR (US) for intel corporation, MANOJ SASTRY of Portland OR (US) for intel corporation
IPC Code(s): H04L9/00, H04L9/32, H04L9/08, H04L9/30
Abstract: in one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication function using the first input as an element of a digital signature protocol, the polynomial multiplication function comprising a plurality of polynomial multiplication operations, the polynomial multiplication function performed in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation or a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation. other examples may be described.
Inventor(s): ANDREA BASSO of London (GB) for intel corporation, DUMITRU-DANIEL DINU of Chandler AZ (US) for intel corporation, SANTOSH GHOSH of Hillsboro OR (US) for intel corporation, MANOJ SASTRY of Portland OR (US) for intel corporation
IPC Code(s): H04L9/08, H04L9/30
Abstract: in one example an apparatus comprises a first input node to receive a first input, a second input node to receive a control signal, a polynomial multiplication circuitry to perform a polynomial multiplication operation using the first input in a security mode determined by the control signal, the security mode comprising one of a first mode in which no side-channel protection is provided to the polynomial multiplication operation, a second mode in which a shuffling-based side-channel protection is provided to the polynomial multiplication operation, a third mode in which a masking or splitting side-channel protection is provided to the polynomial multiplication operation, or a fourth mode in which a masking and shuffling based side-channel protection is provided to the polynomial multiplication operation. other examples may be described.
Inventor(s): Po-Kai Huang of San Jose CA (US) for intel corporation, Cheng Chen of Camas WA (US) for intel corporation, Ido Ouzieli of Tel Aviv (IL) for intel corporation, Avner Epstein of Givatayim (IL) for intel corporation, Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Ofer Schreiber of Kiryat Ono (IL) for intel corporation, Arik Klein of Givaat Shmuel (IL) for intel corporation, Daniel Bravo of Portland OR (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Ofer Hareuveni of Haifa (IL) for intel corporation, Ehud Reshef of Kiryat Tivon (IL) for intel corporation, Nir Balaban of Kfar Netter (IL) for intel corporation
IPC Code(s): H04L9/08, H04W76/15, H04L61/5069
Abstract: this disclosure describes systems, methods, and devices related to security for multi-link operations. a multi-link device (mld) may establish a first communication link between a first device of the mld and a first device of a second mld, and a second communication link between a second device of the mld and a second device of the second mld. the mld may generate a group-addressed message. the mld may protect the group-addressed message using a first key or a first integrity key. the mld may protect the group-addressed message using a second key or a second integrity key. the mld may send, using the first communication link, the group-addressed message protected using the first key or the first integrity key, and may send, using the second communication link, the group-addressed message protected using the second key or the second integrity key.
20240031158.SECURE UNLOCK SYSTEMS FOR LOCKED DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Michael Neve De Mevergnies of Beaverton OR (US) for intel corporation, Neel Shah of Billerica MA (US) for intel corporation, Kumar Dwarakanath of Folsom CA (US) for intel corporation, Fred Bolay of Folsom CA (US) for intel corporation, Mukesh Kataria of Fremont CA (US) for intel corporation
IPC Code(s): H04L9/32, G06F21/33, G06F21/62, G06F21/85, G06F21/72, H04L9/06
Abstract: technologies disclosed herein provide an apparatus comprising a fuse controller coupled to an aggregator. the fuse controller includes a plurality of fuses for storing a unique identifier of a device and a first secured value of a first password associated with the unique identifier. the aggregator is to receive the unique identifier and the first secured value from the fuse controller, send the unique identifier to an unlock host, receive a second password from the unlock host, compute a second secured value of the second password using a security function, and unlock one or more privileged features on the device based on the first secured value corresponding to the second secured value. in a specific embodiment, the first secured value corresponds to the second secured value if the first password is equivalent to the second password.
Inventor(s): SANTOSH GHOSH of Hillsboro OR (US) for intel corporation, MANOJ SASTRY of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32
Abstract: in one example an apparatus comprises receive, in a processing platform, an input request from a remote device comprising a digital signature signing or verify function and determine a selected digital signature scheme for the request based at least in part on a determination of whether the processing platform is to apply a signing function or a verify function to the input request. other examples may be described.
Inventor(s): John J. Browne of Limerick (IE) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Adrian Hoban of Cratloe (IE) for intel corporation, Mats Agerstam of Portland OR (US) for intel corporation, Shekar Ramachandran of Bangalore (IN) for intel corporation, Thijs Metsch of Bruehl (DE) for intel corporation, Timothy Verrall of Pleasant Hill CA (US) for intel corporation, Ciara Loftus of Tuam (IE) for intel corporation, Emma Collins of Limerick (IE) for intel corporation, Krzysztof Kepka of Gdansk (PL) for intel corporation, Pawel Zak of Gdansk (PL) for intel corporation, Aibhne Breathnach of Waterford (IE) for intel corporation, Ivens Zambrano of Ennis (IE) for intel corporation, Shanshu Yang of Dublin (IE) for intel corporation
IPC Code(s): H04L41/0654, H04L41/0806
Abstract: methods, apparatus, and systems are disclosed for mapping active assurance intents to resource orchestration and life cycle management. an example apparatus disclosed herein is to reserve a probe on a compute device in a cluster of compute devices based on a request to satisfy a resource availability criterion associated with a resource of the cluster, apply a risk mitigation operation based on the resource availability criterion before deployment of a workload to the cluster, and monitor whether the criterion is satisfied based on data from the probe after deployment of the workload to the cluster.
20240031289.NETWORK INTERFACE DEVICE LOOK-UP OPERATIONS_simplified_abstract_(intel corporation)
Inventor(s): Arunkumar BALAKRISHNAN of Santa Clara CA (US) for intel corporation, Anurag AGRAWAL of Santa Clara CA (US) for intel corporation, Elazar COHEN of Haifa (IL) for intel corporation, Anjali Singhai JAIN of Portland OR (US) for intel corporation
IPC Code(s): H04L45/748, H04L45/00, H04L12/46
Abstract: examples described herein relate to a network interface device. the network interface device can include circuitry that is to: perform a route lookup for a packet based on first and second lookup operations, wherein the first lookup operation comprises a longest prefix match (lpm) to output a route identifier based on a destination internet protocol (ip) address of the packet and wherein the second look up operation comprises an exact match operation to determine an action based on the route identifier and a packet header.
20240031308.Circuits And Methods For Multi-Layered Networks_simplified_abstract_(intel corporation)
Inventor(s): Rahul Pal of Bangalore (IN) for intel corporation, Ashish Gupta of San Jose CA (US) for intel corporation, Keong Hong Oh of Bayan Lepas (MY) for intel corporation, Gia Thuyet Ngo of George Town (MY) for intel corporation, Vikrant Kapila of Singapore (SG) for intel corporation, Ankita Roy of Kolkata (IN) for intel corporation
IPC Code(s): H04L49/109
Abstract: an integrated circuit includes a core region of logic circuits and a network routed outside the core region. the network includes a wide layer and a narrow layer. the wide layer comprises first routers coupled in series. the narrow layer comprises second routers coupled in series.
Inventor(s): Shih-wei Chien of Zhubei (TW) for intel corporation, Nagabhushan Chitlur of Portland OR (US) for intel corporation, Ajay Gupta of Portland OR (US) for intel corporation, Pradeep Nagarajan of San Jose CA (US) for intel corporation
IPC Code(s): H04L69/16, H04L69/22
Abstract: systems or methods of the present disclosure may provide receiving a request to perform an operation on data. a data payload of the data is then transmitted to a programmable logic device using a first transfer to enable offloading of at least a portion of the operation. then, a descriptor corresponding to a storage location of the data payload in the programmable logic device is received. using memory accesses one or more headers are added to the data payload in the storage location. finally, the descriptor corresponding to the data payload is transmitted without the data payload to the programmable logic device to cause the programmable logic device to transmit packets comprising the data payload and the one or more headers over a network.
20240031534.COMMUNICATION USING INTERACTIVE AVATARS_simplified_abstract_(intel corporation)
Inventor(s): Xiaofeng Tong of Beijing (CN) for intel corporation, Wenlong Li of Beijing (CN) for intel corporation, Yangzhou Du of Beijing (CN) for intel corporation, Wei Hu of Beijing (CN) for intel corporation, Yimin Zhang of Beijing (CN) for intel corporation
IPC Code(s): H04N7/15, H04M1/72439, G06V40/16, G06T13/40, H04N7/14, G06F3/0482, G06F3/04883, G10L21/003, G10L21/013
Abstract: generally this disclosure describes a video communication system that replaces actual live images of the participating users with animated avatars. a method may include selecting an avatar; initiating communication; detecting a user input; identifying the user input; identifying an animation command based on the user input; generating avatar parameters; and transmitting at least one of the animation command and the avatar parameters.
20240031777.GROUP ADDRESSED DATA DELIVERY_simplified_abstract_(intel corporation)
Inventor(s): Po-Kai Huang of San Jose CA (US) for intel corporation, Daniel Bravo of Portland OR (US) for intel corporation, Danny Ben-Ari of Tsur Natan (IL) for intel corporation, Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Amir Hitron of Beit Ytzhak (IL) for intel corporation, Ofer Schreiber of Kiryat Ono (IL) for intel corporation, Arik Klein of Givaat Shmuel (IL) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W4/06
Abstract: this disclosure describes systems, methods, and devices related to group addressed data delivery. a device may determine a plurality of links between one or more access points (aps) in an ap multi-link device (mld) and one or more logical non-ap stations (stas) in a non-ap mld. the device may determine one or more group addressed frames to be sent from the one or more aps of the ap mld to the one or more non-ap stas of the non-ap mld. the device may generate a delivery traffic indication map (dtim) associated with each link to be used by the one or more non-ap stas of the non-ap mld to receive group addressed frames. the device may perform an action based on whether the non-ap mld sent an indication that a first link of the plurality of links is selected by the non-ap mld for receiving a first group addressed frame from the one or more group addressed frames.
Inventor(s): Qinghua Li of San Ramon CA (US) for intel corporation, Feng Jiang of Santa Clara CA (US) for intel corporation, Jonathan Segev of Sunnyvale CA (US) for intel corporation, Xiaogang Chen of Portland OR (US) for intel corporation, Assaf Gurevitz of Ramat Hasharon (IL) for intel corporation, Gadi Shor of Tel Aviv (IL) for intel corporation, Robert Stacey of Portland OR (US) for intel corporation
IPC Code(s): H04W12/63, H04W12/50, H04W24/10, H04L5/00, H04W12/122, H04B17/309
Abstract: this disclosure describes systems, methods, and devices related to enhanced feedback for secure mode wireless communications. a device may send a first null data packet (ndp) to a second device, and identify a second ndp received from the second device. the device may identify a location measurement report (lmr) received from the second device, the lmr including a first channel response indicative of a first arrival time of the first ndp at the second device and a first phase shift associated with the first ndp. the device may generate a second channel response indicative of a second arrival time of the second ndp at the device and a second phase shift associated with the second ndp. the device may determine that the first channel response does not match the second channel response, and may identify an attempted attack.
Inventor(s): Po-Kai Huang of San Jose CA (US) for intel corporation, Daniel F. Bravo of Portland OR (US) for intel corporation, Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Arik Klein of Givaat Shmuel (IL) for intel corporation, Danny Ben-Ari of Tsur Natan (IL) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Robert Stacey of Portland OR (US) for intel corporation
IPC Code(s): H04W24/04, H04W24/10, H04W28/06, H04W84/12, H04W72/51, H04W72/54
Abstract: this disclosure describes systems, methods, and devices related to high throughput (ht) control information. a device may determine a frame comprising ht control information. the device may determine to extend a size of the ht control information. the device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (ht) control information, define a new control identification (id) associated with the extended ht control information, and cause to send the management or data frame to the first station device.
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Minyoung Park of San Ramon CA (US) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation, Alexander Min of Portland OR (US) for intel corporation
IPC Code(s): H04W28/12, H04W28/02, H04W40/24, H04L1/1607
Abstract: this disclosure describes systems, methods, and devices related to multi-link traffic steering. a device may establish one or more links with a station multi-link device (sta mld), wherein the sta mld comprises one or more logical entities defining separate station devices. the device may generate a traffic indication map (tim) bitmap of a plurality of bits, wherein one or more bits are associated with an association identification (aid) corresponding to the sta mld. the device may set the one or more bits to a first value to indicate that there is data to be retrieved by the sta mld on any of the one or more links. the device may generate one or more beacon frames each comprising a same tim element, wherein the tim element comprises the tim bitmap. the device may cause to send one or more beacon frames on each of the one or more links.
20240032120.METHODS AND ARRANGEMENTS FOR SECURE SENSING_simplified_abstract_(intel corporation)
Inventor(s): Cheng Chen of Camas WA (US) for intel corporation, Carlos Cordeiro of Camas WA (US) for intel corporation
IPC Code(s): H04W76/11
Abstract: logic to generate and/or parse a sensing measurement request frame comprising a secure long training field (ltf) parameters element to negotiate a secure sensing session, wherein the secure ltf parameters element comprises a secure ltf counter field, the secure ltf counter field comprising a value to determine a randomized ltf sequence. logic to cause transmission of the sensing measurement request frame to a non-ap sta. logic to generate a sensing measurement response frame. logic cause transmission of the sensing measurement response frame to an ap sta. logic to generate or parse a sensing responder to sensing initiator (sr2si) sounding trigger frame, wherein the sr2si sounding trigger frame comprises a type field and a subtype field to indicate the trigger frame comprises a sr2si sounding trigger frame.
Inventor(s): Sandeep AHUJA of Portland OR (US) for intel corporation, Je-Young CHANG of Tempe AZ (US) for intel corporation, Max KLEMES of Hillsboro OR (US) for intel corporation, Arpita MITRA of Chandler AZ (US) for intel corporation
IPC Code(s): H05K7/20
Abstract: an apparatus is described. the apparatus includes a chamber to contain one or more electronic components, a first liquid and a second liquid. the electronics to be immersed in the second liquid. the first liquid having less density than the second liquid so that the first liquid floats above the second liquid. the first liquid to return second liquid molecules received from the second liquid back to the second liquid. the chamber comprising a first fluidic channel to drain the first liquid from the chamber while the second liquid is within the chamber.
- Intel Corporation
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- Intel corporation
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