Intel Corporation patent applications on February 6th, 2025
Patent Applications by Intel Corporation on February 6th, 2025
Intel Corporation: 24 patent applications
Intel Corporation has applied for patents in the areas of G06N3/04 (3), G06N3/08 (3), G02B6/42 (2), G06N3/082 (2), G02B6/43 (2) B25J9/1612 (1), H01Q1/2266 (1), H05K7/205 (1), H04W52/146 (1), H04W12/60 (1)
With keywords such as: device, layer, based, data, network, interconnect, convolutional, heat, die, and line in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Raymundo VAZQUEZ LUGO of Zapopan (MX) for intel corporation, Julio Cesar ZAMORA ESQUIVEL of Sacramento CA (US) for intel corporation, Edgar MACIAS GARCIA of Zacapu (MX) for intel corporation, Cornelius BUERKLE of Karlsruhe (DE) for intel corporation
IPC Code(s): B25J9/16, B25J13/08, G06T7/50, G06T7/73, G06V20/50, G06V20/70
CPC Code(s): B25J9/1612
Abstract: disclosed herein are systems, devices, and methods for labelling images with grasp points and/or task-related information. the system may receive sensor data of an observed grasping of an object by a hand. the system may also determine, based on the sensor data of the observed grasping of the object, a manipulation point in relation to the object. the system may also create a data label for the object, wherein the data label indicates the manipulation point for the object. the system may also control a robot to grasp an item at a grasping point based on the manipulation point in the data label.
Inventor(s): Xavier F. Brun of Hillsboro OR (US) for intel corporation, Jonas G. Croissant of Maricopa AZ (US) for intel corporation
IPC Code(s): G02B6/42, G02B6/43
CPC Code(s): G02B6/4243
Abstract: in an illustrative embodiment, mechanical adhesive and a separate index-matching material are used as underfill between a photonic integrated circuit (pic) die and an optical interposer. the index-matching material reduces coupling loss between waveguides of the pic die and waveguides of the optical interposer, while the mechanical adhesive secures the optical interposer in place. the mechanical adhesive can be thermally cured, have a low coefficient of thermal expansion (cte), have high viscosity, and have a relatively high optical transmission loss. the index-matching material can have low optical transmission loss, be uv cured, have a relatively high cte, and have low viscosity. the combination of mechanical adhesive and index-matching material can improve ease of manufacture and yield. additional features are disclosed, such as v-groove arrays in the optical interposer and the pic die that have low stress and trenches and walls to control flow of the mechanical adhesive and/or index-matching material.
Inventor(s): Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation
IPC Code(s): G02B6/43, G02B6/42
CPC Code(s): G02B6/43
Abstract: a tunable edge-coupled interface for photonic integrated circuits (pics). the architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the pic die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the pic, (3) actuator beams flanking the waveguide beams, the actuator beams include a heating element and are operated to tune the edge interface by inducing deflection of the edge interface, and (4) an application-specific target pitch of waveguides on the edge interface.
Inventor(s): Raghavendra RAO of Bangalore (IN) for intel corporation, Venkata Mahesh GUNNAM of Mandapeta (IN) for intel corporation, Eliad Adi KLEIN of Sunnyvale CA (US) for intel corporation, David HINES of Cameron Park CA (US) for intel corporation
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/1678
Abstract: examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. the configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.
Inventor(s): Yaniv Fais of Tel Aviv TA (IL) for intel corporation, Moshe Maor of Kiryat Mozking Z (IL) for intel corporation
IPC Code(s): G06N3/04, G06F8/41, G06F17/15, G06N3/063
CPC Code(s): G06N3/04
Abstract: an example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.
Inventor(s): Anbang YAO of Beijing (CN) for intel corporation, Yikai WANG of Shanghai (CN) for intel corporation, Zhaole SUN of Shanghai (CN) for intel corporation, Yi YANG of Shanghai (CN) for intel corporation, Feng CHEN of Shanghai (CN) for intel corporation, Zhuo WANG of Beijing (CN) for intel corporation, Shandong WANG of Beijing (CN) for intel corporation, Yurong CHEN of Beijing (CN) for intel corporation
IPC Code(s): G06N3/0495, G06N3/0464
CPC Code(s): G06N3/0495
Abstract: the disclosure relates to decimal-bit network quantization of cnn models. methods, apparatus, systems, and articles of manufacture for quantizing a cnn model includes, for a convolutional layer of the cnn model: allocating a 1-bit convolutional kernel subset to the convolutional layer, wherein the convolutional layer includes 32-bit or 16-bit floating-point convolutional kernels with a size of k�k and the 1-bit convolutional kernel subset includes 21-bit convolutional kernel candidates with the size of k�k, 1≤n<k�k and both k and n being positive integers; and performing weights quantization of the convolutional layer by selecting 1-bit convolutional kernel candidates from the 1-bit convolutional kernel subset as 1-bit convolutional kernels of the convolutional layer
20250045582. DYNAMIC NEURAL NETWORK SURGERY_simplified_abstract_(intel corporation)
Inventor(s): Anbang Yao of Beijing (CN) for intel corporation, Yiwen Guo of Beijing 11 (CN) for intel corporation, Yan Li of Beijing (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation
IPC Code(s): G06N3/08, G06N3/04, G06N3/045, G06N3/082
CPC Code(s): G06N3/08
Abstract: techniques related to compressing a pre-trained dense deep neural network to a sparsely connected deep neural network for efficient implementation are discussed. such techniques may include iteratively pruning and splicing available connections between adjacent layers of the deep neural network and updating weights corresponding to both currently disconnected and currently connected connections between the adjacent layers.
Inventor(s): Hengyu MENG of Shanghai (CN) for intel corporation, Jiong GONG of Shanghai (CN) for intel corporation, Xudong LIU of Shanghai (CN) for intel corporation, Haihao SHEN of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/082
CPC Code(s): G06N3/082
Abstract: the application provides a method and apparatus for accelerating deep learning inference based on a hw-aware sparsity pattern. the method may include determining a hardware-aware sparsity pattern based on a register width specified by an isa of a hardware unit for implementing the dnn for deep learning inference, the sparsity pattern specifying a block size and a sparsity ratio for block-wise sparsification of a weight matrix of an operator in the dnn; performing the block-wise sparsification for the weight matrix based on the sparsity pattern to obtain a sparse weight matrix, during a training process of the dnn; compressing the sparse weight matrix into a concentrated weight matrix by removing all-zero blocks from the sparse weight matrix; and generating a mask to indicate an index of each row of non-zero blocks in the sparse weight matrix to enable extraction of corresponding elements from an activation matrix of the operator.
Inventor(s): Attila Tamas Afra of Satu Mare (RO) for intel corporation
IPC Code(s): G06T5/92, G06F9/38, G06F17/11, G06N3/04, G06N3/08, G06T5/70
CPC Code(s): G06T5/92
Abstract: systems and methods for tone mapping of high dynamic range (hdr) images for high-quality deep learning based processing are disclosed. in one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. the execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.
20250046001. MULTI-TILE GRAPHICS PROCESSOR RENDERING_simplified_abstract_(intel corporation)
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Arthur Hunter of Cameron Park CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Scott Janus of Loomis CA (US) for intel corporation, Brent Insko of Portland OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/00, G06T1/20, G06T1/60, G06T17/20
CPC Code(s): G06T15/005
Abstract: embodiments are generally directed to multi-tile graphics processor rendering. an embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (gpu) to process data, wherein the gpu includes a plurality of gpu tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of gpu tiles.
Inventor(s): Adam Kupryjanow of Gdansk (PL) for intel corporation, Tomasz Noczynski of Gdansk (PL) for intel corporation, Lukasz Pindor of Pruszcz Gdanski (PL) for intel corporation, Sebastian Rosenkiewicz of Gdansk (PL) for intel corporation
IPC Code(s): G10L15/20, G10L15/16
CPC Code(s): G10L15/20
Abstract: a system, method and computer readable medium for dynamic noise reduction in a voice call. the system includes an encoder having a short-time fourier transform module to determine a magnitude spectrum and a phase spectrum of an input audio signal. the input audio signal includes speech and dynamic noise. a separator is coupled to the encoder. the separator comprises a temporal convolution network (tcn) used to develop a separation mask using the magnitude spectrum as input. the tcn is trained using a frequency snr function used to calculate loss during training. a mixer is coupled to the separator to multiply the separation mask with the magnitude spectrum to separate the speech from the dynamic noise to obtain a denoise magnitude spectrum. the system also includes a decoder coupled to the mixer and the encoder. the decoder includes an inverse short-time fourier transform module to reconstruct the input audio signal without the dynamic noise using the denoise magnitude spectrum and the phase spectrum.
20250046680. EMBEDDED BRIDGE WITH THROUGH-SILICON VIAS_simplified_abstract_(intel corporation)
Inventor(s): Aditya S. VAIDYA of Gilbert AZ (US) for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ (US) for intel corporation, Digvijay A. RAORANE of Chandler AZ (US) for intel corporation, Paul R. START of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/768, H01L23/00, H01L23/498, H01L23/538, H01L25/065, H01L25/16
CPC Code(s): H01L23/481
Abstract: an integrated circuit (ic) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. the bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. the-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. the plurality of vias interconnect ones of the first plurality of pads to ones of the second plurality of pads. the bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
Inventor(s): Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Reken PATEL of Portland OR (US) for intel corporation, Richard E. SCHENKER of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/02, H01L21/027, H01L21/311, H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L23/5283
Abstract: self-aligned patterning with colored blocking and resulting structures are described. in an example, an integrated circuit structure includes an inter-layer dielectric (ild) layer above a substrate, and a hardmask layer on the ild layer. a plurality of conductive interconnect lines is in and spaced apart by the ild layer and the hardmask layer. the plurality of conductive interconnect lines includes a first interconnect line having a first width. a second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. a third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. a fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.
Inventor(s): Bala SUBRAMANYA of Bangalore (IN) for intel corporation, Prakash KURMA RAJU of Bangalore (IN) for intel corporation, Jayprakash THAKUR of Bangalore (IN) for intel corporation, Zaman Zaid MULLA of Mumbai (IN) for intel corporation, Praveen KUMAR of Bangalore (IN) for intel corporation, Yagnesh Vinodrai WAGHELA of Bangalore (IN) for intel corporation, Maruti TAMRAKAR of Chhattisgarh (IN) for intel corporation, Prasanna PICHUMANI of Bangalore (IN) for intel corporation, Harry SKINNER of Beaverton OR (US) for intel corporation
IPC Code(s): H01Q1/22, H01Q1/40, H01Q1/48, H01Q1/52
CPC Code(s): H01Q1/2266
Abstract: disclosed herein is an encapsulated antenna for reducing the impact of radio frequency interference (rfi) that may couple to the antenna at frequencies within the wi-fi 5/6e bandwidths. the encapsulated antenna device may include an insulating housing and a metal layer arranged within a cavity of the housing. the encapsulated antenna device also includes an antenna device comprising a ground terminal and an antenna body, wherein the ground terminal is connected to the metal layer, wherein the antenna body is arranged above the metal layer and within the cavity. the encapsulated antenna device also includes a spacer between the metal layer and the antenna body that provides an offset distance between the metal layer and the antenna body.
20250047436. DMRS CONFIGURATION FOR SMALL DATA TRANSMISSIONS_simplified_abstract_(intel corporation)
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation
IPC Code(s): H04L5/00, H04B7/06, H04L1/1812, H04W74/0836
CPC Code(s): H04L5/0048
Abstract: a computer-readable storage medium stores instructions to configure a ue for a configured grant-based small data transmission (cg-sdt) in the 5g nr network. a plurality of ssbs transmitted from a base station using a corresponding plurality of transmit beams is decoded. an ssb of the plurality of ssbs is selected based on signal strength for each of the plurality of transmit beams. a dmrs resource index is determined for a dmrs resource based on a mapping of the ssb and the dmrs resource. a dmrs sequence is determined based on the dmrs resource index. uplink data is encoded for a cg physical uplink shared channel (cg-pusch) transmission with the dmrs sequence during a pusch occasion configured by the base station.
Inventor(s): Daniel BRAVO of Portland OR (US) for intel corporation, Po-Kai HUANG of San Jose CA (US) for intel corporation, Danny ALEXANDER of Neve Efraim Monoson (IL) for intel corporation, Johannes BERG of Detmold (DE) for intel corporation, Ido OUZIELI of Tel Aviv (IL) for intel corporation, Ilan PEER of Modiin (IL) for intel corporation
IPC Code(s): H04L69/22
CPC Code(s): H04L69/22
Abstract: this disclosure describes systems, methods, and devices related to secure mac header. a device may generate a frame comprising a secure medium access control (mac) header. the device may cause to send the frame to one or more stas. in particular, the device may include processing circuitry coupled to storage, where the processing circuitry is configured to generate a frame comprising a mac header that includes one or more unencrypted fields and one or more encrypted fields. the frame may be one of a management frame or a data frame and the one or more unencrypted fields may include an address 3 (a3) field. the processing circuitry may also be configured to instruct to send the frame to one or more stations (stas).
20250047765. DEVICE-TO-DEVICE LINK TRAINING_simplified_abstract_(intel corporation)
Inventor(s): Kent C. LUSTED of Aloha OR (US) for intel corporation
IPC Code(s): H04L69/24, H04L49/00, H04L49/351, H04L69/324
CPC Code(s): H04L69/24
Abstract: examples described herein relate to a network interface comprising physical medium dependent (pmd) circuitry, the pmd circuitry to during link training of at least one lane consistent with ieee 802.3, exit to time_out state during train_local state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. in some examples, during link training for at least one lane consistent with ieee 802.3, the pmd circuitry is to exit to time_out state during train_remote state based on consideration of expiration of a wait timer, loss of local_tf_lock state, and loss of remote_tf_lock state. in some examples, link training consistent with ieee 802.3 comprises performance of the pmd control function in section 162.8.11 of ieee 802.3ck.
Inventor(s): Ximin Zhang of San Jose CA (US) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Sang-hee Lee of San Jose CA (US) for intel corporation, Keith Rowe of Shingle Springs CA (US) for intel corporation
IPC Code(s): H04N19/124, H04N19/119, H04N19/167, H04N19/172
CPC Code(s): H04N19/124
Abstract: techniques related to adaptive quality boosting for low latency video coding are discussed. such techniques include segmenting each of a number of temporally adjacent video frames into unique high encode quality regions and encoding each of the video frames by applying a coding quality boost to the high encode quality regions relative to other regions of the video frames.
Inventor(s): Piotr Klinke of Szczecin (PL) for intel corporation, Damian Koszewski of Gdansk (PL) for intel corporation, Przemyslaw Maziewski of Gdansk (PL) for intel corporation, Jan Banas of Gdansk (PL) for intel corporation, Kuba Lopatka of Gdansk (PL) for intel corporation, Adam Kupryjanow of Gdansk (PL) for intel corporation, Pawel Trella of Gdansk (PL) for intel corporation, Pawel Pach of Gdansk (PL) for intel corporation
IPC Code(s): H04R29/00, G01S11/14, G06N3/08, G10L21/0208, G10L21/0232, G10L25/30, G10L25/51, H04R1/08
CPC Code(s): H04R29/004
Abstract: apparatus, systems, methods, and articles of manufacture are disclosed for acoustic signal processing adaptive to microphone distances. an example system includes a microphone to convert an acoustic signal to an electrical signal and one or more processors to: estimate a distance between a source of the acoustic signal and the microphone; select a signal processing mode based on the distance; and process the electrical signal in accordance with the selected processing mode.
Inventor(s): Abhijeet KOLEKAR of Leander TX (US) for intel corporation
IPC Code(s): H04W12/02, H04W12/08
CPC Code(s): H04W12/02
Abstract: this disclosure describes systems, methods, and devices related to sensing authorization. a device may transmit a request for sensing services to a network, the request including one or more parameters related to sensing. the device may receive an authorization response from the network based on a ue's subscription status and privacy settings. the device may execute sensing functions locally on the ue upon receiving authorization from the network. the device may transmit sensing data to the network for exposure to authorized clients. the device may update a ue's privacy profile related to sensing data via a communication with a network function.
Inventor(s): Ido OUZIELI of Tel Aviv (IL) for intel corporation, Po-Kai HUANG of San Ramon CA (US) for intel corporation, Johannes BERG of Detmold (DE) for intel corporation
IPC Code(s): H04W12/60, H04L9/40, H04W84/14
CPC Code(s): H04W12/60
Abstract: this disclosure describes systems, methods, and devices related to enhanced capability advertising. a device may send a beacon frame or a probe response frame on a legacy band, including an enhanced security element containing one or more fields of an original robust security network element (rsne). the device may override at least one of the one or more fields from the enhanced security element over corresponding fields in the original rsne during a connection establishment process with a peer device.
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation, Gregory Ermolaev of Nizhny Novgorod (NZ) for intel corporation, Dong Han of San Jose CA (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Sergey Sosnin of Zavolzhie (NZ) for intel corporation
IPC Code(s): H04W52/14, H04L5/16, H04W52/32, H04W52/58
CPC Code(s): H04W52/146
Abstract: a user equipment (ue) may determine one or more nominal time-domain windows (tdws) for demodulation reference signals (dmrs) bundling for physical uplink control channel (pucch) transmissions of a pucch repetition. a start of a new actual tdw for the dmrs bunding is determined in response to an event which causes power consistency and phase continuity not to be maintained across the pucch transmissions of the pucch repetition. the ue may maintain power consistency and phase continuity within the new actual tdw across two pucch transmissions of the pucch repetition. the event may comprise a use of different power control parameters for the two of the pucch transmissions of the pucch repetition within one of the nominal tdws.
Inventor(s): Baomin Liu of Hillsboro TX (US) for intel corporation, Rob Sims of Forest Grove OR (US) for intel corporation, Kannan G. Raja of Beaverton OR (US) for intel corporation, Linden H. Mcclure of Beaverton OR (US) for intel corporation, Gopinath Kandasamy of Bangalore (IN) for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/205
Abstract: particular embodiments described herein provide for an electronic device that can be configured to include a substrate, a plurality of heat sources on the substrate, a heat spreader that extends over the plurality of heat sources, and a plurality of heat spreader mounting brackets. each of the plurality of heat spreader mounting brackets are over a corresponding heat source from the plurality of heat sources and the plurality of heat spreaders secure the heat spreader to the substrate without extending through the heat spreader. in some examples, the heat spreader is a vapor chamber and the plurality of heat spreader mounting brackets are soldered to the vapor chamber.
Inventor(s): Cory BOMBERGER of Portland OR (US) for intel corporation, Anand MURTHY of Portland OR (US) for intel corporation, Mark T. BOHR of Aloha OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L29/417, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. a first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. a second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. a conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures.
- Intel Corporation
- B25J9/16
- B25J13/08
- G06T7/50
- G06T7/73
- G06V20/50
- G06V20/70
- CPC B25J9/1612
- Intel corporation
- G02B6/42
- G02B6/43
- CPC G02B6/4243
- CPC G02B6/43
- G06F13/16
- G06F13/42
- CPC G06F13/1678
- G06N3/04
- G06F8/41
- G06F17/15
- G06N3/063
- CPC G06N3/04
- G06N3/0495
- G06N3/0464
- CPC G06N3/0495
- G06N3/08
- G06N3/045
- G06N3/082
- CPC G06N3/08
- CPC G06N3/082
- G06T5/92
- G06F9/38
- G06F17/11
- G06T5/70
- CPC G06T5/92
- G06T15/00
- G06T1/20
- G06T1/60
- G06T17/20
- CPC G06T15/005
- G10L15/20
- G10L15/16
- CPC G10L15/20
- H01L23/48
- H01L21/768
- H01L23/00
- H01L23/498
- H01L23/538
- H01L25/065
- H01L25/16
- CPC H01L23/481
- H01L23/528
- H01L21/02
- H01L21/027
- H01L21/311
- H01L23/522
- H01L23/532
- CPC H01L23/5283
- H01Q1/22
- H01Q1/40
- H01Q1/48
- H01Q1/52
- CPC H01Q1/2266
- H04L5/00
- H04B7/06
- H04L1/1812
- H04W74/0836
- CPC H04L5/0048
- H04L69/22
- CPC H04L69/22
- H04L69/24
- H04L49/00
- H04L49/351
- H04L69/324
- CPC H04L69/24
- H04N19/124
- H04N19/119
- H04N19/167
- H04N19/172
- CPC H04N19/124
- H04R29/00
- G01S11/14
- G10L21/0208
- G10L21/0232
- G10L25/30
- G10L25/51
- H04R1/08
- CPC H04R29/004
- H04W12/02
- H04W12/08
- CPC H04W12/02
- H04W12/60
- H04L9/40
- H04W84/14
- CPC H04W12/60
- H04W52/14
- H04L5/16
- H04W52/32
- H04W52/58
- CPC H04W52/146
- H05K7/20
- G06F1/20
- CPC H05K7/205
- H01L29/08
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/78
- CPC H01L29/0847
