Intel Corporation patent applications on February 29th, 2024
Patent Applications by Intel Corporation on February 29th, 2024
Intel Corporation: 49 patent applications
Intel Corporation has applied for patents in the areas of H01L23/15 (8), H01L23/00 (7), H01L23/528 (6), H01L23/498 (6), H01L23/49822 (5)
With keywords such as: substrate, layer, device, core, interconnect, circuitry, die, configured, memory, and package in patent application abstracts.
See the following report for Intel Corporation patent applications published on February 29th, 2024:
Intel Corporation patent applications on February 29th, 2024
Patent Applications by Intel Corporation
Inventor(s): Fanyi ZHU of Chandler AZ (US) for intel corporation, Hanyu SONG of Chandler AZ (US) for intel corporation
IPC Code(s): B05D3/06, B05D1/12, H05K3/02
Abstract: there may be provided a material deposition method and a material deposition apparatus. the method may include providing a substrate. the method may further include providing a layer of a material in a solid form onto the substrate. the material in the solid form may be loosely interfacing with the substrate. the method may further include irradiating the material in a solid form with a light to melt the material in the solid form to the material in a liquid form at one or more specific areas of the substrate. the method may further include cooling the material in the liquid form to a solidified material on the substrate. the solidified material may form a pattern, at the one or more specific areas of the substrate, that adheres to the substrate.
20240066698.REAL-TIME MOTION AND PATH PLANNER FOR ROBOTS_simplified_abstract_(intel corporation)
Inventor(s): Leobardo Emmanuel CAMPOS MACIAS of Guadalajara (MX) for intel corporation
IPC Code(s): B25J9/16, B25J13/08
Abstract: disclosed herein are systems, devices, and methods for real-time motion and path planning. the real-time motion and path planner may generate occupancy information about an environment around a robot. the occupancy information represents defined volumes of space of the environment, and each defined volume of space is associated with a corresponding occupancy probability. the motion/path planner also determines a sequence of robot configurations between a starting and a target configuration based on the occupancy information, wherein the sequence of robot configurations defines poses of the robot that occupy selected ones of the defined volumes of space. the motion/path planner also generates an instruction for the robot based on the sequence of robot configurations, wherein the instruction includes trajectory information to control the robot to move from the starting configuration to the target configuration through the sequence of robot configurations.
Inventor(s): Paul DIGLIO of Gaston OR (US) for intel corporation, Craig YOST of Gilbert AZ (US) for intel corporation, Christopher Wade ACKERMAN of Phoenix AZ (US) for intel corporation
IPC Code(s): F16J15/328
Abstract: the present disclosure is directed to a system having a first loading component and a second loading component for applying load to a device during a test of the device, the first loading component is configured to be moveable with respect to the second loading component. the system includes a seal member arranged between the first loading component and the second loading component, the seal member is adapted to engage the device diming testing so as to apply a load against the device during testing and provide sealing around a cavity positioned below the first loading component and above the device.
Inventor(s): Xiaoguo LIANG of Shanghai (CN) for intel corporation, Farzaneh YAHYAEI-MOAYYED of Chandler AZ (US) for intel corporation, Nazar HAIDER of Fremont CA (US) for intel corporation, Nishi AHUJA of Portland OR (US) for intel corporation, Jie YAN of Shanghai (CN) for intel corporation, Julio C. CINCO GALICIA of Zapopan, JAL (MX) for intel corporation
IPC Code(s): G01R19/10
Abstract: techniques and mechanisms for sensing a voltage difference across two interconnect structures of a multi-chip packaged device. in an embodiment, the interconnect structures provide respective voltages to each of multiple integrated circuit (ic) chips of the packaged device. switch circuitry of the packaged device is operable to provide any of multiple modes which each switchedly couple a voltage sensor to a different respective one of various sample point pairs of the interconnect structures. control circuitry operates the switch circuitry to selectively provide one of the multiple modes based on an indication of a workload to be performed with one or more of the ic chips. in another embodiment, the voltage sensor senses the voltages each at a respective sample point of a sample point pair which corresponds to the selected mode of the switch circuitry.
Inventor(s): Huei Hao YAP of Albuquerque NM (US) for intel corporation, Gavin CORCORAN of Albuquerque NM (US) for intel corporation, Jungwon KIM of Albuquerque NM (US) for intel corporation, Seung Hwan LEE of Albuquerque NM (US) for intel corporation, Mark GRUIDL of Rio Rancho NM (US) for intel corporation, Karthik KALAIAZHAGAN of Albuquerque NM (US) for intel corporation, Youren XU of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G01R31/311, G01Q10/04, G01Q20/02, G01Q60/38
Abstract: the present disclosure is directed to an inspection tool having an integrated optical laser unit and atomic force probe unit with a detector unit. the inspection tool further includes a processor unit that is coupled to the optical laser unit and the atomic force probe unit and performs a fault location analysis for a device under test. in addition, the present disclosure to methods for inspecting a device under test for defects using an inspection tool having an integrated optical laser unit and atomic force probe unit that includes a detector unit.
Inventor(s): Vinod ADIVARAHAN of Chandler AZ (US) for intel corporation, Liqiang CUI of Shenzhen, Guangdong (CN) for intel corporation, Aditi MALLIK of Cupertino CA (US) for intel corporation, Boping XIE of San Ramon CA (US) for intel corporation, Sunil PRIYADARSHI of Sunnyvale CA (US) for intel corporation
IPC Code(s): G02B6/36
Abstract: a fiber array unit () and a photonics system (), a fiber array unit () comprises a substrate () with a first el end and a second end. a first mesa () is adjacent to the first end and a second mesa () is adjacent to the second end. a v-groove () is in the first mesa () and a slot () is in the second mesa (). the v-groove () is aligned with the slot ().
20240069433.REPAIR METHOD FOR PHOTOMASK DEFECTS_simplified_abstract_(intel corporation)
Inventor(s): Juan Pablo OVIEDO ROBLES of Santa Clara CA (US) for intel corporation, Raja KATTA of San Jose CA (US) for intel corporation
IPC Code(s): G03F1/74, G03F1/84
Abstract: the present disclosure is directed to a repair method including providing a scanning electron microscope (sem) with an electron beam directed at a defective multilayer photomask disposed in the sem; disposing a droplet of a liquid precursor on a surface of the defective multilayer photomask with a defect; pointing a gas flow on the droplet, wherein the gas flow is configured to planarize the droplet; and repairing the defect in the defective multilayer photomask by performing a chemical reaction on the planarized droplet. a photomask repair system and a photomask repair tool is also provided.
Inventor(s): Deepak SELVANATHAN of Portland OR (US) for intel corporation, William T. BLANTON of Cornelius OR (US) for intel corporation, Martin WEISS of Portland OR (US) for intel corporation
IPC Code(s): G03F7/20, G03F9/00
Abstract: an apparatus of manufacturing a semiconductor device is provided. the apparatus including a controller configured to: expose a first region of a photoresist layer with a light pattern, expose a second region of the photoresist layer with at least in part the same light pattern, wherein the second region and the first region overlap in an overlap region of the photoresist layer, and wherein light pattern is configured to form, in exposing the first region, a first portion of individual markings in the overlap region of the photoresist layer, and to form, in exposing the second region, a second portion of individual markings in the overlap region of the photoresist layer. by measuring the composite pattern formed in photoresist by overlapping the first exposure with the second exposure, the relative position of the two exposures can be determined and controlled.
Inventor(s): Ko Han Wu of Taipei City (TW) for intel corporation, Thiam Wah Loh of Singapore (SG) for intel corporation, Kenneth K. Lau of Taipei (TW) for intel corporation, Wen-Kuang Yu of Taipei (TW) for intel corporation, Ming-Jiun Chang of New Taipei City (TW) for intel corporation, Andy Yeh of Taipei City (TW) for intel corporation, Wei Chih Chen of New Taipei City (TW) for intel corporation
IPC Code(s): G06F1/3234, G06F1/16, G06T1/00, H04N5/232, H04N7/18
Abstract: a method, system, and article provide image processing with power reduction while using universal serial bus cameras.
20240069737.MERGING BIT-MASK ATOMICS TO THE SAME DWORD_simplified_abstract_(intel corporation)
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation
IPC Code(s): G06F3/06
Abstract: embodiments described herein provide a technique to improve the performance of bit-wise atomic writes to the same double word address. one embodiment provides a graphics processor comprising a system interface, a graphics processor core coupled with the system interface, and circuitry to process memory access messages received from the graphics processor core. to process the memory access messages, the circuitry is configured to merge operands associated with one or more memory access messages to perform a bitwise atomic operation, the one or more memory access messages having addresses within a same 4-byte location in memory.
20240069913.Uniform Microcode Update Enumeration_simplified_abstract_(intel corporation)
Inventor(s): Avinash Chandrasekaran of Mountain View CA (US) for intel corporation, Hisham Shafi of Folsom CA (US) for intel corporation, Jeffrey G. Wiedemeier of Austin TX (US) for intel corporation
IPC Code(s): G06F9/22, G06F9/445
Abstract: systems, methods, and devices are provided for identification of model-specific behavior relating to microcode update capabilities of a processor to enable efficient microcode updates across a range of different machines. a system may include a first processor core and a second processor core. a register of the system may indicate a hardware capability of the system to perform a uniform microcode update by propagating a microcode update from the first processor core to a second processor core.
Inventor(s): Biju George of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/345, G06F9/38
Abstract: embodiments described herein provide a system to enable access to an n-dimensional tensor in memory of a graphics processor via a batch of two-dimensional block access messages. one embodiment provides a graphics processor comprising general-purpose graphics execution resources coupled with the system interface, the general-purpose graphics execution resources including a matrix accelerator. the matrix accelerator is configured to perform a matrix operation on a plurality of tensors stored in a memory. circuitry is included to facilitate access to the memory by the general-purpose graphics execution resources. the circuitry is configured to receive a request to access a tensor of the plurality of tensors and generate a batch of two-dimensional block access messages along a dimension of n>2 of the tensor. the batch of two-dimensional block access messages enables access to the tensor by the matrix accelerator.
20240069921.DYNAMICALLY RECONFIGURABLE PROCESSING CORE_simplified_abstract_(intel corporation)
Inventor(s): Scott Cline of Portland OR (US) for intel corporation, Robert Pawlowski of Beaverton OR (US) for intel corporation, Joshua Fryman of Corvallis OR (US) for intel corporation, Ivan Ganev of Portland OR (US) for intel corporation, Vincent Cave of Hillsboro OR (US) for intel corporation, Sebastian Szkoda of Gdansk (PL) for intel corporation, Fabio Checconi of Fremont CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
Abstract: technology described herein provides a dynamically reconfigurable processing core. the technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. in embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. in embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.
Inventor(s): David M. Durham of Beaverton OR (US) for intel corporation, Siddhartha Chhabra of Portland OR (US) for intel corporation, Michael E. Kounavis of Portland OR (US) for intel corporation
IPC Code(s): G06F9/455, G06F12/0891, G06F12/14, G06F21/53, G06F21/79, H04L9/40, H04L69/04
Abstract: systems and methods for memory isolation are provided. the methods include receiving a request to write a data line to a physical memory address, where the physical memory address includes a key identifier, selecting an encryption key from a key table based on the key identifier of the physical memory address, determining whether the data line is compressible, compressing the data line to generate a compressed line in response to determining that the data line is compressible, where the compressed line includes compression metadata and compressed data, adding encryption metadata to the compressed line, where the encryption metadata is indicative of the encryption key, encrypting a part of the compressed line with the encryption key to generate an encrypted line in response to adding the encryption metadata, and writing the encrypted line to a memory device at the physical memory address. other embodiments are described and claimed.
20240070091.ISOLATION OF MEMORY REGIONS IN TRUSTED DOMAIN_simplified_abstract_(intel corporation)
Inventor(s): Pradeep Pappachan of Tualatin OR (US) for intel corporation, Krystof Zmudzinski of Forest Grove OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F12/14
Abstract: an apparatus comprises a hardware processor to program a memory table for a trusted domain with a first device identifier associated with a device, a guest physical address (gpa) range associated with the device, and a guest physical address offset, receive a memory access request from the device, the memory access request comprising a second device identifier and a guest physical address, and validate the memory access request using the memory table.
Inventor(s): Srinivasan NARAYANAMOORTHY of Hillsboro OR (US) for intel corporation, Nadathur Rajagopalan SATISH of Santa Clara CA (US) for intel corporation, Alexey SUPRUN of Beaverton OR (US) for intel corporation, Kenneth J. JANIK of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F17/16, G06F7/544, G06F9/30, G06F9/38, G06N3/00
Abstract: disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. in one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row m and column k of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row k and column n of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row m and column n of the specified dense output matrix.
Inventor(s): John C. Weast of Portland OR (US) for intel corporation, Joshua Boelter of Portland OR (US) for intel corporation
IPC Code(s): G06F21/62, G06F3/14, G06F21/35, G06F21/84, G09G3/00
Abstract: technologies for displaying public and private images includes a display device and one or more user viewing devices. the display device is configured to display or generate a personalized image or video that is viewable by an authorized user viewing device and not viewable by unauthorized viewing devices. to facilitate the display of the personalized images, the display device and the user viewing device(s) may negotiate a display protocol to be used by the display device to display the personalized image in a private manner. in some embodiment, the display device may also display a public image or video that is viewable by unauthorized viewing devices and/or individuals without viewing devices.
Inventor(s): Nicholas HAEHN of Scottsdale AZ (US) for intel corporation, Raquel DE SOUZA BORGES FERREIRA of Ocala FL (US) for intel corporation, Siddharth ALUR of Chandler AZ (US) for intel corporation, Prakaram JOSHI of Gilbert AZ (US) for intel corporation, Dhanya ATHREYA of Chandler AZ (US) for intel corporation, Yidnekachew MEKONNEN of Chandler AZ (US) for intel corporation, Ali HARIRI of Phoenix AZ (US) for intel corporation, Andrea NICOLAS of Chandler AZ (US) for intel corporation, Sri Chaitra Jyotsna CHAVALI of Chandler AZ (US) for intel corporation, Kemal AYGUN of Tempe AZ (US) for intel corporation
IPC Code(s): G06F30/392, H01L23/498
Abstract: a package substrate stack modeler includes a manufacturing modeler, configured to generate a model of a real package substrate stack based on an ideal design of the package substrate stack; a signal integrity model, configured to determine a signal integrity of a metal trace of the real package substrate stack; and a yield model, configured to determine a yield of the real package substrate stack; wherein the metal trace comprises a first value of a trace variable; further comprising a processor, configured to select a second value of the trace variable of the metal trace based on the determined signal integrity of the metal trace or the determined yield of the package substrate stack model.
Inventor(s): Daniel STAHLKE of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F30/392
Abstract: the apparatuses for ic layouting comprise interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to obtain a first hierarchical ic layout comprising a first instance of a cell. the cell from which the first instance is derived comprises at least one planar geometric shape representing components of a first ic. the first instance of the cell results from applying a first geometrical transformation operation to the cell during a first instantiation of the cell. further the processing circuitry is configured to: generate a first hash code of the cell based on a hash function; and generate a second hash code of the first instance of the cell by applying a first mathematical operation to the first hash code. the first mathematical operation is corresponding to the first geometrical transformation operation applied to the cell.
20240070490.PREDICTION-ASSISTED SAMPLING CIRCUITRY_simplified_abstract_(intel corporation)
Inventor(s): SARIT ZUR of Petah-Tikva (IL) for intel corporation, Oren Ezra Avraham of Givat Shmuel (IL) for intel corporation
IPC Code(s): G06N5/04
Abstract: an apparatus can include sampling circuitry and processing circuitry coupled to the sampling circuitry. the processing circuitry can predict a next sample of an input signal and determine a predicative portion of the next sample of the input signal. the processing circuitry can subtract the predicative portion from the input signal to determine a non-predicative portion of the input signal and provide the non-predicative portion to the sampling circuitry for sampling.
Inventor(s): Dhiraj D. KALAMKAR of Bangalore (IN) for intel corporation, Karthikeyan VAIDYANATHAN of Bangalore (IN) for intel corporation, Srinivas SRIDHARAN of Bangalore (IN) for intel corporation, Dipankar DAS of Pune (IN) for intel corporation
IPC Code(s): G06T1/20, G06N3/044, G06N3/045, G06N3/063, G06N3/084
Abstract: one embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.
20240070829.DISTORTION MESHES AGAINST CHROMATIC ABERRATIONS_simplified_abstract_(intel corporation)
Inventor(s): DANIEL POHL of Saarbrücken (DE) for intel corporation
IPC Code(s): G06T5/00, G02B27/01, G06T5/50
Abstract: described herein is a technique in which a plurality of distortion meshes compensate for radial and chromatic aberrations created by optical lenses. the plurality of distortion meshes may include different lens specific parameters that allow the distortion meshes to compensate for chromatic aberrations created within received images. the plurality of distortion meshes may correspond to a red color channel, green color channel, or blue color channel to compensate for the chromatic aberrations. the distortion meshes may also include shaped distortions and grids to compensate for radial distortions, such as pin cushion distortions. in one example, the system uses a barrel-shaped distortion and a triangulation grid to compensate for the distortions created when the received image is displayed on a lens.
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Ben Ashbaugh of Folsom CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Pradeep Ramani of Milpitas CA (US) for intel corporation, Rama Harihara of Santa Clara CA (US) for intel corporation, Jerin C. Justin of San Jose CA (US) for intel corporation, Jing Huang of Chandler AZ (US) for intel corporation, Xiaoming Cui of Santa Clara CA (US) for intel corporation, Timothy B. Costa of Beaverton OR (US) for intel corporation, Ting Gong of San Jose CA (US) for intel corporation, Elmoustapha Ould-ahmed-vall of Chandler AZ (US) for intel corporation, Kumar Balasubramanian of Chandler AZ (US) for intel corporation, Anil Thomas of San Ramon CA (US) for intel corporation, Oguz H. Elibol of Sunnyvale CA (US) for intel corporation, Jayaram Bobba of Portland OR (US) for intel corporation, Guozhong Zhuang of Hillsboro OR (US) for intel corporation, Bhavani Subramanian of Hillsboro OR (US) for intel corporation, Gokce Keskin of Mountain View CA (US) for intel corporation, Chandrasekaran Sakthivel of Cupertino CA (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation
IPC Code(s): G06T9/00, G06F12/02, G06T15/00
Abstract: embodiments are generally directed to compression in machine learning and deep learning processing. an embodiment of an apparatus for compression of untyped data includes a graphical processing unit (gpu) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3d compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
Inventor(s): Nagabhushan Eswara of Bangalore (IN) for intel corporation, Jaroslaw J. Sydir of San Jose CA (US) for intel corporation, Vallabhajosyula Srinivasa Somayazulu of Portland OR (US) for intel corporation, Nilesh Ahuja of Cupertino CA (US) for intel corporation, Omesh Tickoo of Portland OR (US) for intel corporation, Parual Datta of Bangalore (IN) for intel corporation
IPC Code(s): G06V10/44, G06T3/00, G06T3/40, G06T7/20, H04N19/172
Abstract: methods and apparatus are disclosed herein for computation and compression efficiency in distributed video analytics. example apparatus disclosed herein are to identify a key frame and a non-key frame in a video frame sequence input to a neural network at a client server, determine motion information between the key frame and the non-key frame based on optical flow, and determine a frame feature representation based on the motion information reconstructed at an edge server, the motion information including feature warping residual errors.
20240071777.INTEGRATED CIRCUIT PACKAGE SUPPORTS_simplified_abstract_(intel corporation)
Inventor(s): Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Robert May of Chandler AZ (US) for intel corporation, Sri Ranga Sai Boyapati of Austin TX (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Chung Kwang Christopher Tan of Portland OR (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation
IPC Code(s): H01L21/48, H01L23/498
Abstract: disclosed herein are integrated circuit (ic) package supports and related apparatuses and methods. for example, in some embodiments, a method for forming an ic package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.
Inventor(s): Chang Wan Han of Portland OR (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, Vivek Thirtha of Portland OR (US) for intel corporation, William Hsu of Portland OR (US) for intel corporation, Ian Yang of Portland OR (US) for intel corporation, Oleg Golonzka of Beaverton OR (US) for intel corporation, Kevin J. Fischer of Hillsboro OR (US) for intel corporation, Suman Dasgupta of Beaverton OR (US) for intel corporation, Sameerah Desnavi of Hillsboro OR (US) for intel corporation, Deepak Sridhar of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/417, H01L29/423, H01L29/66, H01L29/775, H01L29/778, H01L29/786
Abstract: an integrated circuit includes laterally adjacent first and second devices. the first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. the second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. in an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. the various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure
Inventor(s): Bohan SHAN of Chandler AZ (US) for intel corporation, Haobo CHEN of Gilbert AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Bai NIE of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Kyle ARRINGTON of Gilbert AZ (US) for intel corporation, Ziyin LIN of Chandler AZ (US) for intel corporation, Hongxia FENG of Chandler AZ (US) for intel corporation, Yiqun BAI of Chandler AZ (US) for intel corporation, Xiaoying GUO of Chandler AZ (US) for intel corporation, Dingying David XU of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/498
Abstract: embodiments disclosed herein include package substrates. in an embodiment, the package substrate comprises a core, where the core comprises glass. in an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. in an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. in an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.
Inventor(s): Bok Eng CHEAH of Pulau Pinang (MY) for intel corporation, Seok Ling LIM of Kulim Kedah (MY) for intel corporation, Jenny Shio Yin ONG of Pulau Pinang (MY) for intel corporation, Jackson Chung Peng KONG of Pulau Pinang (MY) for intel corporation, Kooi Chi OOI of Pulau Pinang (MY) for intel corporation
IPC Code(s): H01L23/367, H01L23/373
Abstract: the present disclosure is directed to an electronic assembly and method of forming thereof. the electronic assembly may include a substrate and a first die with first and second opposing surfaces. the first die may be coupled to the substrate at the first surface. at least one first trench may extend partially through the first die from the second surface. a stiffener may be attached to the substrate. the stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. a thermally conductive layer may be positioned between the stiffener and the first die. the conductive layer at least partially fills the at least one first trench.
Inventor(s): Ragh KUTTAPPA of Portland OR (US) for intel corporation, Tanay KARNIK of Portland OR (US) for intel corporation, Mondira Deb PANT of Westborough MA (US) for intel corporation
IPC Code(s): H01L23/48, H01L27/088, H01L29/06, H01L29/78
Abstract: structures having magnetic vias and backside power delivery are described. in an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based or fin-based transistors of the device layer. one of the metallization layers includes one or more magnetic vias. a backside structure is below the nanowire-based or fin-based transistors of the device layer. the backside structure includes a ground metal line.
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Sashi S. KANDANUR of Phoenix AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15, H01L23/544
Abstract: embodiments disclosed herein include cores for package substrates. in an embodiment, the core comprises a first substrate, where the first substrate comprises glass. in an embodiment, the core further comprises a first through glass via (tgv) through the first substrate and a second substrate, where the second substrate comprises glass. in an embodiment, the core further comprises a second tgv through the second substrate, where the first tgv is aligned with the second tgv.
Inventor(s): Dae-Woo KIM of Phoenix AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/13, H01L23/538, H01L25/065
Abstract: alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. in an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. the substrate has a perimeter. a metallization structure is disposed on the lower insulating layer. the metallization structure includes conductive routing disposed in a dielectric material stack. first and second pluralities of conductive pads are disposed in a plane above the metallization structure. conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. an upper insulating layer is disposed on the first and second pluralities of conductive pads. the upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.
20240071913.DOUBLE-DECKED INTERCONNECT FEATURES_simplified_abstract_(intel corporation)
Inventor(s): June Choi of Portland OR (US) for intel corporation, Richard Schenker of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Nikhil J. Mehta of Portland OR (US) for intel corporation, Clifford L. Ong of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522, H01L23/532
Abstract: an integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. the first interconnect layer includes a first interconnect feature and a second interconnect feature. the second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. the third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. in an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.
20240071917.ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Richard E. SCHENKER of Portland OR (US) for intel corporation, Robert L. BRISTOL of Portland OR (US) for intel corporation, Kevin L. LIN of Beaverton OR (US) for intel corporation, Florian GSTREIN of Portland OR (US) for intel corporation, James M. BLACKWELL of Portland OR (US) for intel corporation, Marie KRYSAK of Portland OR (US) for intel corporation, Manish CHANDHOK of Beaverton OR (US) for intel corporation, Paul A. NYHUS of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Curtis W. WARD of Hillsboro OR (US) for intel corporation, Swaminathan SIVAKUMAR of Beaverton OR (US) for intel corporation, Elliot N. TAN of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522, H01L23/532, H01L27/088, H01L29/78
Abstract: advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. self-assembled devices and their methods of fabrication are described.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L23/00, H01L23/29, H01L23/31, H01L23/48, H01L25/065
Abstract: embodiments of a microelectronic assembly comprise: a first layer comprising a plurality of first integrated circuit (ic) dies in an organic dielectric material, the first layer having a first side and a second side opposite to the first side; a second layer on the first side of the first layer, the second layer comprising a second ic die in the organic dielectric material, the second ic die conductively coupling a pair of first ic dies in the plurality of first ic dies of the first layer; and a package substrate coupled to the second side of the first layer. the second ic die is coupled to the pair of first ic dies by interconnects having a pitch less than 60 micrometers between adjacent interconnects, and the pair of first ic dies comprises tsvs conductively coupling circuits in the first ic dies with the interconnects.
Inventor(s): Bok Eng CHEAH of Gelugor (MY) for intel corporation, Jenny Shio Yin ONG of Bayan Lepas (MY) for intel corporation, Jackson Chung Peng KONG of Tanjung Tokong (MY) for intel corporation, Seok Ling LIM of Kulim Kedah (MY) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/64, H01L25/065
Abstract: the present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Ravindranath V. MAHAJAN of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/15, H01L23/31, H01L23/48
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. in an embodiment, electrically conductive routing is provided in the second substrate. in an embodiment, a first die is over the second substrate, and a second die is over the second substrate. in an embodiment, the electrically conductive routing electrically couples the first die to the second die.
20240071938.CAVITY-LESS INTERCONNECT COMPONENT ON GLASS CORE_simplified_abstract_(intel corporation)
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/00, H01L23/15, H01L23/498, H01L25/065
Abstract: a glass core with a cavity-less local interconnect component architecture for complex multi-die packages. the apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. one or more redistribution layers may be located above and below the apparatus.
Inventor(s): Jiun Hann SIR of Pulau Pinang (MY) for intel corporation, Eng Huat GOH of Ayer Itam (MY) for intel corporation, Poh Boon KHOO of Pulau Pinang (MY) for intel corporation, Nurul Khalidah YUSOP of Perak (MY) for intel corporation, Saw Beng TEOH of Folsom CA (US) for intel corporation, Chan Kim LEE of Penang (MY) for intel corporation
IPC Code(s): H01L23/00, H01L23/16, H01L23/367, H01L25/00, H01L25/065
Abstract: a semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.
Inventor(s): Abhishek A. Sharma of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Shem Ogadhoh of West Linn OR (US) for intel corporation, Swaminathan Sivakumar of Beaverton OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Elliot Tan of Portland OR (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/528, H01L27/085
Abstract: described herein is full wafer device that includes a computing logic formed over a substrate and two directional indicators formed in the substrate. the computing logic is arranged as a plurality of dies having a first die edge direction and a second die edge direction perpendicular to the first die edge direction. the computing logic further includes an angled feature extending in a feature direction, the feature direction different from the first die edge direction and the second die edge direction. the first directional indicator formed in the substrate indicates the first die edge direction. the second directional indicator formed in the substrate indicates the feature direction.
Inventor(s): Megan BECK of Hillsboro OR (US) for intel corporation, Joseph BRICE of Hillsboro OR (US) for intel corporation, Ryan WOOD of Beaverton OR (US) for intel corporation, Krishna T. MARLA of Portland OR (US) for intel corporation, Derek CASELLI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/775, H01L29/78
Abstract: gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. a first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. an end of the second gate stack is spaced apart from an end of the first gate stack by a gap. the integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.
20240072419.ANTENNA MODULES AND COMMUNICATION DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Sidharth Dalmia of Portland OR (US) for intel corporation, Jonathan Jensen of Portland OR (US) for intel corporation, Ozgur Inac of Portland OR (US) for intel corporation, Trang Thai of Hillsboro OR (US) for intel corporation, William J. Lambert of Chandler AZ (US) for intel corporation, Benjamin Jann of Hillsboro OR (US) for intel corporation
IPC Code(s): H01Q1/24, H01Q1/22, H01Q9/04
Abstract: disclosed herein are integrated circuit (ic) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). for example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (rffe) die in electrical communication with the logic die; and an antenna patch, wherein the rffe die is closer to the antenna patch than the logic die is to the antenna patch.
Inventor(s): Ronen KRONFELD of Shoham (IL) for intel corporation, Rajesh JULURI of San Jose CA (US) for intel corporation, Walid EL HAJJ of Antibes (FR) for intel corporation, Wilfrid D'Angelo of Mougins (FR) for intel corporation
IPC Code(s): H01Q21/28, H01Q21/00
Abstract: a combined antenna circuitry including a multi-feed antenna including a first antenna feed, a second antenna feed, and a third antenna feed; wherein the first antenna feed is configured to be connected to a first antenna of the combined antenna circuitry and is configured to operate on a first frequency band of a first radio access technology (rat); wherein the second antenna feed is configured to be connected to a second antenna of the combined antenna circuitry and is configured to operate on a second frequency band of the first rat; and wherein the third antenna feed is configured to be connected to the second antenna of the combined antenna circuitry and is configured to operate on a frequency band of a second rat, wherein the frequency band of the second rat does not correspond to any frequencies of the second frequency band of the first rat.
Inventor(s): Sally Safwat Amin of Hillsboro OR (US) for intel corporation
IPC Code(s): H02M3/158, H02M1/00
Abstract: embodiments herein relate to a voltage converter which includes a soft switching driver for a low-side transistor which is in series with a high-side transistor to provide a desired output voltage vx. the soft switching driver receives vx on a feedback path and includes a clipper transistor to clip or reduce a maximum voltage of vx to vxsen. a restore circuit can be used to effectively add back a threshold voltage drop of the clipper transistor which would otherwise occur by holding a source of the clipper transistor at vdrv, a gate voltage of the clipper transistor. a zero-voltage switching circuit receives vxsen to provide an output voltage which in turn sets a control gate voltage of the low-side transistor. the low-side and high-side transistors may be gan-based while the soft switching driver is cmos based.
Inventor(s): Rui Huang of Beijing, 11 (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Hua Li of Arlington VA (US) for intel corporation
IPC Code(s): H04B17/27, G01S5/00, H04L27/26
Abstract: an apparatus and system for determining positioning measurement accuracy are described. a ue receives positioning reference signals (prs) from a reference cell and a neighbor cell and reference signal time difference (rstd) measurements based on the prs. rstd and other prs measurement results based on the reference and neighbor cells have rstd and other prs measurement accuracy requirements, that depend on bandwidth (bw), subcarrier spacing (scs), and repetition factor of the prs.
20240073013.HIGH PERFORMANCE SECURE IO_simplified_abstract_(intel corporation)
Inventor(s): Reshma Lal of Portland OR (US) for intel corporation, Krystof Zmudzinski of Forest Grove OR (US) for intel corporation
IPC Code(s): H04L9/08, G06F12/14
Abstract: an apparatus comprises a hardware processor to perform an attestation procedure to attest a remote device, establish a session key for a communication session with the remote device, define a linear address (la) region outside an established address range for a secure enclave, generate, for the linear address (la) region, a unique encryption key accessible only to the enclave, assign a key identifier to the unique encryption key, store the linear address (la) region and the unique encryption key in an enclave control structure, set a pending bit in the enclave control structure to a value to indicate that contents of the linear address region cannot be changed without approval from the secure enclave, clear the pending bit to indicate that the linear address range is available for use by the enclave, wrap the key identifier and the unique encryption key with the session key, and send the key identifier and the unique encryption key to the remote device.
Inventor(s): Vesh Raj Sharma Banjade of Portland OR (US) for intel corporation, S M Iftekharul Alam of Hillsboro OR (US) for intel corporation, Satish Chandra Jha of Portland OR (US) for intel corporation, Arvind Merwaday of Beaverton OR (US) for intel corporation, Kuilin Clark Chen of Portland OR (US) for intel corporation
IPC Code(s): H04L47/12, H04L47/283
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for in-network computation and control of network congestion based on in-network computation delays. an example device includes interface circuitry to access a packet including a header having (1) a destination address field to identify a first network address of a destination device capable of performing an action and (2) a workload class field to identify a workload class associated with the action. the example device also includes programmable circuitry to utilize machine-readable instructions to perform the action at the device based on the workload class field, the device having a second network address that is different than the first network address. additionally, the example programmable circuitry is to modify an indicator field of the packet to indicate that the action has been performed and cause the interface circuitry to forward the packet with the modified indicator field toward the destination device.
20240073796.METHODS AND DEVICES FOR RADIO COMMUNICATIONS_simplified_abstract_(intel corporation)
Inventor(s): Shahrnaz AZIZI of Cupertino CA (US) for intel corporation, Biljana BADIC of Munich (DE) for intel corporation, John BROWNE of Limerick (IE) for intel corporation, Dave CAVALCANTI of Portland OR (US) for intel corporation, Hyung-Nam CHOI of Hamburg (DE) for intel corporation, Thorsten CLEVORN of Munich (DE) for intel corporation, Ajay GUPTA of Portland OR (US) for intel corporation, Maruti GUPTA HYDE of Portland OR (US) for intel corporation, Ralph HASHOLZNER of Munich (DE) for intel corporation, Nageen HIMAYAT of Fremont CA (US) for intel corporation, Simon HUNT of Naples FL (US) for intel corporation, Ingolf KARLS of Feldkirchen (DE) for intel corporation, Thomas KENNEY of Portland OR (US) for intel corporation, Yiting LIAO of Sunnyvale CA (US) for intel corporation, Christopher MACNAMARA of Ballyclough (IE) for intel corporation, Marta MARTINEZ TARRADELL of Hillsboro OR (US) for intel corporation, Markus Dominik MUECK of Unterhaching (DE) for intel corporation, Venkatesan NALLAMPATTI EKAMBARAM of Hillsboro OR (US) for intel corporation, Niall POWER of Newcastle West (IE) for intel corporation, Bernhard RAAF of Neuried (DE) for intel corporation, Reinhold SCHNEIDER of Veitsbronn (DE) for intel corporation, Ashish SINGH of Munich (DE) for intel corporation, Sarabjot SINGH of Santa Clara CA (US) for intel corporation, Srikathyayani SRIKANTESWARA of Portland OR (US) for intel corporation, Shilpa TALWAR of Cupertino CA (US) for intel corporation, Feng XUE of Redwood City CA (US) for intel corporation, Zhibin YU of Unterhaching (DE) for intel corporation, Robert ZAUS of Munich (DE) for intel corporation, Stefan FRANZ of Munich (DE) for intel corporation, Uwe KLIEMANN of Rednitzhembach (DE) for intel corporation, Christian DREWES of Germering (DE) for intel corporation, Juergen KREUCHAUF of San Francisco CA (US) for intel corporation
IPC Code(s): H04W48/16, H04W4/029, H04W24/08, H04W48/10, H04W68/00, H04W92/04
Abstract: a circuit arrangement includes a preprocessing circuit configured to obtain context information related to a user location, a learning circuit configured to determine a predicted user movement based on context information related to a user location to obtain a predicted route and to determine predicted radio conditions along the predicted route, and a decision circuit configured to, based on the predicted radio conditions, identify one or more first areas expected to have a first type of radio conditions and one or more second areas expected to have a second type of radio conditions different from the first type of radio conditions and to control radio activity while traveling on the predicted route according to the one or more first areas and the one or more second areas.
Inventor(s): Alexey Khoryaev of Nizhny Novgorod (RU) for intel corporation, Mikhail Shilov of Nizhny Novgorod (RU) for intel corporation, Artyom Lomayev of Nizhny Novgorod (RU) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Kilian Peter Anton Roth of München (DE) for intel corporation, Artyom Putilin of Kstovo (RU) for intel corporation, Dmitry Belov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04W72/25, H04L1/1607, H04L1/1829, H04W72/0446
Abstract: a computer-readable storage medium stores instructions to configure a ue for sidelink operation in a 5g nr network, and to cause the ue to perform operations including decoding a first sidelink transmission received from a second ue. the first sidelink transmission includes a first resource reservation for a subsequent sidelink transmission by the second ue. a second sidelink transmission received from a third ue is decoded. the second sidelink transmission includes a second resource reservation for a subsequent sidelink transmission by the third ue. a co-channel collision is detected based on the first resource reservation and the second resource reservation being in a same sidelink slot. a feedback message is encoded for transmission to the second ue and the third ue. the feedback message indicates the co-channel collision.
Inventor(s): Ziyin Lin of Chandler AZ (US) for intel corporation, Karumbu Nathan Meyyappan of Portland OR (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): H05K1/11, H05K1/18, H05K3/46
Abstract: technologies for integrated circuit components with liquid metal interconnects are disclosed. in the illustrative embodiment, a bed of nails socket can mate with an integrated circuit component with liquid metal interconnects. the nails pierce a foam cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. a fabric layer adjacent to the foam cap layer helps secure the foam cap layer, preventing small pieces of the foam cap layer that may be dislodged during repeated insertion into a bed of nails socket from becoming separated from the foam cap layer. the fabric layer can provide additional benefits, such as removing more of the liquid metal from the nails when the integrated circuit component is removed from the bed of nails socket.
Intel Corporation patent applications on February 29th, 2024
- Intel Corporation
- B05D3/06
- B05D1/12
- H05K3/02
- Intel corporation
- B25J9/16
- B25J13/08
- F16J15/328
- G01R19/10
- G01R31/311
- G01Q10/04
- G01Q20/02
- G01Q60/38
- G02B6/36
- G03F1/74
- G03F1/84
- G03F7/20
- G03F9/00
- G06F1/3234
- G06F1/16
- G06T1/00
- H04N5/232
- H04N7/18
- G06F3/06
- G06F9/22
- G06F9/445
- G06F9/30
- G06F9/345
- G06F9/38
- G06F9/455
- G06F12/0891
- G06F12/14
- G06F21/53
- G06F21/79
- H04L9/40
- H04L69/04
- G06F17/16
- G06F7/544
- G06N3/00
- G06F21/62
- G06F3/14
- G06F21/35
- G06F21/84
- G09G3/00
- G06F30/392
- H01L23/498
- G06N5/04
- G06T1/20
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/084
- G06T5/00
- G02B27/01
- G06T5/50
- G06T9/00
- G06F12/02
- G06T15/00
- G06V10/44
- G06T3/00
- G06T3/40
- G06T7/20
- H04N19/172
- H01L21/48
- H01L21/8238
- H01L27/092
- H01L29/06
- H01L29/08
- H01L29/417
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/778
- H01L29/786
- H01L23/15
- H01L23/367
- H01L23/373
- H01L23/48
- H01L27/088
- H01L29/78
- H01L23/544
- H01L23/00
- H01L23/13
- H01L23/538
- H01L25/065
- H01L23/528
- H01L23/522
- H01L23/532
- H01L23/29
- H01L23/31
- H01L23/64
- H01L21/56
- H01L23/16
- H01L25/00
- H01L27/085
- H01Q1/24
- H01Q1/22
- H01Q9/04
- H01Q21/28
- H01Q21/00
- H02M3/158
- H02M1/00
- H04B17/27
- G01S5/00
- H04L27/26
- H04L9/08
- H04L47/12
- H04L47/283
- H04W48/16
- H04W4/029
- H04W24/08
- H04W48/10
- H04W68/00
- H04W92/04
- H04W72/25
- H04L1/1607
- H04L1/1829
- H04W72/0446
- H05K1/11
- H05K1/18
- H05K3/46
- H01L23/49822
