Intel Corporation patent applications on February 20th, 2025
Patent Applications by Intel Corporation on February 20th, 2025
Intel Corporation: 38 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (3), G06N3/045 (3), G06N3/063 (3), G06N3/08 (3), G06F7/544 (3) H01L23/49827 (2), G06T1/20 (2), G06N3/0495 (2), G02B3/0056 (1), H02J1/14 (1)
With keywords such as: data, device, based, example, user, embodiments, surface, power, finger, and source in patent application abstracts.
Patent Applications by Intel Corporation
20250060516. SUB-SURFACE COMPOUND MICROLENSES_simplified_abstract_(intel corporation)
Inventor(s): Nicholas Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B3/00, G02B1/10, G02B6/42
CPC Code(s): G02B3/0056
Abstract: photonic devices, packages, and systems with sub-surface compound microlenses are disclosed. an example microlens structure includes a glass core and a microlens stack embedded in the glass core, the stack comprising a plurality of regions stacked a direction of propagation of light that is to be manipulated by the microlens structure, wherein each region is a region of a substantially uniform refractive index that is different from the refractive index of the glass core. such a stack may be referred to as a “sub-surface compound microlens,” where the term “sub-surface” is indicative of the fact that the stack may be below all surfaces of the glass core (i.e., is embedded in the glass core) and the term “compound” is indicative of the fact that the stack is a compound arrangement of multiple regions (e.g., each region is an individual microlens).
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Xiaoqian Li of Chandler AZ (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/122, G02B6/12
CPC Code(s): G02B6/1225
Abstract: photonic packages and device assemblies that include photonic integrated circuits (pics) coupled to optical lenses on lateral sides of the pics. an example photonic package comprises a package support, an integrated circuit (ic), an insulating material, a pic having an active side and a lateral side substantially perpendicular to the active side. at least one optical structure is on the active side. a substantial portion of the active side is in contact with the insulating material, and the pic is electrically coupled to the package support and to the ic. the photonic package further includes an optical lens coupled to the pic on the lateral side. in some embodiments, the photonic package further includes an interposer between the pic or the ic and the package support.
Inventor(s): Sapumal Wijeratne of Portland OR (US) for intel corporation, Stephen H. Gunther of Beaverton OR (US) for intel corporation, Rene Barrientos Barrientos of Hillsboro OR (US) for intel corporation, Joseph Alberts of Aloha OR (US) for intel corporation, Preeti Agarwal of Portlan OR (US) for intel corporation, Chee Lim Nge of Beaverton OR (US) for intel corporation, Jorge Rodriguez of Portland OR (US) for intel corporation
IPC Code(s): G06F1/3209
CPC Code(s): G06F1/3209
Abstract: in one example, an apparatus comprises a first intellectual property (ip) circuit to execute operations on data and a power controller. the power controller is to: receive a boost value that is based at least in part on one or more characteristics of a power supply; determine a boosted maximum power level based at least in part on the boost value and a legacy maximum power level; and provide a boosted maximum power budget for the first ip circuit based at least in part on the boosted maximum power level. the first ip circuit, in response to an input voltage violation signal, is to reactively reduce power consumption equal to or below a legacy maximum power budget for the first ip circuit lower than the boosted maximum power budget. other embodiments are described and claimed.
Inventor(s): Manan Goel of Hillsboro OR (US) for intel corporation, Saurin Shah of Portland OR (US) for intel corporation, Lakshman Krishnamurthy of Portland OR (US) for intel corporation, Steven Xing of San Jose CA (US) for intel corporation, Matthew Pinner of Denver CO (US) for intel corporation, Kevin James Doucette of Los Angeles CA (US) for intel corporation
IPC Code(s): G06F3/01, G06F3/03, G06F3/042, G06F3/16, G06V40/20, G10H1/00
CPC Code(s): G06F3/017
Abstract: gesture-controlled virtual reality systems and methods of controlling the same are disclosed herein. an example apparatus includes an on-body sensor to output first signals associated with at least one of movement of a body part of a user or a position of the body part relative to a virtual object and an off-body sensor to output second signals associated with at least one of the movement or the position relative to the virtual object. the apparatus also includes at least one processor to generate gesture data based on at least one of the first or second signals, generate position data based on at least one of the first or second signals, determine an intended action of the user relative to the virtual object based on the position data and the gesture data, and generate an output of the virtual object in response to the intended action.
Inventor(s): Arnab Raha of San Jose CA (US) for intel corporation, Michael Wu of Belmont CA (US) for intel corporation, Deepak Abraham Mathaikutty of Chandler AZ (US) for intel corporation, Daksha Sharma of Hillsboro OR (US) for intel corporation, Martin Langhammer of Alderbury (GB) for intel corporation
IPC Code(s): G06F7/544, G06F5/01
CPC Code(s): G06F7/5443
Abstract: a data processing unit may include a memory, processing elements (pes), and a control unit. the memory may store weight blocks within a weight tensor of a neural network operation. each weight block has an input channel (ic) dimension and an output channel (oc) dimension and includes subblocks. a subblock includes one or more weights having a first data precision and one or more other weights having a second data precision. the second data precision is lower than the first data precision. the control unit may distribute different ones of the subblocks to different ones of the pes. a pe may receive a subblock and perform a first mac operation on a weight having a first data precision and a second mac operation on a weight having a second data precision. the first mac operation may consume more computation cycles or more multipliers than the second mac operation.
Inventor(s): Bogdan Mihai Pasca of Toulouse (FR) for intel corporation, Malladi Venkat Sriram Sastry of Bangalore (IN) for intel corporation
IPC Code(s): G06F7/556, G06F17/17
CPC Code(s): G06F7/556
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to improve performance of a computing device implementing an exponential function. an example apparatus includes interface circuitry to obtain an input, computer readable instructions, and programmable circuitry to instantiate range reduction circuitry to determine, based on the input, a first range reduced argument and an accuracy control value for an approximation of the exponential function of the neural network, and determine, based on the first range reduced argument, a second range reduced argument for the approximation of the exponential function, the second range reduced argument having a smaller data range than the first range reduced argument, and exponential configuration circuitry to compute an exponential value of the input based on the accuracy control value and an exponential value of the second range reduced argument.
Inventor(s): JESUS CORBAL of King City OR (US) for intel corporation, ROBERT VALENTINE of Kiryat Tivon (IL) for intel corporation, ROMAN S. DUBTSOV of Novosibirsk (RU) for intel corporation, NIKITA A. SHUSTROV of Novosibirsk (RU) for intel corporation, MARK J. CHARNEY of Lexington MA (US) for intel corporation, DENNIS R. BRADFORD of Portland OR (US) for intel corporation, MILIND B. GIRKAR of Sunnyvale CA (US) for intel corporation, EDWARD T. GROCHOWSKI of San Jose CA (US) for intel corporation, THOMAS D. FLETCHER of Sherwood OR (US) for intel corporation, WARREN E. FERGUSON of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/30, G06F7/483, G06F7/544, G06F9/38
CPC Code(s): G06F9/3001
Abstract: embodiments of systems, apparatuses, and methods for chained fused multiply add. in some embodiments, an apparatus includes a decoder to decode a single instruction having an opcode, a destination field representing a destination operand, a first source field representing a plurality of packed data source operands of a first type that have packed data elements of a first size, a second source field representing a plurality of packed data source operands that have packed data elements of a second size, and a field for a memory location that stores a scalar value. a register file having a plurality of packed data registers includes registers for the plurality of packed data source operands that have packed data elements of a first size, the source operands that have packed data elements of a second size, and the destination operand. execution circuitry executes the decoded single instruction to perform iterations of packed fused multiply accumulate operations by multiplying packed data elements of the sources of the first type by sub-elements of the scalar value, and adding results of these multiplications to an initial value in a first iteration and a result from a previous iteration in subsequent iterations.
Inventor(s): Stephen H. GUNTHER of Beaverton OR (US) for intel corporation, Praveen Kumar GUPTA of Hillsboro OR (US) for intel corporation, Mahesh Kumar P of Bangalore (IN) for intel corporation, Monica GUPTA of Hillsboro OR (US) for intel corporation, Russell FENGER of Beaverton OR (US) for intel corporation, Benjamin GRANIELLO of Gilbert AZ (US) for intel corporation
IPC Code(s): G06F9/50, G06F11/34
CPC Code(s): G06F9/505
Abstract: techniques for providing hardware provided guidance for efficiently scheduling workloads to an optimal compute module are described. in some examples, hardware includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; a power management unit to monitor telemetry data on the first plurality of processor cores and second plurality of processor cores and to update hardware feedback telemetry data; and thread runtime telemetry circuitry to provide a hint using the hardware feedback telemetry data to consolidate tasks on one of core types.
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F12/0815, G06F12/0804, G06F12/0811, G06F12/1009, G06F12/1045
CPC Code(s): G06F12/0815
Abstract: embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. in one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. for example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.
Inventor(s): Anbang Yao of Beijing 11 (CN) for intel corporation, Ming Lu of Beijing 11 (CN) for intel corporation, Yikai Wang of Beijing (CN) for intel corporation, Scott Janus of Loomis CA (US) for intel corporation, Sungye Kim of Folsom CA (US) for intel corporation
IPC Code(s): G06F18/2136, G06T11/00
CPC Code(s): G06F18/2136
Abstract: embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. an embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.
20250061203. DEVICE RUNTIME UPDATE PRE-AUTHENTICATION_simplified_abstract_(intel corporation)
Inventor(s): Shamanna DATTA of Hillsboro OR (US) for intel corporation, Mahesh NATU of Folsom CA (US) for intel corporation, Jiewen YAO of Shanghai (CN) for intel corporation, Xiaoyu RUAN of Folsom CA (US) for intel corporation, Andrew Martyn DRAPER of Chesham, Buckinghamshire (GB) for intel corporation, Raghunandan MAKARAM of Northborough MA (US) for intel corporation, Alberto MUNOZ of Los Altos CA (US) for intel corporation
IPC Code(s): G06F21/57, G06F21/53, G06F21/54
CPC Code(s): G06F21/572
Abstract: a method comprises establishing, in a trusted security manager of a trusted execution environment, a device update pre-authentication policy for a device communicatively coupled to the trusted execution manager, providing the device update pre-authentication policy to the device, receiving, from the device, a pre-authentication event signal, and providing, to the device, a pre-authentication event response comprising an update indicator to indicate to the device whether a runtime update may be performed.
Inventor(s): Micah Sheller of Hillsboro OR (US) for intel corporation, Cory Cornelius of Portland OR (US) for intel corporation
IPC Code(s): G06F21/62, G06F16/951, G06F18/21, G06F18/2411, G06F21/74, G06N3/04, G06N3/045, G06N3/063, G06N3/08, G06N20/00, G06N99/00, H04L67/10
CPC Code(s): G06F21/6245
Abstract: methods, apparatus, systems and articles of manufacture for distributed use of a machine learning model are disclosed. an example edge device includes a model partitioner to partition a machine learning model received from an aggregator into private layers and public layers. a public model data store is implemented outside of a trusted execution environment of the edge device. the model partitioner is to store the public layers in the public model data store. a private model data store is implemented within the trusted execution environment. the model partitioner is to store the private layers in the private model data store.
Inventor(s): Sameh Gobriel of Dublin CA (US) for intel corporation, Nilesh Jain of Portland OR (US) for intel corporation, Vui Seng Chua of Hillsboro OR (US) for intel corporation, Juan Pablo Munoz of Folsom CA (US) for intel corporation, Gopi Krishna Jha of Mysore, Karnataka (IN) for intel corporation
IPC Code(s): G06N3/0495, G06N3/082
CPC Code(s): G06N3/0495
Abstract: key-value (kv) cache paging schemes can improve memory management for kv caches by storing a kv cache page having key tensors and value tensors for a fixed number of tokens in a fixed-sized block in the kv cache of a worker. to further improve memory management, the schemes can be modified to implement dynamic variable quantization. quantization level of a kv cache page can be set based on a runtime importance score of the kv cache page. in addition, the quantization level of the kv cache page can be set based on the system load. the end result is a scheme that can achieve a high compression ratio of kv cache pages in the kv cache. fitting more kv cache pages in the kv cache can lead to higher inference throughput, higher system-level user capacity, and higher end-to-end service availability.
Inventor(s): Juan Pablo Munoz Chiabrando of Folsom CA (US) for intel corporation, Jinjie Yuan of Beijing (CN) for intel corporation, Nilesh Kumar Jain of Portland OR (US) for intel corporation
IPC Code(s): G06N3/0495
CPC Code(s): G06N3/0495
Abstract: an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to sparsify a base model of a foundation model to generate a sparse base model, apply a neural low-rank adapter search to the sparse base model, and output a fine-tuned base model based on application of the neural low-rank adapter search to the sparse base model.
Inventor(s): NAVEEN MELLEMPUDI of Bangalore (IN) for intel corporation, DIPANKAR DAS of Pune (IN) for intel corporation
IPC Code(s): G06N3/063, G06F5/01, G06F7/487, G06F7/544, G06N3/044, G06N3/045, G06N3/084, G06T1/20
CPC Code(s): G06N3/063
Abstract: one embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. the compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.
Inventor(s): Glen Anderson of Beaverton OR (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation
IPC Code(s): G06N3/08, G06F16/901, G06F16/906, G06F18/21, G06F18/214, G06F18/40, G06N5/04, G06N20/00, G06V10/776, G06V10/778
CPC Code(s): G06N3/08
Abstract: a mechanism is described for facilitating misuse index for explainable artificial intelligence in computing environments, according to one embodiment. a method of embodiments, as described herein, includes mapping training data with inference uses in a machine learning environment, where the training data is used for training a machine learning model. the method may further include detecting, based on one or more policy/parameter thresholds, one or more discrepancies between the training data and the inference uses, classifying the one or more discrepancies as one or more misuses, and creating a misuse index listing the one or more misuses.
Inventor(s): Eriko Nurvitadhi of Hillsoboro OR (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Nicolas C. Galoppo Von Borries of Portland OR (US) for intel corporation, Rajkishore Barik of Santa Clara CA (US) for intel corporation, Tsung-Han Lin of Campbell CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Nadathur Rajagopalan Satish of Santa Clara CA (US) for intel corporation, Jeremy Bottleson of Rancho Cordova CA (US) for intel corporation, Farshad Akhbari of Chandler AZ (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Narayan Srinivasa of Portland OR (US) for intel corporation, Dukhwan Kim of San Jose CA (US) for intel corporation, Sara S. Baghsorkhi of San Jose CA (US) for intel corporation, Justin E. Gottschlich of Santa Clara CA (US) for intel corporation, Feng Chen of Shanghai (CN) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Kevin Nealis of San Jose CA (US) for intel corporation, Xiaoming Chen of Shanghai (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation
IPC Code(s): G06T1/20, G06F9/30, G06F9/38, G06N3/04, G06N3/044, G06N3/045, G06N3/063, G06N3/08, G06N3/084
CPC Code(s): G06T1/20
Abstract: one embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.
Inventor(s): Naveen Matam of Rancho Cordova CA (US) for intel corporation, Lance Cheney of El Dorado Hills CA (US) for intel corporation, Eric Finley of Ione CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Sanjeev Jahagirdar of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Josh Mastronarde of Sacramento CA (US) for intel corporation, Iqbal Rajwani of Roseville CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Melaku Teshome of El Dorado Hills CA (US) for intel corporation, Vikranth Vemulapalli of Folsom CA (US) for intel corporation, Binoj Xavier of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F13/40
CPC Code(s): G06T1/20
Abstract: embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. in one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. a chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. a diverse set of chiplets with different ip core logic can be assembled into a single device.
20250061904. USER IDENTIFICATION WITH AUDIO EARBUDS_simplified_abstract_(intel corporation)
Inventor(s): Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Alejandro Ibarra Von Borstel of Buda TX (US) for intel corporation, Julio Cesar Zamora Esquivel of West Sacramento CA (US) for intel corporation, Paulo Lopez Meyer of Zapopan (MX) for intel corporation, Rodrigo Aldana Lopez of Zapopan (MX) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Edgar Macias Garcia of Zapopan (MX) for intel corporation, Margarita Jauregui Franco of Japopan (MX) for intel corporation
IPC Code(s): G10L19/022, H04R1/26
CPC Code(s): G10L19/022
Abstract: techniques are provided herein for identifying the user of audio earbuds. in particular, a wearer's head filters an audio signal, and the audio filtering capabilities of a user's head are used as a biometric feature. one earbud can be used as an audio emitter and the other earbud as an audio receiver. a broadband sound can be generated by the speaker in one earbud and received at the microphone of the other earbud. the received sound is filtered by the user's head and the head characterization of the received filtered sound can be used to identify the user. in particular, the material properties of the user's head change the signal, such that the received signal at the microphone of the other earbud is different from the transmitted signal. the differences are unique to the user's head due to physiological variances among people, and can be used to identify the user.
Inventor(s): Justin WHETTEN of Gilbert AZ (US) for intel corporation, Zhou YANG of Chandler AZ (US) for intel corporation, Zheng KANG of Chandler AZ (US) for intel corporation, Haowen LIU of Chandler AZ (US) for intel corporation, Bassam ZIADEH of Gilbert AZ (US) for intel corporation, Vijay Krishnan SUBRAMANIAN of Gilbert AZ (US) for intel corporation, John HARPER of Chandler AZ (US) for intel corporation, Pramod MALATKAR of Chandler AZ (US) for intel corporation, Patrick NARDI of Scottsdale AZ (US) for intel corporation, Anthony MONTERROSA of Chandler AZ (US) for intel corporation, Michael TAN of Gilbert AZ (US) for intel corporation, Sean BUSHELL of Peoria AZ (US) for intel corporation
IPC Code(s): H01L23/24, B23K26/362, H01L21/268, H01L21/67
CPC Code(s): H01L23/24
Abstract: the present disclosure is directed to a patterned stiffener that includes a metallic body, which is a component of and is attached to a semiconductor device platform for providing rigidity. in an aspect, there are patterned sections formed on the metallic body that act to modulate the metallic body to obtain a desired configuration for the semiconductor device platform. in another aspect, the present disclosure is also directed to a method that includes providing a platform for forming an electronic component, disposing a stiffener having a metallic body on the platform, disposing at least one semiconductor device onto the platform, performing one or more bonding process steps, and exposing the stiffener to localized heating to modulate changes in the stiffener to a pre-determined shape or desired configuration.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/538, H01L25/065
CPC Code(s): H01L23/49827
Abstract: embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (ic) dies proximate to the second surface.
Inventor(s): Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Tarek Adly Ibrahim of Mesa AZ (US) for intel corporation, Ravindra Vijay Tanikella of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L23/15
CPC Code(s): H01L23/49827
Abstract: methods and apparatus to reduce cracking in glass cores are disclosed. an example apparatus includes a package substrate comprising a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface, and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first portion in continuity with a second surface of the second portion.
Inventor(s): Sagar Suthram of Portland OR (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Pushkar Sharad Ranade of San Jose CA (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation, Ravindranath Vithal Mahajan of Chandler AZ (US) for intel corporation, Abhishek A. Sharma of Portland OR (US) for intel corporation, Joshua Fryman of Corvallis OR (US) for intel corporation, Stephen Morein of San Jose CA (US) for intel corporation, Matthew Adiletta of Bolton MA (US) for intel corporation, Michael Crocker of Portland OR (US) for intel corporation, Aaron Gorius of Upton MA (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00, H01L23/522
CPC Code(s): H01L25/0652
Abstract: embodiments of a microelectronic assembly may include a first integrated circuit (ic) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first ic die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second ic die including a fourth surface, wherein the fourth surface of the second ic die is electrically coupled to the third surface of the first ic die by an interconnect including solder.
20250062576. EDGE MOUNT MEMORY CONNECTOR FOOTPRINT_simplified_abstract_(intel corporation)
Inventor(s): Landon HANKS of Milwaukie OR (US) for intel corporation
IPC Code(s): H01R13/6471, G06F1/18, H01R12/70, H01R13/24
CPC Code(s): H01R13/6471
Abstract: a dual inline memory module (dimm) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. the shape and placement of ground pads and signal pads can improve grounding of noise signals and improve the signal isolation on the signal pins. the ground pads can have additional ground vias to increase the ground path to the ground plane.
Inventor(s): Harel Aronheim of Giv'atayim (IL) for intel corporation, Dmitry Felsenstein of Gan-Yavne (IL) for intel corporation, Ariel Wolf of Haifa (IL) for intel corporation, Eran Amir of Givat Ada (IL) for intel corporation, Ofir Klein of Petah Tikva (IL) for intel corporation, Yazan Alwilly of Majdal shams (IL) for intel corporation, Sergey Sofer of Rishon Lezion (IL) for intel corporation, Sagi Belizowski of Haifa (IL) for intel corporation
IPC Code(s): H02J1/14
CPC Code(s): H02J1/14
Abstract: for example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. for example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. for example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the integrated circuit from the power supply. for example, the controller may be configured to control activation of the controllable load circuitry to apply an event-based load to the power supply, for example, based on the current consumption event.
Inventor(s): Danny Alexander of Monoson (IL) for intel corporation, Danny Ben-Ari of Hasharon Hatichon (IL) for intel corporation, Michael Shachar of Kfar Glikson (IL) for intel corporation
IPC Code(s): H04L1/00
CPC Code(s): H04L1/0015
Abstract: for example, a wireless communication station (sta) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a physical layer (phy) protocol data unit (ppdu) based on a minimal medium access control (mac) protocol data unit (mpdu) size requirement such that, for at least one mpdu of the ppdu, a first count of mac padding bits to pad the mpdu according to the selected setting of the one or more rate-dependent parameters is less than a second count of mac padding bits to pad the mpdu according to a channel-based setting of the one or more rate-dependent parameters, wherein, the channel-based setting of the one or more rate-dependent parameters is based on a condition of a wireless communication channel for transmission of the ppdu; and to transmit the ppdu according to a transmission data rate based on the selected setting.
Inventor(s): Yi Wang of Santa Clara CA (US) for intel corporation, Yingyang Li of Santa Clara CA (US) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation
IPC Code(s): H04L1/1867, H04W72/1273, H04W72/232
CPC Code(s): H04L1/1887
Abstract: systems, apparatuses, methods, and computer-readable media are provided for dynamic hybrid automatic repeat request (harq)-acknowledgement (ack) feedback for multi-cell scheduling (e.g., a downlink control information (dci) that schedules physical downlink shared channels (pdschs) and/or physical uplink shared channels (puschs) on multiple cells). embodiments may include techniques to determine a downlink assignment index (dai) and/or a harq-ack codebook, e.g., a type-1. type-2, and/or type-3 codebook, for multi-cell scheduling. other embodiments may be described and claimed.
Inventor(s): Abhijeet Kolekar of Leander TX (US) for intel corporation
IPC Code(s): H04L9/08, H04L9/00, H04W60/00
CPC Code(s): H04L9/0825
Abstract: various embodiments herein provide techniques related to registering a user equipment (ue) with a wireless network based on a blockchain identity (bi) of the ue. in embodiments, the bi, or a derived key thereof, may be used to sign a cryptographic challenge provided by the network, wherein the challenge is based on the bi. other embodiments may be described and/or claimed.
Inventor(s): Qinghua Li of San Ramon CA (US) for intel corporation, Hao Song of Santa Clara CA (US) for intel corporation, Shlomi Vituri of Tel Aviv (IL) for intel corporation, Assaf Gurevitz of Ramat Hasharon (IL) for intel corporation, Robert Stacey of Portland OR (US) for intel corporation
IPC Code(s): H04L27/34, H04L1/00, H04L27/36
CPC Code(s): H04L27/3483
Abstract: this disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (qam) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (fec) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel, a first portion of the parity bits as sign bits for the shaped amplitude bits; and cause to transmit, using the channel, a second portion of the parity bits.
Inventor(s): Yizhi YAO of Chandler AZ (US) for intel corporation
IPC Code(s): H04L41/16, H04L41/5067
CPC Code(s): H04L41/16
Abstract: this disclosure describes systems, methods, and devices related to optimized resource technologies. a device may create a managed object instance (moi) representing actions executed based on artificial intelligence or machine learning (ai/ml) inference function. the device may notify a management and network service (mns) consumer about the creation of the moi. the device may execute actions by a network or management function acting as the consumer of the inference output. the device may manage performance of the ai/ml inference function.
Inventor(s): Robert VAUGHN of Portland OR (US) for intel corporation
IPC Code(s): H04L51/216, G06F40/30, H04L9/32
CPC Code(s): H04L51/216
Abstract: provided is a computer-readable medium including computer-readable instructions. when the instructions are executed by a computer, the computer may implement a method. according to this method, contextual information of a plurality of users in a conversation is generated based on messages from the plurality of users over a period of time. then the contextual information of the plurality of users is sent to a first artificial intelligence (ai) language model as input for training the ai language model and a request is sent to the first ai language model, wherein the request requires a response associated with the contextual information.
Inventor(s): Ilil BLUM SHEM-TOV of Kiryat Tivon (IL) for intel corporation, Yaron KLEIN of Rosh Haayin (IL) for intel corporation, Dan HOROVITZ of Rishon Lezion (IL) for intel corporation, Yoni KAHANA of Kfar Hess (IL) for intel corporation, Omer BEN-SHALOM of Rishon Lezion (IL) for intel corporation
IPC Code(s): H04W12/06, H04W12/63
CPC Code(s): H04W12/06
Abstract: a method and apparatus for authentication of a user. a user profile is generated during an initial registration. the user profile may include a trusted location of the user. during a subsequent authentication process for the user, it is determined whether the user is located in the trusted location of the user, and an access to a service for the user may be controlled based on a result of the authentication process and the determination whether the user is located in the trusted location of the user. a location-based parameter of the trusted location of the user may be determined and stored in advance, and it is determined whether the user is located in the trusted location of the user by comparing the location-based parameter of the current location of the user and the location-based parameter of the trusted location of the user.
Inventor(s): Oded Liron of Haifa (IL) for intel corporation, Eran Segev of Tel Aviv (IL) for intel corporation, Danny Alexander of Monoson (IL) for intel corporation, Omer Ytzhaki of Haifa (IL) for intel corporation, Hila Ben Artzi of Herzliya (IL) for intel corporation
IPC Code(s): H04W28/20
CPC Code(s): H04W28/20
Abstract: for example, a wireless communication station (sta) may be configured to determine a usage-based channel bandwidth (bw) setting, for example, based on a link-usage parameter corresponding to a usage of a wireless communication link for communication of traffic between the sta and an access point (ap). for example, the sta may be configured to transmit a channel bw reduction request to the ap, for example, based on a determination that the usage-based channel bw setting is less than an operating channel bw setting for the sta. for example, the channel bw reduction request may be configured to request the ap to reduce the operating channel bw setting for the sta based on the usage-based channel bw setting.
Inventor(s): Avik Sengupta of Santa Clara CA (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation
IPC Code(s): H04W72/30, H04W72/0453, H04W72/23
CPC Code(s): H04W72/30
Abstract: various embodiments herein provide techniques related to downlink multicast and broadcast service (mbs) data and control. in embodiments, abase station may identify, based on an active bandwidth part (bwp) of a user equipment (ue), a transmission control indicator (tci) state list configuration related to a unicast transmission to the ue; and transmit the multicast or broadcast transmission based on the tci state list. other embodiments may be described and/or claimed.
Inventor(s): Oded Liron of Haifa (IL) for intel corporation, Danny Alexander of Monoson (IL) for intel corporation, Danny Ben-Ari of Hasharon Hatichon (IL) for intel corporation, Nadav Szanto of Haifa (IL) for intel corporation, Ehud Reshef of Kiryat Tivon (IL) for intel corporation
IPC Code(s): H04W74/0816, H04B17/336, H04W74/08, H04W76/20
CPC Code(s): H04W74/0816
Abstract: for example, a non access point (ap) (non-ap) multi-link device (mld) may be configured to assign a first priority to a first link of a multi-link operation mode and a second priority to a second link of the multi-link operation mode. for example, the first priority assigned to the first link of the multi-link operation mode may be higher than the second priority assigned to the second link of the multi-link operation mode. for example, the non-ap mld may be configured to limit a transmission from the non-ap mld over the second link based, for example, on a busy state of a wireless communication medium of the first link.
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W76/11, H04W72/1268
CPC Code(s): H04W76/11
Abstract: this disclosure describes systems, methods, and devices related to pre-association exchange. a device may receive a physical layer (phy) based extended long range (elr) request from a station device (sta) within a transmission opportunity (txop). the device may allocate a unique unassociated id (uid) to the sta within the same txop, the uid being distinct among active unassociated devices. the device may indicate to the sta to use the uid in subsequent communications until association or a predefined timeout occurs. the device may cause to send a trigger frame to the sta using the uid for scheduled uplink transmissions.
Inventor(s): Landon HANKS of Milwaukie OR (US) for intel corporation
IPC Code(s): H05K1/11, G06F1/18, G11C5/04, H01R12/72, H01R12/73, H01R13/24, H01R13/6471
CPC Code(s): H05K1/113
Abstract: a dual inline memory module (dimm) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. the signals pins are staggered with alternating signal pins being longer and shorter. longer pins have corresponding signal pads on the system board farther away from the connector than corresponding signals pads for the shorter pins.
20250063798. DRIVER STAGE CURRENT DENSITY ENHANCEMENT_simplified_abstract_(intel corporation)
Inventor(s): Yuri Rozenfeld of Haifa (IL) for intel corporation, Yishai Eilat of Haifa (IL) for intel corporation, Elham Mohammadi of Portland OR (US) for intel corporation, Naor Roi Shay of Rehovot (IL) for intel corporation, Anna Nazimov of Haifa (IL) for intel corporation
IPC Code(s): H01L29/417, H01L27/02, H01L27/088, H01L29/78
CPC Code(s): H01L29/41758
Abstract: a transistor device can include a drain contact operably connected to a drain finger and a source contact operably connected to a source finger. the transistor device can further include diffusion area connected to the drain finger and the source finger to provide current to the drain finger and the source finger. the drain finger can have a length extending along an axis and different drain finger widths along the drain finger length such that current density is equal at each point along the drain finger length. the source finger can have a length extending along the axis and source finger widths along the source finger length such that current density is equal at each point along the source finger length.
Intel Corporation patent applications on February 20th, 2025
- Intel Corporation
- G02B3/00
- G02B1/10
- G02B6/42
- CPC G02B3/0056
- Intel corporation
- G02B6/122
- G02B6/12
- CPC G02B6/1225
- G06F1/3209
- CPC G06F1/3209
- G06F3/01
- G06F3/03
- G06F3/042
- G06F3/16
- G06V40/20
- G10H1/00
- CPC G06F3/017
- G06F7/544
- G06F5/01
- CPC G06F7/5443
- G06F7/556
- G06F17/17
- CPC G06F7/556
- G06F9/30
- G06F7/483
- G06F9/38
- CPC G06F9/3001
- G06F9/50
- G06F11/34
- CPC G06F9/505
- G06F12/0815
- G06F12/0804
- G06F12/0811
- G06F12/1009
- G06F12/1045
- CPC G06F12/0815
- G06F18/2136
- G06T11/00
- CPC G06F18/2136
- G06F21/57
- G06F21/53
- G06F21/54
- CPC G06F21/572
- G06F21/62
- G06F16/951
- G06F18/21
- G06F18/2411
- G06F21/74
- G06N3/04
- G06N3/045
- G06N3/063
- G06N3/08
- G06N20/00
- G06N99/00
- H04L67/10
- CPC G06F21/6245
- G06N3/0495
- G06N3/082
- CPC G06N3/0495
- G06F7/487
- G06N3/044
- G06N3/084
- G06T1/20
- CPC G06N3/063
- G06F16/901
- G06F16/906
- G06F18/214
- G06F18/40
- G06N5/04
- G06V10/776
- G06V10/778
- CPC G06N3/08
- CPC G06T1/20
- G06F13/40
- G10L19/022
- H04R1/26
- CPC G10L19/022
- H01L23/24
- B23K26/362
- H01L21/268
- H01L21/67
- CPC H01L23/24
- H01L23/498
- H01L23/00
- H01L23/538
- H01L25/065
- CPC H01L23/49827
- H01L23/15
- H01L23/522
- CPC H01L25/0652
- H01R13/6471
- G06F1/18
- H01R12/70
- H01R13/24
- CPC H01R13/6471
- H02J1/14
- CPC H02J1/14
- H04L1/00
- CPC H04L1/0015
- H04L1/1867
- H04W72/1273
- H04W72/232
- CPC H04L1/1887
- H04L9/08
- H04L9/00
- H04W60/00
- CPC H04L9/0825
- H04L27/34
- H04L27/36
- CPC H04L27/3483
- H04L41/16
- H04L41/5067
- CPC H04L41/16
- H04L51/216
- G06F40/30
- H04L9/32
- CPC H04L51/216
- H04W12/06
- H04W12/63
- CPC H04W12/06
- H04W28/20
- CPC H04W28/20
- H04W72/30
- H04W72/0453
- H04W72/23
- CPC H04W72/30
- H04W74/0816
- H04B17/336
- H04W74/08
- H04W76/20
- CPC H04W74/0816
- H04W76/11
- H04W72/1268
- CPC H04W76/11
- H05K1/11
- G11C5/04
- H01R12/72
- H01R12/73
- CPC H05K1/113
- H01L29/417
- H01L27/02
- H01L27/088
- H01L29/78
- CPC H01L29/41758
