Intel Corporation patent applications on December 5th, 2024
Patent Applications by Intel Corporation on December 5th, 2024
Intel Corporation: 34 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (4), G02B6/42 (3), G06F7/544 (2), G06F9/30 (2), H01L23/528 (2) G01R31/31917 (1), H01L25/16 (1), H05K7/20145 (1), H05K1/11 (1), H04W24/10 (1)
With keywords such as: circuit, device, surface, source, signal, capacitor, substrate, memory, embodiments, and computing in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Aryeh FARBER of Petah Tikva (IL) for intel corporation, Evgeny SHUMAKER of Nesher (IL) for intel corporation, Samer ARRAM of Santa Clara CA (US) for intel corporation, Dana Shalala YETIV of Haifa (IL) for intel corporation, Nir GERON of Ramat Efal (IL) for intel corporation, Gil HOROVITZ of Emek-Hefer (IL) for intel corporation
IPC Code(s): G01R31/319, G01R31/3193
CPC Code(s): G01R31/31917
Abstract: a mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.
Inventor(s): A Ezekiel Poulose of Kerala (IN) for intel corporation, Avinash Manu Aravindan of Kerala (IN) for intel corporation, Naoki Matsumura of San Jose CA (US) for intel corporation, Jagadish Vasudeva Singh of Bangalore (IN) for intel corporation
IPC Code(s): G01R31/392, G01R31/389, H01M10/48, H02J7/00
CPC Code(s): G01R31/392
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to manage battery outgassing conditions. an example apparatus includes an enclosure having a first conductive surface located proximate to an outer boundary of the enclosure, a second conductive surface located a first distance from the first conductive surface, a capacitance circuit coupled to the first conductive surface and the second conductive surface, and a charge control circuit to control an input signal to the second conductive surface and a third conductive surface based on an output of the capacitance circuit.
Inventor(s): Chia-Pin Chiu of Tempe AZ (US) for intel corporation, Xiaoqian Li of Chandler AZ (US) for intel corporation, Kaveh Hosseini of Livermore CA (US) for intel corporation, Tim T. Hoang of San Jose CA (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4228
Abstract: the substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. an edge of a photonic integrated circuit (pic) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. an optical fiber in an fau is aligned with a waveguide within the pic and the fau is attached to the pic edge and an attachment block. the attachment block provides an increased attachment surface area for the fau. a portion of the fau extends into the substrate cutout. a stress relief mechanism can secure the fiber optic cable attached to the fau to the substrate to at least partially isolate the fau-pic attachment from external mechanical forces applied to the optical fiber cable. the integrated circuit component can be attached to a socket that comprises a socket cutout into which an fau can extend.
Inventor(s): John M. Heck of Berkeley CA (US) for intel corporation, Saeed Fathololoumi of Los Gatos CA (US) for intel corporation, Harel Frish of Albuquerque NM (US) for intel corporation, Sang Yup Kim of Sunnyvale CA (US) for intel corporation, Hari Mahalingam of San Jose CA (US) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/42, H01L25/16
CPC Code(s): G02B6/423
Abstract: a kinematically aligned optical connector may be implemented with a silicon pic component and a glass substrate component. the kinematically aligned optical connector includes one or more kinematic connectors or mechanical alignment features and visual fiducials that enable true kinematic coupling (i.e., in a three-dimensional cartesian coordinate system, full constraint in all 6 degrees of freedom, meaning, x, y, z planes and all 3 angles), and enables an increased thickness of the glass substrate material of the glass waveguide substrate.
20240402445. HYDROPHOBIC FEATURE TO CONTROL ADHESIVE FLOW_simplified_abstract_(intel corporation)
Inventor(s): Bassam ZIADEH of Gilbert AZ (US) for intel corporation, Jingyi HUANG of San Diego CA (US) for intel corporation, Yiqun BAI of Chandler AZ (US) for intel corporation, Ziyin LIN of Chandler AZ (US) for intel corporation, Vipul MEHTA of Chandler AZ (US) for intel corporation, Joseph VAN NAUSDLE of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4239
Abstract: embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. these hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. in embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. other embodiments may be described and/or claimed.
Inventor(s): Glen J. Anderson of Portland OR (US) for intel corporation
IPC Code(s): G06F3/01, G06F3/03, G06F3/0481, G06F3/0484, G06F3/14
CPC Code(s): G06F3/017
Abstract: gesture input with multiple displays, views, and physics is described. in one example, a method includes generating a three dimensional space having a plurality of objects in different positions relative to a user and a virtual object to be manipulated by the user, presenting, on a display, a displayed area having at least a portion of the plurality of different objects, detecting an air gesture of the user against the virtual object, the virtual object being outside the displayed area, generating a trajectory of the virtual object in the three-dimensional space based on the air gesture, the trajectory including interactions with objects of the plurality of objects in the three-dimensional space, and presenting a portion of the generated trajectory on the displayed area.
Inventor(s): Shuai Mu of San Diego CA (US) for intel corporation, Cristina S. Anderson of Hillsboro OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F7/544, G06T1/20
CPC Code(s): G06F9/3001
Abstract: embodiments are directed to systems and methods for reuse of fma execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a gpu. these new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the fma execution unit, which allows the main dataflow of the fma execution unit to be bypassed for such special cases. since special cases are handled by the fma execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for hpc applications.
Inventor(s): Ren WANG of Portland OR (US) for intel corporation, Yifan YUAN of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F9/48
CPC Code(s): G06F9/4818
Abstract: methods, apparatus, and computer programs are disclosed to schedule access to multiple accelerators. in one embodiment, a method is disclosed to perform: receiving a first request to process data for a first application by a first accelerator of a plurality of accelerators of a computing system, an accelerator of the plurality of accelerators being dedicated to one or more respective specialized computations of the computing system for data processing; scheduling resources for the first request based on the first request and a second request to process data for a second application by a second accelerator of the plurality of accelerators, the first and second requests having one or more priority indications indicating priority between the first and second requests; and processing the data for the first application using the resources as scheduled responsive to the first request.
Inventor(s): Zhonghua SUN of Shanghai (CN) for intel corporation, Pei GAO of Shanghai (CN) for intel corporation, Yue LIU of Shanghai (CN) for intel corporation, Liangqi ZHU of Shanghai (CN) for intel corporation, Yue YAO of Shanghai (CN) for intel corporation, Junyu TONG of Shanghai (CN) for intel corporation, Hua MA of Shanghai (CN) for intel corporation, Cong ZHANG of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: provided is a method comprising obtaining information about a detected memory error in a memory device, the memory device being connected to a first host via a compute express link, cxl, interface. the method comprises further recording the memory error information into a firmware of the memory device.
20240403259. COMPRESSION TECHNIQUES_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Mike MacPherson of Portland OR (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Nicolas Galoppo Von Borries of Portland OR (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Jayakrishna P S of Bangalore (IN) for intel corporation, Pattabhiraman K of Bangalore (IN) for intel corporation, Sudhakar Kamma of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46
CPC Code(s): G06F15/7839
Abstract: methods and apparatus relating to techniques for data compression. in an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. other embodiments are also disclosed and claimed.
Inventor(s): Nirmit Parikh of San Jose CA (US) for intel corporation, Tanmay Hiren Desai of Navsari (IN) for intel corporation
IPC Code(s): G06F16/9535, G06F16/34, G06F16/9536
CPC Code(s): G06F16/9535
Abstract: embodiments are provided for summarization and recommendation of content. in disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. the summaries may be formed with constituent parts extracted from the contents. a recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. other embodiments may be described and/or claimed.
Inventor(s): Umer Iftikhar Cheema of Hillsboro OR (US) for intel corporation, Kevin Brady of Newry (GB) for intel corporation, Robert Simofi of Dumbravita, Timis (RO) for intel corporation, Colm O Faolain of Dublin (IE) for intel corporation, Deepak Abraham Mathaikutty of Chandler AZ (US) for intel corporation, Arnab Raha of San Jose CA (US) for intel corporation, Dinakar Kondru of Frisco TX (US) for intel corporation, Gary Baugh of Bray (IE) for intel corporation, Darren Crews of Portland OR (US) for intel corporation, Fergal Connor of Dundalk (IE) for intel corporation
IPC Code(s): G06N3/048
CPC Code(s): G06N3/048
Abstract: an activation function in a neural network may be approximated by one or more linear functions. a linear function may correspond to a segment of the input range of the activation function, e.g., a linear segment. a programmable look-up table may store slopes and intercepts of linear functions. a post processing engine (ppe) array executing the activation function may determine that an input data element of the activation function falls into the linear segment and compute an output of the linear function using the input data element. the output of the linear function may be used as the approximated output of the activation function. alternatively, the ppe array may determine that the input data element is in a saturation segment and use a fixed value associated with the saturation segment as the approximated output of the activation function.
20240403620. MACHINE LEARNING ACCELERATOR MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Anavai Ramesh of Chandler AZ (US) for intel corporation, Asit Mishra of Hillsboro OR (US) for intel corporation, Deborah Marr of Portland OR (US) for intel corporation, Jeffrey Cook of Portland OR (US) for intel corporation, Srinivas Sridharan of Bangalore (IN) for intel corporation, Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Dheevatsa Mudigere of Bangalore (IN) for intel corporation, Mohammad Ashraf Bhuiyan of Beaverton OR (US) for intel corporation, Md Faijul Amin of Chandler AZ (US) for intel corporation, Wei Wang of San Jose CA (US) for intel corporation, Dhawal Srivastava of Scottsdale AZ (US) for intel corporation, Niharika Maheshwari of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/063, G06F7/78, G06F9/00, G06N3/084, G06N20/00, G06T1/20
CPC Code(s): G06N3/063
Abstract: an apparatus to facilitate acceleration of machine learning operations is disclosed. the apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.
20240404487. GRAPHICS WITH ADAPTIVE TEMPORAL ADJUSTMENTS_simplified_abstract_(intel corporation)
Inventor(s): Louis Feng of San Jose CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Tomasz Janczak of Gdansk (PL) for intel corporation, Andrew T. Lauritzen of Victoria (CA) for intel corporation, David M. Cimini of Orangevale CA (US) for intel corporation, Nikos Kaburlasos of Lincoln CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, Jacek Kwiatkowski of Santa Clara CA (US) for intel corporation, Philip R. Laws of Santa Clara CA (US) for intel corporation, Devan Burke of Portland OR (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G09G5/00, G06T1/20, G09G5/36, G09G5/38, G09G5/391
CPC Code(s): G09G5/005
Abstract: an embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. other embodiments are disclosed and claimed.
20240404617. RUNTIME ALERT SIGNAL ACTIVATION TEST MODE_simplified_abstract_(intel corporation)
Inventor(s): Kuljit S. BAINS of Olympia WA (US) for intel corporation, Shigeki TOMISHIMA of Portland OR (US) for intel corporation
IPC Code(s): G11C29/46, G11C29/10, G11C29/12
CPC Code(s): G11C29/46
Abstract: a system enables an alert signal test mode. the system has an alert signal line between the memory device and the memory controller. the memory device has a register that controls entry into the alert signal test mode. the memory controller sends a command to trigger the memory device to enter the alert signal test mode. in response to the commands, the memory device asserts the alert signal line with an alert signal in response to entry into the alert signal test mode.
Inventor(s): Eric ERIKE of Mesa AZ (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation, Karumbu MEYYAPPAN of Portland OR (US) for intel corporation, Anikki GIESSLER of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/13, H01L21/48, H01L23/498
CPC Code(s): H01L23/13
Abstract: embodiments described herein include a liquid metal carrier. in an embodiment, the liquid metal carrier includes a substrate that is a polymer. in an embodiment, a first opening is provided through the substrate with a first shape, and a second opening is provided through the substrate with a second shape. in an embodiment, the first shape is different than the second shape.
Inventor(s): Sikandar Abbas of Forest Grove OR (US) for intel corporation, Chanaka Munasinghe of Portland OR (US) for intel corporation, Leonard Guler of Hillsboro OR (US) for intel corporation, Reza Bayati of Portland OR (US) for intel corporation, Madeleine Stolt of Beaverton OR (US) for intel corporation, Makram Abd El Qader of Hillsboro OR (US) for intel corporation, Pratik Patel of Portland OR (US) for intel corporation, Anindya Dasgupta of Portland OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/768, H01L23/528
CPC Code(s): H01L23/481
Abstract: devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. a device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
Inventor(s): Denzil Frost of Rio Rancho, NM ID (US) for intel corporation
IPC Code(s): H01L23/522
CPC Code(s): H01L23/5223
Abstract: disclosed herein are ic devices with fishbone capacitor structures. an example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure.
Inventor(s): Chong ZHANG of San Jose CA (US) for intel corporation, Cheng XU of Chandler AZ (US) for intel corporation, Junnan ZHAO of San Jose CA (US) for intel corporation, Ying WANG of Chandler AZ (US) for intel corporation, Meizi JIAO of San Jose CA (US) for intel corporation
IPC Code(s): H01L25/16, H01L21/56, H01L23/498, H01L23/528, H01L23/538
CPC Code(s): H01L25/16
Abstract: microelectronic assemblies, related devices, and methods are disclosed herein. in some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. in some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.
Inventor(s): Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Patrick MORROW of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/088, H01L29/06, H01L29/423
CPC Code(s): H01L29/41775
Abstract: integrated circuit structures having backside contact stitching are described. in an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. first and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. a conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. the conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.
Inventor(s): Szuya S. LIAO of Hillsboro OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/8234, H01L29/08, H01L29/165, H01L29/78
CPC Code(s): H01L29/66795
Abstract: confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. for example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. an isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. an upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. the epitaxial source and drain regions do not extend laterally over the isolation structure. the semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
20240405433. ANTENNA MODULES AND COMMUNICATION DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Georg Seidemann of Landshut (DE) for intel corporation, Harald Gossner of Riemerling (DE) for intel corporation, Thomas Wagner of Regelsbach (DE) for intel corporation, Bernd Waidhas of Pettendorf (DE) for intel corporation, Tae Young Yang of Hillsboro OR (US) for intel corporation
IPC Code(s): H01Q9/04, H01Q1/22
CPC Code(s): H01Q9/0414
Abstract: disclosed herein are antenna modules, electronic assemblies, and communication devices. an example antenna module includes an ic component, an antenna patch support over a face of the ic component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the ic component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. the first antenna patch is on the face of the ic component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the ic component.
20240405459. Modular Printed Circuit Boards with Connectors_simplified_abstract_(intel corporation)
Inventor(s): Navneet K. SINGH of Bangalore (IN) for intel corporation, Aiswarya PIOUS of Bangalore (IN) for intel corporation, Samarth ALVA of Bangalore (IN) for intel corporation, Sharvil DESAI of Ahmedabad (IN) for intel corporation, Ralph JENSEN of Hillsboro OR (US) for intel corporation, Carlos MARISCAL of Gresham OR (US) for intel corporation, Michael CROCKER of Portland OR (US) for intel corporation, Kevin MA of Beaverton OR (US) for intel corporation, Pedro Jose MARTINEZ NARVAEZ of Hillsboro OR (US) for intel corporation
IPC Code(s): H01R12/52, H05K3/36
CPC Code(s): H01R12/52
Abstract: according to the various aspects, the present disclosure is directed to printed circuit board assemblies having a plurality of printed circuit board units or modules that use board connectors for joining the printed circuit board units. in an aspect, the board connector has a first surface, which may be a top surface, and an opposing second surface, which may be a bottom surface, and a plurality of openings, including a first set of connector openings for providing electrical connections between the at least two plurality of printed circuit board units. in another aspect, a method that includes forming a first printed circuit board unit with a first connecting portion and a second printed circuit board unit with a second connecting portion, and the first and second connecting are electrically coupled with the printed circuit board connector.
Inventor(s): Chi-Hsiang HUANG of Seattle WA (US) for intel corporation, Su Hwan KIM of Portland OR (US) for intel corporation, Harish KRISHNAMURTHY of Beaverton OR (US) for intel corporation
IPC Code(s): H02M3/07
CPC Code(s): H02M3/07
Abstract: voltage converters using switch capacitor voltage converters are described. in some implementations, a hybrid converter having a switch capacitor voltage converter coupled with a downstream second voltage converter such as a buck regulator or ldo is described. it may incorporate circuitry for reducing output offset from the switch cap converter, which in turn, may reduce voltages exposed to switch transistors used in the downstream voltage regulator.
Inventor(s): Sophia MAERKOVICH of Haifa (IL) for intel corporation, Sarit ZUR of Petah-Tikva M (IL) for intel corporation, Oren Ezra AVRAHAM of Givat Shmuel (IL) for intel corporation
IPC Code(s): H03M1/46, H03K19/17728, H03M1/40
CPC Code(s): H03M1/462
Abstract: a circuit comprising: an analog-to-digital converter configured to generate a digital signal based on a received input voltage and a received reference voltage; a capacitor array; and a switching network configured to switch each capacitor of the capacitor array between a first conductor connected to a supply voltage source, and a second conductor connected to the reference voltage; wherein the analog-to-digital converter comprises a logic configured to control the switching network to selectively switch between the first conductor and the second conductor based on the generated digital signal.
Inventor(s): Yi Wang of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Dae Won Lee of Portland OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation
IPC Code(s): H04L1/1829, H04L1/1812, H04L5/00, H04W72/1273
CPC Code(s): H04L1/1854
Abstract: a user equipment (ue) may generate first harq-ack information bits based on a first pdsch and second harq-ack information bits based on a second pdsch. the ue may determine a first slot for an expected pucch transmission with the first harq-ack information bits. when the ue is configured for deferring harq-ack for the first pdsch and when the first slot is unavailable for the expected pucch transmission, the ue may determine an earliest second slot that is available. the ue may also determine a third slot for an expected pucch transmission with the second harq-ack information bits assigned for the second pdsch. the resource assigned for transmission of the first harq-ack information bits is used to verify the order for the first and second harq-ack transmissions regardless of whether the first slot is unavailable and the second earliest slot is used for transmission of the first harq-ack information bits.
20240406240. TECHNOLOGIES FOR STREAMING DEVICE ROLE REVERSAL_simplified_abstract_(intel corporation)
Inventor(s): Karthik Veeramani of Hillsboro OR (US) for intel corporation, Rajneesh Chowdhury of Portland OR (US) for intel corporation, Ujwal Paidipathi of Beaverton OR (US) for intel corporation, Brian E. Rogers of Aloha OR (US) for intel corporation, Aslam Padath Peedikayil Abdul Rahim of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L65/75, H04L65/61, H04W4/80
CPC Code(s): H04L65/75
Abstract: technologies for streaming device role reversal include a source computing device and a destination computing device coupled via a communication channel. the source computing device and destination computing device are each configured to support role reversal. in other words, the source computing device and the destination computing device are each capable of switching between receiving and transmitting digital media content over the established communication channel. the source computing device is configured to initiate the role reversal, pause transmit functionality of the source computing device, and enable receive functionality of the source computing device. the destination computing device is configured to receive a role reversal indication from the source computing device, locally process the content, transmit a content stream to the source computing device, and display the content stream on an output device of the source computing device. other embodiments are described and claimed herein.
Inventor(s): Qian Xu of Folsom CA (US) for intel corporation, Jian Hu of El Dorado Hills CA (US) for intel corporation, Navyasree Matturu of Rancho Cordova CA (US) for intel corporation, Dmitry E. Ryzhov of Mountain View CA (US) for intel corporation, Satya N. Yedidi of Roseville CA (US) for intel corporation
IPC Code(s): H04N19/105, H04N19/176
CPC Code(s): H04N19/105
Abstract: a block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. it is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. to address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. a reference frame priority list is applied to select a subset of potential reference frame combinations. an efficient top-k sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. motion compensation and rate-distortion optimization are performed on the top merge candidates only.
Inventor(s): Vasilii Aristarkhov of Magdeburg (DE) for intel corporation
IPC Code(s): H04N19/513, G06V10/74, G06V10/82
CPC Code(s): H04N19/513
Abstract: example apparatus disclosed includes at least one memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to process a first frame of a video sequence with a neural network, store intermediate outputs of at least one of a convolution layer or a pooling layer of the neural network, the intermediate outputs associated with the first frame, process a second frame of the video sequence based on the intermediate outputs associated with the first frame to skip processing of a temporally static area of the second frame by the at least one of the convolution layer or a pooling layer, the temporally static image area common to the first frame and the second frame.
Inventor(s): Jaison Fernandez of Bangalore (IN) for intel corporation, Adam Kupryjanow of Gdansk (PL) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation, Tarakesava Reddy Koki of Hyderbad (IN) for intel corporation, Aiswarya M. Pious of Bengaluru (IN) for intel corporation
IPC Code(s): H04R3/00, G10L21/028, G10L25/30, G10L25/60, H04R5/027, H04R29/00, H04S3/00
CPC Code(s): H04R3/005
Abstract: a computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. the audio signals are associated with audio emitted from a same source. the method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Sergey Sosnin of Santa Clara CA (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Sergey Panteleev of Kildare (IE) for intel corporation, Jie Zhu of Santa Clara CA (US) for intel corporation, Gregory Ermolaev of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W24/10, H04W74/0833
CPC Code(s): H04W24/10
Abstract: various embodiments herein relate to techniques that may improve coverage for a physical random access channel (prach). additionally, some embodiments may relate to techniques for repetition of a channel state information (csi) report on a physical uplink shared channel (pusch) for coverage enhancement. other embodiments may be described and/or claimed.
20240407092. COVERS FOR INTEGRATED CIRCUIT PACKAGE SOCKETS_simplified_abstract_(intel corporation)
Inventor(s): Ariatne Ramirez Macias of Zapopan (MX) for intel corporation, Allison Van Horn of Beaverton OR (US) for intel corporation, Kristin L. Weldon of Hillsboro OR (US) for intel corporation, Israel Cruz Ruiz of Zapopan (MX) for intel corporation, Fernando Gonzalez Lenero of Zapopan (MX) for intel corporation, Min Pei of Camas WA (US) for intel corporation, Francisco Javier Colorado Alonso of San Pedro Tlaquepaque (MX) for intel corporation, Randall Scott Sanford of Scappoose OR (US) for intel corporation, Emery Evon Frey of Portland OR (US) for intel corporation, Eric W. Buddrius of Hillsboro OR (US) for intel corporation
IPC Code(s): H05K1/11
CPC Code(s): H05K1/11
Abstract: covers for integrated circuit package sockets are disclosed herein. an example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.
Inventor(s): Douglas HEYMANN of Portland OR (US) for intel corporation, Debra BEYER of Hillsboro OR (US) for intel corporation, Ameya LIMAYE of Portland OR (US) for intel corporation, Mark MACDONALD of Beaverton OR (US) for intel corporation, Sung Ki KIM of Portland OR (US) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20145
Abstract: a cooling system includes a cooling fluid bypass to direct cooling fluid around a processor device to a memory module shadowed by the processor device from the cooling fluid flow. the fluid bypass allows the system to direct cooling fluid to the shadowed memory module that has not been used to cool the processor. there are various configurations, allowing the bypassing of different amounts of cooling fluid, allowing system designers to balance a tradeoff between processor heat and memory module heat.
20240407142. HYBRID AND ADAPTIVE COOLING MECHANISMS_simplified_abstract_(intel corporation)
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Uzair Qureshi of Chandler AZ (US) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Marek Piotrowski of Pepowo (PL) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20836
Abstract: hybrid and adaptive cooling systems are described. a method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. other embodiments are described and claimed.
- Intel Corporation
- G01R31/319
- G01R31/3193
- CPC G01R31/31917
- Intel corporation
- G01R31/392
- G01R31/389
- H01M10/48
- H02J7/00
- CPC G01R31/392
- G02B6/42
- CPC G02B6/4228
- H01L25/16
- CPC G02B6/423
- CPC G02B6/4239
- G06F3/01
- G06F3/03
- G06F3/0481
- G06F3/0484
- G06F3/14
- CPC G06F3/017
- G06F9/30
- G06F7/544
- G06T1/20
- CPC G06F9/3001
- G06F9/48
- CPC G06F9/4818
- G06F11/10
- G06F11/07
- CPC G06F11/1068
- G06F15/78
- G06F7/575
- G06F7/58
- G06F9/38
- G06F9/50
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0862
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0888
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/16
- G06F17/18
- G06N3/08
- G06T1/60
- G06T15/06
- H03M7/46
- CPC G06F15/7839
- G06F16/9535
- G06F16/34
- G06F16/9536
- CPC G06F16/9535
- G06N3/048
- CPC G06N3/048
- G06N3/063
- G06F7/78
- G06F9/00
- G06N3/084
- G06N20/00
- CPC G06N3/063
- G09G5/00
- G09G5/36
- G09G5/38
- G09G5/391
- CPC G09G5/005
- G11C29/46
- G11C29/10
- G11C29/12
- CPC G11C29/46
- H01L23/13
- H01L21/48
- H01L23/498
- CPC H01L23/13
- H01L23/48
- H01L21/768
- H01L23/528
- CPC H01L23/481
- H01L23/522
- CPC H01L23/5223
- H01L21/56
- H01L23/538
- CPC H01L25/16
- H01L29/417
- H01L27/088
- H01L29/06
- H01L29/423
- CPC H01L29/41775
- H01L29/66
- H01L21/8234
- H01L29/08
- H01L29/165
- H01L29/78
- CPC H01L29/66795
- H01Q9/04
- H01Q1/22
- CPC H01Q9/0414
- H01R12/52
- H05K3/36
- CPC H01R12/52
- H02M3/07
- CPC H02M3/07
- H03M1/46
- H03K19/17728
- H03M1/40
- CPC H03M1/462
- H04L1/1829
- H04L1/1812
- H04L5/00
- H04W72/1273
- CPC H04L1/1854
- H04L65/75
- H04L65/61
- H04W4/80
- CPC H04L65/75
- H04N19/105
- H04N19/176
- CPC H04N19/105
- H04N19/513
- G06V10/74
- G06V10/82
- CPC H04N19/513
- H04R3/00
- G10L21/028
- G10L25/30
- G10L25/60
- H04R5/027
- H04R29/00
- H04S3/00
- CPC H04R3/005
- H04W24/10
- H04W74/0833
- CPC H04W24/10
- H05K1/11
- CPC H05K1/11
- H05K7/20
- CPC H05K7/20145
- CPC H05K7/20836
