Intel Corporation patent applications on December 26th, 2024
Patent Applications by Intel Corporation on December 26th, 2024
Intel Corporation: 45 patent applications
Intel Corporation has applied for patents in the areas of H01L29/06 (7), G06F9/30 (6), H01L29/775 (6), H01L29/786 (6), H01L29/423 (6) H01L23/481 (3), H01L23/528 (2), G06F17/16 (2), G03F1/38 (1), H03B9/08 (1)
With keywords such as: layer, structure, circuit, device, metal, conductive, memory, coupled, lines, and region in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Sho Kawada of Ogaki (JP) for intel corporation
IPC Code(s): G03F1/38, H01L21/48
CPC Code(s): G03F1/38
Abstract: systems, apparatus, articles of manufacture, and methods to photolithographically pattern materials in integrated circuit packages are disclosed. an example photolithography mask includes: a transparent substrate, and an opaque material supported by the transparent substrate. the opaque material covers a first area of the transparent substrate. the example photolithography mask further includes an optical filter supported by the transparent substrate. the optical filter covers a second area of the transparent substrate. the second area is distinct from the first area. both the opaque material and the optical material are spaced apart from a third area of the transparent substrate
Inventor(s): Gabriel Munguia of Phoenix AZ (US) for intel corporation, Peter Chambers of Phoenix AZ (US) for intel corporation
IPC Code(s): G06F1/12, G06F1/10
CPC Code(s): G06F1/12
Abstract: an apparatus includes a clock monitoring circuit and a multiplexing circuit. the clock monitoring circuit includes an output terminal. the clock monitoring circuit is configured to generate a control signal based on monitoring a plurality of clock signals. the multiplexing circuit is coupled to the output terminal of the clock monitoring circuit and is configured to receive the control signal. the multiplexing circuit includes a first input terminal to receive a first signal generated based on a first clock signal of the plurality of clock signals. the multiplexing circuit includes a second input terminal to receive a second signal generated based on a second clock signal of the plurality of clock signals. the multiplexing circuit includes an output terminal to output one of the first signal or the second signal based on the control signal.
Inventor(s): Mark Hildebrand of Damascus OR (US) for intel corporation, Mariano Tepper of Portland OR (US) for intel corporation, Maria Cecilia Aguerrebere Otegui of Sunnyvale CA (US) for intel corporation, Ishwar Singh Bhati of Portland OR (US) for intel corporation, Theodore Willke of Portland OR (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30038
Abstract: systems, apparatuses and methods may provide for technology that conducts, in accordance with a first instruction, a load of a block of data into a register, wherein the block of data is to include a plurality of lanes, conducts, in accordance with a second instruction, a first bitwise mask application to each lane in the plurality of lanes, and extracts a set of vector dimensions from the block of data based on the first bitwise mask application.
Inventor(s): Robert C. VALENTINE of Kiryat Tivon (IL) for intel corporation, Jesus Corbal SAN ADRIAN of King City OR (US) for intel corporation, Roger Espasa SANS of Barcelona (ES) for intel corporation, Robert D. CAVIN of San Francisco CA (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Santiago Galan DURAN of Molins de Rei (ES) for intel corporation, Jeffrey G. WIEDEMEIER of Austin TX (US) for intel corporation, Sridhar SAMUDRALA of Austin TX (US) for intel corporation, Milind Baburao GIRKAR of Sunnyvale CA (US) for intel corporation, Edward Thomas GROCHOWSKI of San Jose CA (US) for intel corporation, Jonathan Cannon HALL of Hillsboro OR (US) for intel corporation, Dennis R. BRADFORD of Portland OR (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, James C ABEL of Phoenix AZ (US) for intel corporation, Mark CHARNEY of Lexington MA (US) for intel corporation, Seth ABRAHAM of Tempe AZ (US) for intel corporation, Suleyman SAIR of Phoenix AZ (US) for intel corporation, Andrew Thomas FORSYTH of Kirkland WA (US) for intel corporation, Lisa WU of New York NY (US) for intel corporation, Charles YOUNT of Phoenix AZ (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/34, H01L29/66, H01L29/775, H01L29/78, H01L29/786
CPC Code(s): G06F9/30145
Abstract: a vector friendly instruction format and execution thereof. according to one embodiment of the invention, a processor is configured to execute an instruction set. the instruction set includes a vector friendly instruction format. the vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
Inventor(s): Fangfei LIU of Hillsboro OR (US) for intel corporation, Carlos ROZAS of Portland OR (US) for intel corporation, Thomas UNTERLUGGAUER of Carinthia (AT) for intel corporation, Scott CONSTABLE of PORTLAND OR (US) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: an apparatus and method for securely reserving resources for trusted execution. for example, one embodiment of a processor comprises: a plurality of cores, each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors; a first plurality of registers, each register of the first plurality of registers to associate a class of service (clos) value with a corresponding logical processor of the plurality of logical processors; a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding clos value; a first control register of a first logical processor of the plurality of logical processors to be configured with a reserved clos value associated with a trusted control structure; resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved clos value; and enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved clos value.
Inventor(s): Renu Patle of Folsom CA (US) for intel corporation, Hanmanthrao Patli of Folsom CA (US) for intel corporation, Rakesh Mehta of San Jose CA (US) for intel corporation, Hagay Spector of Sderot (IL) for intel corporation, Ivan Herrera Mejia of El Dorado Hills CA (US) for intel corporation, Fylur Rahman Sathakathulla of Folsom CA (US) for intel corporation, Gowtham Raj Karnam of Folsom CA (US) for intel corporation, Mohsin Ali of San Jose CA (US) for intel corporation, Sahar Sharabi of Beer Yaakov (IL) for intel corporation, Abraham Halevi Fraenkel of Jerusalem (IL) for intel corporation, Eyal Pniel of Susya (IL) for intel corporation, Ehud Cohn of Bruchin (IL) for intel corporation, Raghav Ramesh Lakshmi of Folsom CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F11/26, G06F9/30
CPC Code(s): G06F11/26
Abstract: described herein is a generic hardware/software communication (hsc) channel that facilitates the re-use of pre-silicon dpi methods to enable fpga-based post-silicon validation. the hsc channel translates a dpi interface into a hardware fifo based mechanism. this translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. the core logic for the transactor remains the same, while only a small layer of the transactor is converted into the fifo based mechanism.
Inventor(s): Vedvyas Shanbhogue of Austin TX (US) for intel corporation, Stephen J. Robinson of Austin TX (US) for intel corporation, Christopher D. Bryant of Austin TX (US) for intel corporation, Jason W. Brandt of Austin TX (US) for intel corporation
IPC Code(s): G06F15/80, G06F9/30, G06F9/38
CPC Code(s): G06F15/8007
Abstract: a processor includes a widest set of data registers that corresponds to a given logical processor. each of the data registers of the widest set have a first width in bits. a decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. the atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. the atomic store to memory instruction is to indicate memory address information associated with a memory location. an execution unit is coupled with the decode unit. the execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
20240427842. MATRIX OPERATION OPTIMIZATION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Dhiraj D. Kalamkar of Bangalore (IN) for intel corporation, Sasikanth Avancha of Karnataka (IN) for intel corporation
IPC Code(s): G06F17/16, G06F7/78, G06F9/30, G06N3/044, G06N3/084
CPC Code(s): G06F17/16
Abstract: an apparatus to facilitate machine learning matrix processing is disclosed. the apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2d) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
Inventor(s): SUBRAMANIAM MAIYURAN of GOLD RIVER CA (US) for intel corporation, JORGE PARRA of EL DORADO HILLS CA (US) for intel corporation, SUPRATIM PAL of BANGALORE (IN) for intel corporation, ASHUTOSH GARG of FOLSOM CA (US) for intel corporation, SHUBRA MARWAHA of FOLSOM CA (US) for intel corporation, CHANDRA GURRAM of FOLSOM CA (US) for intel corporation, DARIN STARKEY of ROSEVILLE CA (US) for intel corporation, DURGESH BORKAR of FOLSOM CA (US) for intel corporation, VARGHESE GEORGE of FOLSOM CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F9/30, G06F15/80
CPC Code(s): G06F17/16
Abstract: described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.
Inventor(s): Rakesh Kandula of Bangalore (IN) for intel corporation, Srinivasa Ramakrishna STG of Bangalore (IN) for intel corporation
IPC Code(s): G06F30/3315, G06F1/04
CPC Code(s): G06F30/3315
Abstract: methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. an example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (soc) architecture, obtain a timing assertion associated with the soc architecture, determine, using a formal property verification (fpv) tool, valid functional vectors and counter examples for the soc architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.
20240428048. IN-MEMORY PROTECTION FOR NEURAL NETWORKS_simplified_abstract_(intel corporation)
Inventor(s): Wenjie Wang of () for intel corporation, Yi Zhang of () for intel corporation, Yi Qian of () for intel corporation, Wanglei Shen of () for intel corporation, Junjie Li of () for intel corporation, Lingyun Zhu of () for intel corporation
IPC Code(s): G06N3/04
CPC Code(s): G06N3/04
Abstract: technology providing in-memory neural network protection can include a memory to store a neural network, and a processor executing instructions to generate a neural network memory structure having a plurality of memory blocks in the memory, scatter the neural network among the plurality of memory blocks based on a randomized memory storage pattern, and reshuffle the neural network among the plurality of memory blocks based on a neural network memory access pattern. scattering the neural network model can include dividing each layer of the neural network into a plurality of chunks, for each layer, selecting, for each chunk of the plurality of chunks, one of the plurality of memory blocks based on the randomized memory storage pattern, and storing each chunk in the respective selected memory block. the plurality of memory blocks can be organized into a groups of memory blocks and be divided between stack space and heap space.
Inventor(s): Cornelius BUERKLE of Karlsruhe (DE) for intel corporation, Fabian OBORIL of Karlsruhe (DE) for intel corporation, Leon JUNGEMEYER of Markdorf (DE) for intel corporation
IPC Code(s): G06V10/764, B25J9/16, G06T7/50, G06T15/00, G06V20/70
CPC Code(s): G06V10/764
Abstract: a device for detecting a dynamic object, comprising a processor configured to determine a first point density of a first volume around a first point in a first image, the first image being an image of an environment of a robot, the image including image 3d data; determine one or more second point densities, wherein each second point density is a point density of a second volume about a second point, wherein the second point corresponds to the first point in each of one or more second images, the one or more second images of the environment being one or more images taken prior to the first image and including image data corresponding to the three dimensions; and classify the first point as dynamic or static based on a comparison of the first point density and the one or more second point densities.
20240428851. MEMORY WITH CHARGE SHARING BITLINES_simplified_abstract_(intel corporation)
Inventor(s): Amlan GHOSH of Mebane NC (US) for intel corporation, Saroj SATAPATHY of Austin TX (US) for intel corporation, Anandraj DEVARAJAN of Austin TX (US) for intel corporation, Jaydeep KULKARNI of Austin TX (US) for intel corporation, Feroze MERCHANT of Austin TX (US) for intel corporation
IPC Code(s): G11C11/419, G06F12/084, G11C11/412
CPC Code(s): G11C11/419
Abstract: some embodiments relate generally to memory arrays having complementary bitlines. with some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.
Inventor(s): Harshit DHAKAD of Bangalore (IN) for intel corporation, Georgios C. DOGIAMIS of Chandler AZ (US) for intel corporation, Georg SEIDEMANN of Landshut (DE) for intel corporation, Bernd WAIDHAS of Pettendorf (DE) for intel corporation, Thomas WAGNER of Regelsbach (DE) for intel corporation, Manisha DUTTA of Munich (DE) for intel corporation, Michael LANGENBUCH of Munich (DE) for intel corporation
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/42, H01L23/498, H01L23/552
CPC Code(s): H01L23/3128
Abstract: embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. other embodiments may be described and/or claimed.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Chanaka D. MUNASINGHE of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Saurabh ACHARYA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L27/092, H01L29/06, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: integrated circuit structures having deep via bar isolation are described. for example, an integrated circuit structure includes a plurality of gate lines. a plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. a backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. a conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. the conductive structure includes has a cut between first and second conductive structure portions. a cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.
Inventor(s): Jeffrey S. LEIB of Portland OR (US) for intel corporation, Daniel B. O’BRIEN of Beaverton OR (US) for intel corporation, Jennifer ZAVESTOSKI of Portland OR (US) for intel corporation, Hye Kyung KIM of Hillsboro OR (US) for intel corporation, Caitlin Kilroy of Hillsboro OR (US) for intel corporation, Cortnie Vogelsberg of Beaverton OR (US) for intel corporation, Abha Gosavi of Hillsboro OR (US) for intel corporation, Ashish Bhattarai of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/48, H01L23/498
CPC Code(s): H01L23/481
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a plurality of conductive lines, individual ones of the plurality of conductive lines having a liner including molybdenum (mo), and a fill including tungsten (w). the integrated circuit structure also includes an inter-layer dielectric (ild) structure having portions between adjacent ones of the plurality of conductive lines.
Inventor(s): Bok Eng CHEAH of Bukit Gambir (MY) for intel corporation, Choong Kooi CHEE of Batu Uban (MY) for intel corporation, Jackson Chung Peng KONG of Tanjung Tokong (MY) for intel corporation, Wai Ling LEE of Bayan Lepas (MY) for intel corporation, Tat Hin TAN of Batu Uban (MY) for intel corporation
IPC Code(s): H01L23/48, H01L21/768, H01L21/822, H01L23/00, H01L25/16
CPC Code(s): H01L23/481
Abstract: an electronic device comprises an integrated circuit (ic) die. the ic die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (tsv) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked tsv includes a first buried silicon via (bsv) portion having a first width and a second bsv portion having a second width smaller than the first width, and wherein the first bsv portion extends to the first backside surface and the second bsv portion extends to the first active device layer.
20240429155. INTEGRATED CAPACITOR_simplified_abstract_(intel corporation)
Inventor(s): Mamatha YAKKEGONDI VIRUPAKSHAPPA of Munich (DE) for intel corporation, Peter BAUMGARTNER of Munich (DE) for intel corporation, Carla MORAN GUIZAN of Munich (DE) for intel corporation, Philipp RIESS of Munich (DE) for intel corporation, Michael LANGENBUCH of Munich (DE) for intel corporation, Roshini SACHITHANANDAN of Munich (DE) for intel corporation, Jonathan C. JENSEN of Greenville SC (US) for intel corporation
IPC Code(s): H01L23/522, G06F30/367
CPC Code(s): H01L23/5223
Abstract: integrated capacitors are described. in an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. a metal plate is over or beneath the alternating first metal lines and second metal lines. the metal plate is coupled to the first metal lines or the second metal lines by vias.
20240429161. STAGGERED VIA ARCHITECTURE ACROSS UNIT CELLS_simplified_abstract_(intel corporation)
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Tai-Hsuan Wu of Portland OR (US) for intel corporation, Nikolay Ryzhenko Vladimirovich of Beaverton OR (US) for intel corporation, Anand Krishnamoorthy of Portland OR (US) for intel corporation, Mikhail Sergeevich Talalay of Portland OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation, Quan Shi of Portland OR (US) for intel corporation, Ozdemir Akin of Beaverton OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/522
CPC Code(s): H01L23/528
Abstract: techniques are described for designing and forming cells having transistor devices. in an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. a first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. no part of the first via is aligned with any part of the second via along the first direction.
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Sagar Suthram of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528
CPC Code(s): H01L23/528
Abstract: an example ic device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. the plurality of areas includes a first area and a second area. the ic device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L23/00, H01L23/522, H01L23/532
CPC Code(s): H01L23/5283
Abstract: an example ic device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. the device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. a first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. such an arrangement of conductive lines may be referred to as “flipped staircase.”
Inventor(s): Henning BRAUNISCH of Chandler AZ (US) for intel corporation, Chia-Pin CHIU of Tempe AZ (US) for intel corporation, Aleksandar ALEKSOV of Chandler AZ (US) for intel corporation, Hinmeng AU of Phoenix AZ (US) for intel corporation, Stefanie M. LOTZ of Phoenix AZ (US) for intel corporation, Johanna M. SWAN of Scottsdale AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/683, H01L23/00, H01L23/13, H01L25/065
CPC Code(s): H01L23/5385
Abstract: a multi-chip package includes a substrate () having a first side (), an opposing second side (), and a third side () that extends from the first side to the second side, a first die () attached to the first side of the substrate and a second die () attached to the first side of the substrate, and a bridge () adjacent to the third side of the substrate and attached to the first die and to the second die. no portion of the substrate is underneath the bridge. the bridge creates a connection between the first die and the second die. alternatively, the bridge may be disposed in a cavity () in the substrate or between the substrate and a die layer (). the bridge may constitute an active die and may be attached to the substrate using wirebonds ().
Inventor(s): Yi Shi of Chandler AZ (US) for intel corporation, Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Feras Eid of Chandler AZ (US) for intel corporation, Xavier Brun of Hillsboro OR (US) for intel corporation, Johanna Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/67, H01L21/68, H01L21/683
CPC Code(s): H01L24/97
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.
Inventor(s): Bernd Waidhas of Pettendorf (DE) for intel corporation, Thomas Wagner of Regelsbach (DE) for intel corporation, Georg Seidemann of Landshut (DE) for intel corporation, Nicolas Richaud of Rome (IT) for intel corporation, Manisha Dutta of Munich (DE) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Harshit Dhakad of Bangalore (IN) for intel corporation, Michael Langenbuch of Munich (DE) for intel corporation
IPC Code(s): H01L25/18, H01L23/31, H01L25/00, H01L27/01, H01Q1/22, H01Q9/04
CPC Code(s): H01L25/18
Abstract: glass layers and capacitors for use with integrated circuit packages are disclosed. an example integrated circuit (ic) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.
Inventor(s): Krzysztof Domanski of Neubiberg (DE) for intel corporation, Robert Haeussler of Augsburg (DE) for intel corporation
IPC Code(s): H01L27/02, H02H9/04
CPC Code(s): H01L27/0255
Abstract: an integrated circuit device includes an electrostatic discharge (esd) protection circuit comprising a plurality of p+/n-well diodes (p-diodes) and a plurality of n+/p-well (n-diodes) arranged in a stripe geometry, a p-tap anode stripe of the esd protection circuit shared between a first p-diode and a second p-diode of the esd protection circuit, and a n-tap cathode stripe of the esd protection circuit shared between a first n-diode and a second n-diode of the esd protection circuit. other examples are disclosed and claimed.
Inventor(s): Bilal Chehab of Portland OR (US) for intel corporation, Changyok Park of Portland OR (US) for intel corporation, Tuhin Guha Neogi of Sherwood OR (US) for intel corporation, George Joseph Sacks of Ridgefield WA (US) for intel corporation, Christophe Berteau-Pavy of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L29/06, H01L29/417, H01L29/778, H01L29/786
CPC Code(s): H01L27/092
Abstract: a cfet may include two or more transistors stacked over each other. a transistor may be a fet including a forked semiconductor structure. the source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. a branch may include a fin, nanoribbon, etc. the channel region may be between a branch of the source region and a branch of the drain region. the body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. the two bodies may be diagonally arranged with respect to the channel region. the body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, Dax M. CRUM of Beaverton OR (US) for intel corporation, Omair SAADAT of Beaverton OR (US) for intel corporation, Oleg GOLONZKA of Beaverton OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/0924
Abstract: gate-all-around integrated circuit structures having additive metal gates are described. for example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. a first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a p-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. a second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an n-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the p-type conductive layer.
20240429269. INTEGRATED CAPACITOR_simplified_abstract_(intel corporation)
Inventor(s): Peter BAUMGARTNER of Munich (DE) for intel corporation, Mamatha YAKKEGONDI VIRUPAKSHAPPA of Munich (DE) for intel corporation, Carla MORAN GUIZAN of Munich (DE) for intel corporation, Roshini SACHITHANANDAN of Munich (DE) for intel corporation, Philipp RIESS of Munich (DE) for intel corporation, Michael LANGENBUCH of Munich (DE) for intel corporation, Jonathan C. JENSEN of Greenville SC (US) for intel corporation
IPC Code(s): H01G4/30
CPC Code(s): H01L28/87
Abstract: integrated capacitors are described. in an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. a metal plate is over or beneath the alternating first metal lines and second metal lines. a dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Shengsi Liu of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8238, H01L27/092, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. the techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. the forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (gaa) transistors to be included within the same cell. the cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.
Inventor(s): Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: integrated circuit structures having backside source or drain contact selectivity are described. in an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. a second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.
Inventor(s): Shaun MILLS of Hillsboro OR (US) for intel corporation, Makram ABD EL QADER of Hillsboro OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H01L29/41766
Abstract: integrated circuit structures having backside plug last approach are described. in an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. a gate stack is over the plurality of horizontally stacked nanowires or the fin. a conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.
Inventor(s): Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Pratyush P. Buragohain of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L29/06, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a transistor device may be formed with a doped perovskite material as a channel region. the doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.
Inventor(s): Diego Correas-Serrano of Tempe AZ (US) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Henning Braunisch of Phoenix AZ (US) for intel corporation, Neelam Prabhu Gaunkar of Chandler AZ (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation
IPC Code(s): H01P3/16
CPC Code(s): H01P3/16
Abstract: disclosed herein are components for millimeter-wave communication, as well as related methods and systems. in one aspect, a microelectronic support for millimeter-wave communication includes a millimeter-wave communication transmission line, wherein the transmission line includes a trace in a metal layer, wherein the trace is electrically coupled to a via by a via pad in the metal layer; and a ground plane in the metal layer, wherein one or more metal portions contact the via pad and the ground plane.
20240429816. ACTIVE BOOTSTRAPPED-SUPPLY GENERATOR_simplified_abstract_(intel corporation)
Inventor(s): Nachiket Desai of Portland OR (US) for intel corporation, Suhwan Kim of Portland OR (US) for intel corporation
IPC Code(s): H02M3/155, H02M1/088
CPC Code(s): H02M3/155
Abstract: some embodiments include an apparatus having a first node to receive a connection from a gate of a first transistor of a voltage converter; a second node to receive a connection from a gate of a second transistor of the voltage converter; a third node to receive a connection from a node between the first and second transistors; a capacitor including a first plate coupled to the third node; a first driver including an output node coupled to the first node, a first voltage node coupled to the first plate of the capacitor, and a second voltage node coupled to a second plate of the capacitor; a second driver including an output node coupled to the second node; and a circuit including third transistors coupled in series between the second voltage node and a third voltage node.
Inventor(s): Jainaveen SUNDARAM PRIYA of Hillsboro OR (US) for intel corporation, Vinayak HONKOTE of Bangalore (IN) for intel corporation, Ragh KUTTAPPA of Portland OR (US) for intel corporation, Satish YADA of Bangalore (IN) for intel corporation, Tanay KARNIK of Portland OR (US) for intel corporation, Dileep J. KURIAN of Portland OR (US) for intel corporation
IPC Code(s): H03B9/08, H01L25/065
CPC Code(s): H03B9/08
Abstract: various embodiments provide apparatuses, systems, and methods for resonant rotary clocking for die-to-die (d2d) communication in a multi-die system. a base die may include a resonant ring structure to form a plurality of rotary traveling wave oscillators (rtwos) coupled to one another in a rotary oscillator array (roa). the roa may provide synchronized clock signals at deterministic phase points that are tapped from the resonant ring structure. multiple dies may be coupled to the base die and may receive the tapped clock signals from respective tap points. the clock signals may be used for die-to-die communication and/or other purposes. other embodiments may be described and claimed.
Inventor(s): Ritesh Bhat of Portland OR (US) for intel corporation, Steven Callender of Denver CO (US) for intel corporation, Peter Baumgartner of Munich (DE) for intel corporation
IPC Code(s): H03F3/45, H03G1/00, H03G3/00
CPC Code(s): H03F3/45264
Abstract: an integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. other examples are disclosed and claimed.
Inventor(s): Steven K. Hsu of Lake Oswego OR (US) for intel corporation, Amit Agarwal of Hillsboro OR (US) for intel corporation, Abhishek Anil Sharma of Portland OR (US) for intel corporation, Ram K. Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): H03K3/037, H03K17/687
CPC Code(s): H03K3/037
Abstract: embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. the shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. one example implementation uses tri-state keeper sharing. another example implementation uses tri-state keeper and/or pass gate sharing. another example implementation uses pass gate sharing and no keeper.
Inventor(s): Sami Hyvonen of Beaverton OR (US) for intel corporation, Michael Lopez of Chandler AZ (US) for intel corporation, Zachary Brantner of Hillsboro OR (US) for intel corporation
IPC Code(s): H03M1/10, H03K3/03
CPC Code(s): H03M1/1014
Abstract: an apparatus includes a pair of voltage-controlled oscillators (vcos). the pair includes a first vco with a first biasing stage receiving an input voltage signal and a first output stage coupled to the first biasing stage. the first output stage generates a first output frequency signal based on the input voltage signal. the pair also includes a second vco. the second vco includes a second biasing stage receiving the input voltage signal and a second output stage coupled to the second biasing stage. the second output stage generates a second output frequency signal based on the input voltage signal.
Inventor(s): Iosif Gasparakis of Hillsboro OR (US) for intel corporation, Ronen Chayat of Haifa (IL) for intel corporation, John Fastabend of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L41/082, H04L67/00, H04L67/04
CPC Code(s): H04L41/082
Abstract: a compute node coupled to a computer network via a computing device that includes communications for communicating with the computer network and persistent instructions for providing control functions to the computing device, wherein the control functions are defined by protocol data. an update control module of the computing device may receive update data from a remote node in the computer network via the communications, wherein the update data includes new protocol data for the persistent instructions. a protocol parser module may parse the update data and generate metadata relating to the update data. a classifier module may receive rules for the control functions, wherein the rules are based at least in part on the update data and metadata. a compiler may compile the parsed update data to the persistent instructions for providing new control functions to the computing device based at least in part on the received rules.
20240430634. METHOD AND SYSTEM OF BINAURAL AUDIO EMULATION_simplified_abstract_(intel corporation)
Inventor(s): Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Samuel Kincaid of Santa Clara CA (US) for intel corporation, Willem Beltman of West Linn OR (US) for intel corporation, Jesus Rodrigo Ferrer Romero of Guadalajara (MX) for intel corporation
IPC Code(s): H04S7/00, H04R3/00, H04R5/04
CPC Code(s): H04S7/301
Abstract: a system, article, device, apparatus, and method of binaural audio emulation comprises receiving, by processor circuitry, multiple audio signals from multiple microphones and overlapping in a same time and associated with a same at least one audio source. the method also comprises generating binaural audio signals comprising inputting at least one version of the multiple audio signals into a neural network.
20240430743. BLOCK ACKNOWLEDGMENT OVERHEAD REDUCTION_simplified_abstract_(intel corporation)
Inventor(s): Po-Kai HUANG of San Jose CA (US) for intel corporation, Daniel BRAVO of Portland OR (US) for intel corporation, Danny ALEXANDER of Neve Efraim Monoson (IL) for intel corporation, Juan FANG of Portland OR (US) for intel corporation, Nebo IDAN of Zichron Ya'akov (IL) for intel corporation, Laurent CARIOU of Milizac (FR) for intel corporation
IPC Code(s): H04W28/06, H04L1/00, H04L1/1607, H04L5/00
CPC Code(s): H04W28/06
Abstract: this disclosure describes systems, methods, and devices related to block acknowledgment (ack) overhead reduction. a device may receive a soliciting physical layer convergence protocol data unit (ppdu). the device may encode a multiple station device (multi-sta) block acknowledgment (ba) as a response to the soliciting ppdu. the device may transmit the multi-sta ba in response to the ppdu. the device may manage multiple per association identification (aid) traffic identifier (tid) information (per aid tid info) entries with the same aid and tid in the same multi-sta ba. the device may set the per aid tid info entries with the same aid and tid to be consecutive.
Inventor(s): Alonso Rodriguez Chacon of La Guacima (CR) for intel corporation, Arturo Navarro Alvarez of San Isidro (CR) for intel corporation, Jeff Ku of Taipei (TW) for intel corporation
IPC Code(s): H05K7/14, H05K1/02
CPC Code(s): H05K7/142
Abstract: example fittings that combine standoffs and springs for supporting thermal solutions are disclosed herein. an example electronic device includes a chassis; a substrate; a thermal solution; and a fitting to separate the substrate from the chassis and to separate the thermal solution from the substrate, the fitting including a standoff end and a spring end.
Inventor(s): Jeff Ku of Taipei City (TW) for intel corporation, Chi Chou Cheng of Taoyuan City (TW) for intel corporation, Jeffrey Ho of New Taipei City (TW) for intel corporation, Chih-Tsung Hu of New Taipei City (TW) for intel corporation, Srinivasarao Konakalla of Bangalore (IN) for intel corporation, Tsung-Kai Lin of New Taipei City (TW) for intel corporation, Arnab Sen of Whitefield (IN) for intel corporation, Chiu-Chun Wang of Taoyuan City (TW) for intel corporation, Jiacheng Wu of Taipei City (TW) for intel corporation
IPC Code(s): H05K7/20, G06F1/20
CPC Code(s): H05K7/20154
Abstract: heat exchange apparatuses and methods for hyperbaric cooling fan applications such as computing devices. the apparatus comprises a material with high thermal conductivity and is configured to be overlaid on an internal surface of the housing, such that an internal surface of the apparatus is exposed to the hot air flowing inside the housing, and an external surface of the apparatus occludes at least some of the existing through-holes of the housing. in operation, the apparatus converts the through-holes into passive heat exchanging regions that passively transfer heat from inside the housing to outside the housing, which brings the internal air temperature and junction temperature (tj) of the heat generating components down. provided embodiments do not require reworking of the original industrial design (id) of the housing.
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/20
Abstract: a transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. a first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. a second portion of the gate electrode is over a first portion of the drain region in the second direction. the source contact is over at least part of the source region. the drain contact is over a second portion of the drain region. a distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.
Inventor(s): Abhishek A. Sharma of Portland OR (US) for intel corporation, Wilfred Gomes of Portland OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: ic devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. an example ic device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. first capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. ic devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1t-1c memory technology and enable high-density embedded memory compatible with advanced cmos processes.
Intel Corporation patent applications on December 26th, 2024
- Intel Corporation
- G03F1/38
- H01L21/48
- CPC G03F1/38
- Intel corporation
- G06F1/12
- G06F1/10
- CPC G06F1/12
- G06F9/30
- CPC G06F9/30038
- G06F9/34
- H01L29/66
- H01L29/775
- H01L29/78
- H01L29/786
- CPC G06F9/30145
- G06F9/50
- CPC G06F9/5027
- G06F11/26
- CPC G06F11/26
- G06F15/80
- G06F9/38
- CPC G06F15/8007
- G06F17/16
- G06F7/78
- G06N3/044
- G06N3/084
- CPC G06F17/16
- G06F30/3315
- G06F1/04
- CPC G06F30/3315
- G06N3/04
- CPC G06N3/04
- G06V10/764
- B25J9/16
- G06T7/50
- G06T15/00
- G06V20/70
- CPC G06V10/764
- G11C11/419
- G06F12/084
- G11C11/412
- CPC G11C11/419
- H01L23/31
- H01L21/56
- H01L23/00
- H01L23/42
- H01L23/498
- H01L23/552
- CPC H01L23/3128
- H01L23/48
- H01L27/092
- H01L29/06
- H01L29/423
- CPC H01L23/481
- H01L21/768
- H01L21/822
- H01L25/16
- H01L23/522
- G06F30/367
- CPC H01L23/5223
- H01L23/528
- CPC H01L23/528
- H01L23/532
- CPC H01L23/5283
- H01L23/538
- H01L21/683
- H01L23/13
- H01L25/065
- CPC H01L23/5385
- H01L21/67
- H01L21/68
- CPC H01L24/97
- H01L25/18
- H01L25/00
- H01L27/01
- H01Q1/22
- H01Q9/04
- CPC H01L25/18
- H01L27/02
- H02H9/04
- CPC H01L27/0255
- H01L29/417
- H01L29/778
- CPC H01L27/092
- H01L21/8238
- CPC H01L27/0924
- H01G4/30
- CPC H01L28/87
- H01L29/08
- CPC H01L29/0673
- CPC H01L29/41733
- CPC H01L29/41766
- CPC H01L29/42392
- H01P3/16
- CPC H01P3/16
- H02M3/155
- H02M1/088
- CPC H02M3/155
- H03B9/08
- CPC H03B9/08
- H03F3/45
- H03G1/00
- H03G3/00
- CPC H03F3/45264
- H03K3/037
- H03K17/687
- CPC H03K3/037
- H03M1/10
- H03K3/03
- CPC H03M1/1014
- H04L41/082
- H04L67/00
- H04L67/04
- CPC H04L41/082
- H04S7/00
- H04R3/00
- H04R5/04
- CPC H04S7/301
- H04W28/06
- H04L1/00
- H04L1/1607
- H04L5/00
- CPC H04W28/06
- H05K7/14
- H05K1/02
- CPC H05K7/142
- H05K7/20
- G06F1/20
- CPC H05K7/20154
- H10B12/00
- CPC H10B12/20
- H10B53/30
- CPC H10B53/30
