Intel Corporation patent applications on December 19th, 2024
Patent Applications by Intel Corporation on December 19th, 2024
Intel Corporation: 30 patent applications
Intel Corporation has applied for patents in the areas of H01L25/065 (6), H01L23/00 (5), H01L23/538 (5), G06F9/30 (3), G06T1/20 (3) H01L23/562 (2), G06T1/20 (2), B25J9/1612 (1), H01L23/49838 (1), H04W74/0808 (1)
With keywords such as: circuit, vector, die, layer, example, device, semiconductor, structure, package, and substrate in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): David Gonzalez Aguirre of Portland OR (US) for intel corporation, Julio Zamora Esquivel of Zapopan (MX) for intel corporation, Leobardo Campos Macias of Guadalajara (MX) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation
IPC Code(s): B25J9/16
CPC Code(s): B25J9/1612
Abstract: various aspects of techniques, systems, and use cases for selecting grasping configurations for a robot are disclosed. geometric primitives are generated to model the robot for grasping and manipulation by the robot. the geometric primitives are combined using various functions to determine which configuration to use. the instantaneous configuration is determined, as well as the forward kinematics and links to determine active geometric primitives of the gripper. the active geometric primitives are used to approximate an x, y, and z coordinate of each point of the primitives, a distance between the point and a grasping target, and an associated surface link. the configurations are ranked based on grasping metrics and one of the configurations selected to use accordingly.
20240418825. RADAR APPARATUS, SYSTEM, AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Ofer Markish of Ra'anana (IL) for intel corporation, Ophir Shabtay of Tsofit (IL) for intel corporation, Thushara Hewavithana of Chandler AZ (US) for intel corporation, Arnaud Amadjikpe of Beaverton OR (US) for intel corporation, Shengbo Xu of Newark CA (US) for intel corporation
IPC Code(s): G01S7/35, B60W60/00, G01S13/89, H01Q1/32, H01Q21/22
CPC Code(s): G01S7/352
Abstract: some demonstrative aspects include radar apparatuses, devices, systems and methods. in one example, an apparatus may include a plurality of transmit (tx) antennas to transmit radar tx signals, and a plurality of receive (rx) antennas to receive radar rx signals. for example, the radar rx signals may be based on the radar tx signals. the apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. in other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.
Inventor(s): Peng Li of Palo Alto CA (US) for intel corporation, Joel Martinez of Hayward CA (US) for intel corporation, Jon Long of Scotts Valley CA (US) for intel corporation
IPC Code(s): G02B6/43, H01L23/00, H01L23/498, H01L23/538, H01L25/065, H04B10/40
CPC Code(s): G02B6/43
Abstract: a multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. the main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. the transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. the transceiver die has physical-layer circuits that directly drive the optical engine. an optical cable can be connected directly to the optical engine of the multichip package.
Inventor(s): Martin LANGHAMMER of Alderbury (GB) for intel corporation, Alexander F. HEINECKE of () for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/3001
Abstract: a processor of an aspect includes decoder circuitry to decode an instruction indicating a source floating-point operand, having a floating-point data element, and indicating a destination register. the element has a sign bit, an n-bit first exponent value, and m bits. execution circuitry of the processor is to interpret the m bits as an m-bit significand, when the n-bit first exponent value is not all zeroes or all ones, and interpret the m bits as including a second exponent value in at least one of the m bits, and a less than m-bit significand in at least one other of the m bits, when the n-bit first exponent value is either all zeroes or all ones. the execution unit is to perform an operation on the source floating-point operand to generate a result floating-point operand, and to store the result floating-point operand in the destination register.
Inventor(s): Prashant D. Chaudhari of Folsom CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation
IPC Code(s): G06F9/30, G06T1/20
CPC Code(s): G06F9/30185
Abstract: described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. the performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. in one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective contexts used to execute the workloads, the specific instructions executed respectively by the workloads, or the datatypes used respectively by the workloads.
Inventor(s): Mariano Tepper of Portland OR (US) for intel corporation, Ishwar Singh Bhati of Portland OR (US) for intel corporation, Maria Cecilia Aguerrebere Otegui of Sunnyvale CA (US) for intel corporation, Mark Hildebrand of Damascus OR (US) for intel corporation, Theodore Willke of Portland OR (US) for intel corporation
IPC Code(s): G06F16/2458, G06F16/22, G06F16/2457
CPC Code(s): G06F16/2458
Abstract: technology as described herein provides for accessing input vectors and a query vector, the input vectors each having a dimensionality, the query vector associated with a query and having a dimensionality, applying a first vector transformation to the input vectors to generate primary vectors, each of the primary vectors having a dimensionality smaller than the dimensionality associated with the input vectors, applying a second vector transformation to the query vector to generate a modified query vector, the modified query vector having a dimensionality smaller than the dimensionality of the query vector, and conducting a similarity search on the primary vectors based on the modified query vector to generate one or more candidates for the query. in embodiments a first component of the first vector transformation is determined based on an algorithm and a second component of the second vector transformation is determined based on the same algorithm.
20240419877. PRE-SILICON POWER ANALYSIS_simplified_abstract_(intel corporation)
Inventor(s): John CRESSMAN of Jefferson MA (US) for intel corporation, Gian FRANCISCO of Westford MA (US) for intel corporation, David GRUNDMANN of Westborough MA (US) for intel corporation, Arun SUBBIAH of Folsom CA (US) for intel corporation
IPC Code(s): G06F30/327, G06F30/31
CPC Code(s): G06F30/327
Abstract: provided is a power estimation tool for estimating power from an rtl simulation waveform. the tool may use an inference engine that uses an ml trained power estimation model.
20240419883. THERMAL CONDUCTIVITY IN INTEGRATED CIRCUITS_simplified_abstract_(intel corporation)
Inventor(s): Lei JIANG of Camas WA (US) for intel corporation, Daniel CHRISTENSEN of Portland OR (US) for intel corporation, Daniel PANTUSO of Portland OR (US) for intel corporation, Kambiz KOMEYLI of Portland OR (US) for intel corporation, Jeffrey HICKS of Banks OR (US) for intel corporation, Manjunath SHAMANNA of Austin TX (US) for intel corporation
IPC Code(s): G06F30/392, G06F30/394
CPC Code(s): G06F30/392
Abstract: disclosed is an integrated circuit with a metallization stack that has thermal tower assemblages formed from wires in two or more metal layers to assist in dissipating heat out of the metallization stack.
Inventor(s): Eran Ben-Avi of Haifa (IL) for intel corporation, Neta Zmora of Tzur Moshe (IL) for intel corporation, Guy Jacob of Netanya (IL) for intel corporation, Lev Faivishevsky of Kfar Saba (IL) for intel corporation, Jeremie Dreyfuss of Tel-Aviv (IL) for intel corporation, Tomer Bar-On of Petah Tikva (IL) for intel corporation, Jacob Subag of Kiryat Haim (IL) for intel corporation, Yaniv Fais of Tel-Aviv (IL) for intel corporation, Shira Hirsch of Jerusalem (IL) for intel corporation, Orly Weisel of Elazar (IL) for intel corporation, Zigi Walter of Haifa (IL) for intel corporation, Yarden Oren of Jerusalem (IL) for intel corporation
IPC Code(s): G06N3/063, G06N3/044, G06N3/045, G06N3/084
CPC Code(s): G06N3/063
Abstract: in an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. other embodiments are also disclosed and claimed.
20240420273. DYNAMIC ACCUMULATOR ALLOCATION_simplified_abstract_(intel corporation)
Inventor(s): Andrew Thomas FORSYTH of Kirkland WA (US) for intel corporation
IPC Code(s): G06T1/20, G06F9/30
CPC Code(s): G06T1/20
Abstract: a system that includes a graphics processing unit (gpu) that includes at least one processor and multiple registers. in some examples, based on execution of an instruction by at least one of the at least one processor to allocate a particular number of registers to a thread, assign the number of registers to the thread. in some examples, a compiler is to consider register demands for a code segment and number of available registers in determining a number of registers to allocate to the code segment.
Inventor(s): Prashant D. Chaudhari of Folsom CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation
IPC Code(s): G06T1/20
CPC Code(s): G06T1/20
Abstract: described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. the performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. in one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective shader programs, fixed function units, and/or processing resources used to execute the workloads.
Inventor(s): Jiaxiang Jiang of Santa Clara CA (US) for intel corporation, Omesh Tickoo of Portland OR (US) for intel corporation, Mahesh Subedar of Portland OR (US) for intel corporation, Ibrahima Jacques Ndiour of Chandler AZ (US) for intel corporation
IPC Code(s): G06V20/40, G06V10/25, G06V10/77
CPC Code(s): G06V20/46
Abstract: methods and apparatus to detect anomalies in video data are disclosed. an example apparatus disclosed herein generates a reconstructed feature vector corresponding to an input feature vector representative of a video segment, the reconstructed feature vector based on a transformation applied to the input feature vector and an inverse of the transformation applied to an output of the transformation, the input feature vector and the reconstructed feature vector including features associated with a plurality of dimensions including a time dimension. the disclosed example apparatus also generates an error vector based on a difference between the input feature vector and the reconstructed feature vector. the disclosed example apparatus further generates an anomaly map based on sums of elements of the error vector across at least the time dimension, the anomaly map corresponding to the video segment.
Inventor(s): Hwichan Jun of Portland OR (US) for intel corporation, Edward Yeh of San Jose CA (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H01L21/823456
Abstract: an ic device includes a gate electrode having multiple lengths. the length of a first portion of the gate electrode, which is over a channel region in a semiconductor structure, may be longer (e.g., about 0.5-3 nm longer) than the length of a second portion of the gate electrode, which is over a channel region in another semiconductor structure. the pitches at the two portions of the gate electrode may be the same or substantially similar. the lengths of the gate electrode can be differentiated by using dry clean based removal of a dielectric material surrounding the semiconductor structures. a larger amount of the dielectric material may be removed at a first region than a second region so that the gap at the first region can be longer than the gap at the second region. a conductive material may be provided to fill the gaps to form the gate electrode.
Inventor(s): Lianchang DU of Kunshan (CN) for intel corporation, Jeffory L. SMALLEY of Olympia WA (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation, Eric W. BUDDRIUS of Hillsboro OR (US) for intel corporation, Yi ZENG of Shanghai (CN) for intel corporation, Xinjun ZHANG of Shanghai (CN) for intel corporation, Maoxin YIN of Shanghai (CN) for intel corporation, Zhichao ZHANG of Chandler AZ (US) for intel corporation, Chen ZHANG of Shanghai (CN) for intel corporation, Yuehong FAN of Shanghai (CN) for intel corporation, Mingli ZHOU of Shanghai (CN) for intel corporation, Guoliang YING of Shanghai (CN) for intel corporation, Yinglei REN of Shanghai (CN) for intel corporation, Chong J. ZHAO of West Linn OR (US) for intel corporation, Jun LU of Shanghai (CN) for intel corporation, Kai WANG of Portland OR (US) for intel corporation, Timothy Glen HANNA of Tigard OR (US) for intel corporation, Vijaya K. BODDU of Pleasanton CA (US) for intel corporation, Mark A. SCHMISSEUR of Phoenix AZ (US) for intel corporation, Lijuan FENG of Shanghai (CN) for intel corporation
IPC Code(s): H01L23/367, H01L23/538, H01L25/065, H01R13/627
CPC Code(s): H01L23/3675
Abstract: a semiconductor chip package is described. the semiconductor chip package has a substrate. the substrate has side i/os on the additional surface area of the substrate. the side i/os are coupled to i/os of a semiconductor chip within the semiconductor chip package. a cooling assembly has also been described. the cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side i/os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second i/os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.
20240421042. INTEGRATED CIRCUIT DEVICE WITH VERTICAL VIA PIN_simplified_abstract_(intel corporation)
Inventor(s): Jung Kyu Chae of Incheon (KR) for intel corporation
IPC Code(s): H01L23/49
CPC Code(s): H01L23/49
Abstract: an ic device (e.g., a standard cell) may have one or more vertical via pins for power supply or signal transmission. the ic device may also include semiconductor structures stacked over each other along the vertical axis of the ic device and electrodes stacked over each other along the horizontal axis. an electrode may be a gate electrode over a channel region of a transistor or a trench electrode over a source region or drain region of a transistor. a vertical via pin may be connected to a gate electrode or trench electrode. a vertical via pin may be an input pin or output pin. a vertical via pin may have a longitudinal axis that is perpendicular or substantially perpendicular to the horizontal axis and the vertical axis of the ic device. the ic device may have an eeq cell that includes cells having different layouts of vertical via pins.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Ji Yong Park of Chandler AZ (US) for intel corporation, Kyu Oh Lee of Chandler AZ (US) for intel corporation, Sheng Li of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Sameer Paital of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/495, H01L21/768
CPC Code(s): H01L23/49513
Abstract: various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. the present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.
Inventor(s): Tolga Acikalin of San Jose CA (US) for intel corporation, Shuhei Yamada of Vancouver WA (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Tae Young Yang of Portland OR (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/3205, H01L23/00, H01L23/15, H01L23/49, H01L23/538, H01L23/544, H01L25/065
CPC Code(s): H01L23/49838
Abstract: wireless interconnects in integrated circuit package substrates with glass cores are disclosed. an example apparatus includes a semiconductor die and a substrate including a glass core. the apparatus also includes a pluggable interconnect including a portion of the glass core. the pluggable interconnect includes a transmission line extending along the portion of the glass core.
20240421073. LOCALIZED HIGH DENSITY SUBSTRATE ROUTING_simplified_abstract_(intel corporation)
Inventor(s): Robert STARKSTON of Phoenix AZ (US) for intel corporation, Debendra MALLIK of Chandler AZ (US) for intel corporation, John S. GUZEK of Chandler AZ (US) for intel corporation, Chia-Pin CHIU of Tempe AZ (US) for intel corporation, Deepak KULKARNI of Chandler AZ (US) for intel corporation, Ravi V. MAHAJAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/56, H01L23/00, H01L23/538, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/5226
Abstract: embodiments of a system and methods for localized high density substrate routing are generally described herein. in one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. the medium can include low density routing therein. the interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. the interconnect element can include high density routing therein. the dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
20240421101. BACKSIDE CONTACT BASED DIE EDGE GUARD RINGS_simplified_abstract_(intel corporation)
Inventor(s): Sunny CHUGH of Hillsboro OR (US) for intel corporation, Rahim KASIM of Portland OR (US) for intel corporation, Mohammad Enamul KABIR of Portland OR (US) for intel corporation, Jasmeet S. CHAWLA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Joseph D’SILVA of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/50, H01L23/58
CPC Code(s): H01L23/562
Abstract: guard rings are described. in an example, a semiconductor die includes an active device layer including a plurality of nanoribbon devices. a dielectric structure is over the active device layer. a first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the plurality of nanoribbon devices. a plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. a plurality of direct backside contacts extend to the active device layer. a plurality of backside metallization structures is beneath the plurality of direct backside contacts. the plurality of direct backside contacts are connected to the plurality of backside metallization structures. a second die-edge metal guard ring is laterally around the plurality of backside metallization structures.
Inventor(s): Chunqing Peng of Chandler AZ (US) for intel corporation, Tony Dambrauskas of Chandler AZ (US) for intel corporation, Mohan Yasodharababu of Phoenix AZ (US) for intel corporation, Yuvraj Singh of Chandler AZ (US) for intel corporation, Praneeth Nampally of Chandler AZ (US) for intel corporation, Robert Stingel of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L23/16, H01L23/31, H01L25/065
CPC Code(s): H01L23/562
Abstract: disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. in some embodiments, a microelectronic assembly may include a first die having a first surface, an opposing second surface, and a first footprint; a second die electrically coupled to the second surface of the first die and having a second footprint, wherein the second footprint is smaller than the first footprint; and a mold material on the second surface of the first die and surrounding the second die, the mold material including a trench.
Inventor(s): Chun-Hao Lin of Chandler AZ (US) for intel corporation, Teng Sun of Chandler AZ (US) for intel corporation, Yuxin Fang of Chandler AZ (US) for intel corporation
IPC Code(s): H01L27/01, H01G4/33
CPC Code(s): H01L27/016
Abstract: disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. in some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.
Inventor(s): Ritesh Agarwal of Munich (DE) for intel corporation, Harshit Dhakad of Bangalore (IN) for intel corporation, Krzysztof Domanski of Neubiberg (DE) for intel corporation
IPC Code(s): H01L27/02
CPC Code(s): H01L27/0285
Abstract: techniques and mechanisms for selectively disabling functionality of a power clamp circuit which is to mitigate damage due to electrostatic discharge (esd). in an embodiment, a shut-off circuit is coupled to receive a control signal which indicates an actual or expected future power state transition of a load. the power clamp circuit comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. based on a filtered version of the control signal, the shut-off circuit generates a first one or more signals to selectively disable the pull-up circuit. the shut-off circuit further generates a second one or more signals, based on the filtered version of the control signal, to selectively disable the pull-down circuit.
Inventor(s): Joseph D’SILVA of Hillsboro OR (US) for intel corporation, Mauro J. KOBRINSKY of Portland OR (US) for intel corporation, Ehren MANNEBACH of Tigard OR (US) for intel corporation, Shaun MILLS of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/423, H01L29/775, H01L29/78
CPC Code(s): H01L27/088
Abstract: integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. in an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. a gate stack is over the plurality of horizontally stacked nanowires or the fin. an epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. a conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. the conductive source or drain contact is in a cavity in the isolation layer. the isolation layer extends laterally beneath the gate stack.
Inventor(s): Denzil Frost of Rio Rancho ID (US) for intel corporation, Sudipto Naskar of Portland OR (US) for intel corporation
IPC Code(s): H01G4/30
CPC Code(s): H01L28/92
Abstract: disclosed herein are ic devices with 3d interlocked corrugated capacitor structures. an example ic device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Thomas O’BRIEN of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Anindya DASGUPTA of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L29/06, H01L29/08, H01L29/40, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H01L29/41733
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for creating flyover trench connectors within a transistor structure, where a first portion of the trench connector is electrically coupled with a first epitaxial structure and where a second portion of the trench connector extends above but is not electrically coupled with a second epitaxial structure. other embodiments may be described and/or claimed.
Inventor(s): Tolga Acikalin of San Jose CA (US) for intel corporation, Tae Young Yang of Portland OR (US) for intel corporation, Shuhei Yamada of Vancouver WA (US) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation
IPC Code(s): H01Q1/22, H01L23/15, H01L23/538, H01L25/065, H01P3/08, H01Q13/02
CPC Code(s): H01Q1/2283
Abstract: wireless interconnects in integrated circuit package substrates with glass cores are disclosed. an example apparatus includes a semiconductor die. the example apparatus further includes a package substrate supporting the semiconductor die. the package substrate includes a glass core. the example apparatus also includes an antenna within the glass core.
Inventor(s): Xiang LI of Portland OR (US) for intel corporation, George VERGIS of Portland OR (US) for intel corporation
IPC Code(s): H01R12/70, H01R13/20, H05K1/11
CPC Code(s): H01R12/707
Abstract: examples include techniques for a module connector design to improve pin connection. the techniques include covering top and bottom cavities of a connector that includes connector pins arranged to be coupled with a printed circuit board via a reflow soldering process to prevent a film from forming on the connector pins during or after the reflow soldering process.
Inventor(s): Harshit Dhakad of Bangalore (IN) for intel corporation, Yossi Shoshany of Petach Tikva (IL) for intel corporation, Sergey Sofer of Rishon Lezion (IL) for intel corporation, Suhwan Kim of Portland OR (US) for intel corporation, Krzysztof Domanski of Neubiberg (DE) for intel corporation
IPC Code(s): H02H9/04, H01L27/02, H03K19/003
CPC Code(s): H02H9/046
Abstract: techniques and mechanisms for a dc-dc voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (esd). in an embodiment, a protection circuit of the dc-dc voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. a voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an esd event. during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. in another embodiment, a resistor-capacitor (rc) circuit automatically transitions the protection circuit from the first mode.
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W74/0808
CPC Code(s): H04W74/0808
Abstract: this disclosure describes systems, methods, and devices related to prioritized access. a device may broadcast advertisements to stations (stas) indicating specific service periods for prioritized channel access within a basic service set (bss). the device may send an indication to the stas queued for prioritized access to transmit reservation signals at a predetermined time post a start of a contention period. the device may send contention window (cw) parameter settings to the stas to control their backoff counter values during periods of prioritized access contention. the device may detect reception of overlapping reservation signals from stas and enforce clear channel assessment (cca) protocol to cause stas to defer their transmissions.
Inventor(s): Srinivas B REDDY of Bangalore (IN) for intel corporation, Jayprakash THAKUR of Bangalore (IN) for intel corporation, Arvind S of Bangalore (IN) for intel corporation, Rajasekar A of Nagercoil (IN) for intel corporation, Bindu Prabhakar RAO of Bangalore (IN) for intel corporation, Pali BARMATE of Balaghat (IN) for intel corporation
IPC Code(s): H05K1/02, H05K1/03, H05K3/46
CPC Code(s): H05K1/0298
Abstract: the present disclosure generally relates to a multi-layer printed circuit board. the multi-layer printed circuit board may include a core layer and a first prepreg layer adjacent the core layer. the core layer may include a first biodegradable material sandwiched between two electrically conducting layers. a method for forming a multi-layer printed circuit board is also provided herein.
Intel Corporation patent applications on December 19th, 2024
- Intel Corporation
- B25J9/16
- CPC B25J9/1612
- Intel corporation
- G01S7/35
- B60W60/00
- G01S13/89
- H01Q1/32
- H01Q21/22
- CPC G01S7/352
- G02B6/43
- H01L23/00
- H01L23/498
- H01L23/538
- H01L25/065
- H04B10/40
- CPC G02B6/43
- G06F9/30
- CPC G06F9/3001
- G06T1/20
- CPC G06F9/30185
- G06F16/2458
- G06F16/22
- G06F16/2457
- CPC G06F16/2458
- G06F30/327
- G06F30/31
- CPC G06F30/327
- G06F30/392
- G06F30/394
- CPC G06F30/392
- G06N3/063
- G06N3/044
- G06N3/045
- G06N3/084
- CPC G06N3/063
- CPC G06T1/20
- G06V20/40
- G06V10/25
- G06V10/77
- CPC G06V20/46
- H01L21/8234
- H01L27/088
- CPC H01L21/823456
- H01L23/367
- H01R13/627
- CPC H01L23/3675
- H01L23/49
- CPC H01L23/49
- H01L23/495
- H01L21/768
- CPC H01L23/49513
- H01L21/3205
- H01L23/15
- H01L23/544
- CPC H01L23/49838
- H01L23/522
- H01L21/56
- H01L25/00
- H01L25/18
- CPC H01L23/5226
- H01L23/50
- H01L23/58
- CPC H01L23/562
- H01L23/16
- H01L23/31
- H01L27/01
- H01G4/33
- CPC H01L27/016
- H01L27/02
- CPC H01L27/0285
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/78
- CPC H01L27/088
- H01G4/30
- CPC H01L28/92
- H01L29/417
- H01L29/08
- H01L29/40
- H01L29/778
- H01L29/786
- CPC H01L29/41733
- H01Q1/22
- H01P3/08
- H01Q13/02
- CPC H01Q1/2283
- H01R12/70
- H01R13/20
- H05K1/11
- CPC H01R12/707
- H02H9/04
- H03K19/003
- CPC H02H9/046
- H04W74/0808
- CPC H04W74/0808
- H05K1/02
- H05K1/03
- H05K3/46
- CPC H05K1/0298
