Intel Corporation patent applications on August 8th, 2024
Patent Applications by Intel Corporation on August 8th, 2024
Intel Corporation: 18 patent applications
Intel Corporation has applied for patents in the areas of A63F13/355 (1), H01L23/495 (1), H01L25/00 (1), H01L23/00 (1), H01L27/092 (1) A63F13/355 (1), H01L25/00 (1), H04L63/1416 (1), H04L47/826 (1), H04L47/125 (1)
With keywords such as: circuitry, memory, circuit, substrate, input, processor, operating, apparatus, group, and nanowires in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Minggui CAO of Shanghai (CN) for intel corporation, Jian Jun CHEN of Shanghai (CN) for intel corporation, Qian OUYANG of Shanghai (CN) for intel corporation, Yi QIAN of Shanghai (CN) for intel corporation, Junjun SHAN of Shanghai (CN) for intel corporation, Xiangyang WU of Shanghai (CN) for intel corporation
IPC Code(s): A63F13/355, A63F13/335, H04L67/568
CPC Code(s): A63F13/355
Abstract: a control apparatus (), control device, control method and computer program for controlling one or more parameters of a hypervisor () and an apparatus, device, method, and computer program for a virtual machine (). the control apparatus () comprises circuitry configured to obtain information on respective performance targets of two or more virtual machines () being hosted by the hypervisor (). the circuitry is configured to set the one or more parameters of the hypervisor () to one or more initial values. the circuitry is configured to obtain respective results of a benchmark being run in the two or more virtual machines (), the results of the benchmark indicating a performance of the respective virtual machines () with respect to the respective performance targets, with the results of the benchmark being affected by the one or more parameters. the circuitry is configured to adjust the one or more parameters based on the results of the benchmark and based on the respective performance targets. the circuitry is configured to repeat obtaining the respective results of the benchmark and adjusting the one or more parameters until a termination condition is met.
Inventor(s): Rakesh KANDULA of Bangalore (IN) for intel corporation, Michaël Carl NÈVE DE MÉVERGNIES of Guidel (FR) for intel corporation
IPC Code(s): G01R31/3185, G01R31/317, G06F21/72
CPC Code(s): G01R31/318588
Abstract: examples include techniques for infield testing of cryptographic circuitry located on a die. the infield testing to include providing a pass or fail status of an infield test scan of the cryptographic circuitry based on comparing an output generated by the cryptographic circuitry during a test run to a signature. the output generated by the cryptographic circuitry is in response to an input generated by a linear-feedback shift register during the test run.
Inventor(s): Sang Yup Kim of Sunnyvale CA (US) for intel corporation, Myung Jin Yim of San Jose CA (US) for intel corporation, Woosung Kim of Mountain View CA (US) for intel corporation
IPC Code(s): G02B6/43, G02B6/12, G02B6/122, G02B6/42
CPC Code(s): G02B6/43
Abstract: an interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.
20240264530. LIGHT RESPONSIVE PHOTORESISTS AND METHODS_simplified_abstract_(intel corporation)
Inventor(s): Ryan Carrazzone of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Brandon Rawlings of Chandler AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): G03F7/16, C08G75/20, G03F7/038, G03F7/039
CPC Code(s): G03F7/168
Abstract: light responsive photoresists, and methods of using light responsive photoresists in processes, such as lithography processes. the light responsive photoresists may include a polymer featuring a photocleavable group. due to the photocleavable group, the polymer may depolymerize when irradiated with one or more wavelengths of light. the depolymerized products may be in the gas phase.
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Bhushan M. Borole of Rancho Cordova CA (US) for intel corporation, Wenyin Fu of Folsom CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06F1/3234, G06F1/3237, G06F1/324, G06F1/3296, G09G5/36
CPC Code(s): G06F1/3234
Abstract: in one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. the power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. the voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. other embodiments are described and claimed.
Inventor(s): Anand K. ENAMANDRAM of Folsom CA (US) for intel corporation, Kerry VANDER KAMP of Hillsboro OR (US) for intel corporation, Mahesh S. NATU of Folsom CA (US) for intel corporation, Robert A. BRANCH of Portland OR (US) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: a cloud service provider reconfigures a memory subsystem during routine operation, while minimizing the amount of time a server is not online. server downtime is reduced by offloading reconfiguration of system memory to the operating system with platform assistance. the operating system enumerates potential memory configurations of the memory subsystem with associated performance characteristics in an abstracted manner and performs reconfiguration of the memory subsystem without a cold reset. when reconfiguration of the memory subsystem is deemed necessary by the operating system, the operating system examines the enumerated memory subsystem configurations provided by system firmware. after selecting the memory subsystem configuration, the operating system initiates a reconfiguration process. the reconfiguration process saves any existing memory context to an auxiliary device, requests system firmware to perform the memory subsystem reconfiguration, and restores the existing memory context from the auxiliary device after the memory subsystem reconfiguration has been completed.
Inventor(s): Christoph Dobraunig of St. Veit an der Glan (AT) for intel corporation, Santosh Ghosh of Hillsboro OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30196
Abstract: techniques are described for an instruction for a conditional rotate and xor operation in a single instruction and triple input bitwise logical operations in a single instruction in an instruction set of a computing system.
20240264871. STORAGE TRANSACTIONS WITH PREDICTABLE LATENCY_simplified_abstract_(intel corporation)
Inventor(s): Ziye YANG of Shanghai (CN) for intel corporation, James R. HARRIS of Chandler AZ (US) for intel corporation, Kiran PATIL of Portland OR (US) for intel corporation, Benjamin WALKER of Chandler AZ (US) for intel corporation, Sudheer MOGILAPPAGARI of Hillsboro OR (US) for intel corporation, Yadong LI of Portland OR (US) for intel corporation, Mark WUNDERLICH of Lake Oswego OR (US) for intel corporation, Anil VASUDEVAN of Portland OR (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/46, G06F9/54, G06F13/22, H04L67/1097, H04L69/16
CPC Code(s): G06F9/5027
Abstract: the disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. the disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.
20240265232. METHODS AND APPARATUS TO ACCELERATE CONVOLUTION_simplified_abstract_(intel corporation)
Inventor(s): Darren Crews of Portland OR (US) for intel corporation, Yong Jiang of Shanghai (CN) for intel corporation, Yuanyuan Li of Shanghai (CN) for intel corporation, Xu Qian of Shanghai (CN) for intel corporation, Peiqing Jiang of Shanghai (CN) for intel corporation, Haiyun Hong of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/04
CPC Code(s): G06N3/04
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed. an example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to detect a pattern of an upsampled input submatrix, generate a transformed input submatrix by selecting four elements of the upsampled input submatrix, select a transformed weight submatrix based on the pattern, and convolve the transformed input submatrix and the transformed weight submatrix.
Inventor(s): Saikat MANDAL of Sacramento CA (US) for intel corporation, Prasoonkumar SURTI of Folsom CA (US) for intel corporation, Sven WOOP of Voelklingen (DE) for intel corporation
IPC Code(s): G06T1/20, G06F7/02, G06F7/24, G06F7/505, G06F9/38, G06T15/00, G06T15/08, G06T17/10
CPC Code(s): G06T1/20
Abstract: apparatus and method for stable and short latency sorting. for example, one embodiment of a processor comprises: an input circuit to receive a set of n input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least n*(n−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the n*(n−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the n*(n−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate n unique result values; and sorting circuitry to index into the n unique result values to return the sorted order.
Inventor(s): Edward BURTON of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L25/00, H01L23/00
CPC Code(s): H01L25/00
Abstract: stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. the stacked semiconductor die architectures may be included in or used to form semiconductor packages. a stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.
Inventor(s): Dax M. CRUM of Beaverton OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Leonard GULER of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/08, H01L29/423, H01L29/51, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up approach, are described. for example, integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. the first vertical arrangement of nanowires has a greater number of nanowires than the second vertical arrangement of nanowires. the first vertical arrangement of nanowires has an uppermost nanowire co-planar with an uppermost nanowire of the second vertical arrangement of nanowires. the first vertical arrangement of nanowires has a bottommost nanowire below a bottommost nanowire of the second vertical arrangement of nanowires. a first gate stack is over the first vertical arrangement of nanowires. a second gate stack is over the second vertical arrangement of nanowires.
Inventor(s): Feras EID of Chandler AZ (US) for intel corporation, Sasha N. OSTER of Marion IA (US) for intel corporation, Telesphor KAMGAING of Chandler AZ (US) for intel corporation, Georgios C. DOGIAMIS of Chandler AZ (US) for intel corporation, Aleksandar ALEKSOV of Chandler AZ (US) for intel corporation
IPC Code(s): H01Q9/04, H01L21/56, H01L23/31, H01L23/367, H01L23/495, H01L23/552, H01L23/66, H01Q1/22, H01Q1/24, H01Q1/52, H01Q19/22
CPC Code(s): H01Q9/0414
Abstract: embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (rf) components and a second substrate that is coupled to the first substrate. the second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 ghz or higher. a mold material is disposed on the first and second substrates. the mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation
IPC Code(s): H04L9/08, H04L9/30
CPC Code(s): H04L9/0869
Abstract: key encapsulation implemented by random sample generator circuitry to generate a plurality of pseudorandom bitstreams; polynomial multiplier circuitry to multiply a plurality of polynomial coefficients; and a controller to power off the polynomial multiplier circuitry and power on the random sample generator circuitry to generate the plurality of pseudorandom bitstreams, and power off the random sample generator circuitry and power on the polynomial multiplier circuitry to multiple the plurality of polynomial coefficients.
Inventor(s): Stephen Palermo of Chandler AZ (US) for intel corporation, Bradley Chaddick of Portland OR (US) for intel corporation, Gage Eads of Austin TX (US) for intel corporation, Mrittika Ganguli of Tempe AZ (US) for intel corporation, Abhishek Khade of Chandler AZ (US) for intel corporation, Abhirupa Layek of Chandler AZ (US) for intel corporation, Sarita Maini of Tempe AZ (US) for intel corporation, Niall McDonnell of Limerick (IE) for intel corporation, Rahul Shah of Chandler AZ (US) for intel corporation, Shrikant Shah of Chandler AZ (US) for intel corporation, William Burroughs of Macungie PA (US) for intel corporation, David Sonnier of Austin TX (US) for intel corporation
IPC Code(s): H04L47/125, H04L47/62, H04L47/625, H04L47/6275
CPC Code(s): H04L47/125
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. an example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.
20240267340. TIME ORDERED SWITCHING_simplified_abstract_(intel corporation)
Inventor(s): Anil VASUDEVAN of Portland OR (US) for intel corporation, Roberto PENARANDA CEBRIAN of Santa Clara CA (US) for intel corporation, Md Ashiqur RAHMAN of Phoenix AZ (US) for intel corporation, Pedro YEBENES SEGURA of San Jose CA (US) for intel corporation, Allister ALEMANIA of North Plains OR (US) for intel corporation
IPC Code(s): H04L47/70
CPC Code(s): H04L47/826
Abstract: examples described herein relate to a network interface device that includes an interface to a port; and a circuitry. the circuitry can be configured to: receive a first packet that comprises a time stamp associated with a prior or originating transmission of the first packet by a transmitter network interface device; enqueue an entry for the first packet in a queue; and dequeue the entry based at least in part on the time stamp.
Inventor(s): Marcio Juliato of Portland OR (US) for intel corporation, Javier Perez-Ramirez of North Plains OR (US) for intel corporation, Manoj Sastry of Portland OR (US) for intel corporation, Dave Cavalcanti of Portland OR (US) for intel corporation, Christopher Gutierrez of Hillsboro OR (US) for intel corporation, Vuk Lesi of Cornelius OR (US) for intel corporation, Shabbir Ahmed of Beaverton OR (US) for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/1416
Abstract: techniques include a method, apparatus, system and computer-readable medium to detect, quantify and localize attacks to enhance security for time-synchronized networking. embodiments include a diagnostic stream producer to produce diagnostic information providing evidence of a timing attack on a node of a time-synchronized network. embodiments include a diagnostic stream consumer to consume diagnostic information, analyze the diagnostic information, and determine whether a node is under a timing attack. other embodiments are described and claimed.
Inventor(s): Jing ZHU of Portland OR (US) for intel corporation, Menglei ZHANG of Portland OR (US) for intel corporation, Shu-ping YEH of Campbell CA (US) for intel corporation
IPC Code(s): H04W28/08, H04W28/02
CPC Code(s): H04W28/0975
Abstract: the present disclosure is related to multi-access management services (mams), which is a programmable framework that provides mechanisms for the flexible selection of network paths in a multi-access (mx) communication environment, based on an application's needs. generic multi-access (gma) functions are also integrated into the mams framework. the present disclosure discusses dynamic traffic splitting and one-way delay measurement techniques. other implementations may be disclosed and/or claimed.
- Intel Corporation
- A63F13/355
- A63F13/335
- H04L67/568
- CPC A63F13/355
- Intel corporation
- G01R31/3185
- G01R31/317
- G06F21/72
- CPC G01R31/318588
- G02B6/43
- G02B6/12
- G02B6/122
- G02B6/42
- CPC G02B6/43
- G03F7/16
- C08G75/20
- G03F7/038
- G03F7/039
- CPC G03F7/168
- G06F1/3234
- G06F1/3237
- G06F1/324
- G06F1/3296
- G09G5/36
- CPC G06F1/3234
- G06F3/06
- CPC G06F3/0647
- G06F9/30
- CPC G06F9/30196
- G06F9/50
- G06F9/46
- G06F9/54
- G06F13/22
- H04L67/1097
- H04L69/16
- CPC G06F9/5027
- G06N3/04
- CPC G06N3/04
- G06T1/20
- G06F7/02
- G06F7/24
- G06F7/505
- G06F9/38
- G06T15/00
- G06T15/08
- G06T17/10
- CPC G06T1/20
- H01L25/00
- H01L23/00
- CPC H01L25/00
- H01L27/092
- H01L21/8238
- H01L29/06
- H01L29/08
- H01L29/423
- H01L29/51
- H01L29/66
- H01L29/78
- CPC H01L27/0924
- H01Q9/04
- H01L21/56
- H01L23/31
- H01L23/367
- H01L23/495
- H01L23/552
- H01L23/66
- H01Q1/22
- H01Q1/24
- H01Q1/52
- H01Q19/22
- CPC H01Q9/0414
- H04L9/08
- H04L9/30
- CPC H04L9/0869
- H04L47/125
- H04L47/62
- H04L47/625
- H04L47/6275
- CPC H04L47/125
- H04L47/70
- CPC H04L47/826
- H04L9/40
- CPC H04L63/1416
- H04W28/08
- H04W28/02
- CPC H04W28/0975
