Intel Corporation patent applications on August 29th, 2024
Patent Applications by Intel Corporation on August 29th, 2024
Intel Corporation: 39 patent applications
Intel Corporation has applied for patents in the areas of G06F9/50 (3), H01L21/768 (2), G06N3/08 (2), H01L27/092 (2), G06T7/246 (2) H01L27/0924 (2), G06T5/77 (2), G05B19/4155 (1), H04N19/395 (1), H01L29/0673 (1)
With keywords such as: data, memory, apparatus, circuitry, network, device, channel, based, image, and layer in patent application abstracts.
Patent Applications by Intel Corporation
20240288850. ADAPTIVE TUNING FOR MULTI-ASIC SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Long SHENG of Shanghai (CN) for intel corporation, Liang CHEN of Shanghai (CN) for intel corporation, Tao ZHOU of Oceanside CA (US) for intel corporation, Shuping HAN of Shanghai (CN) for intel corporation, Yan WANG of Shanghai (CN) for intel corporation, Chandra KATTA of Cupertino CA (US) for intel corporation, Vikram SURESH of Portland OR (US) for intel corporation, Chong HAN of Shanghai (CN) for intel corporation, He HAN of Shanghai (CN) for intel corporation, Tatt Hee OONG of Jelutong (MY) for intel corporation, Chee Hung CHIAN of Bayan Lepas (MY) for intel corporation, Yi HAN of Shanghai (CN) for intel corporation, Hao CHEN of Shanghai (CN) for intel corporation
IPC Code(s): G05B19/4155, H05K7/20
CPC Code(s): G05B19/4155
Abstract: various embodiments are directed to frequency and voltage tuning for systems with multiple application-specific integrated circuits (asics) and disclosed herein may be applied to multi-aic systems in a variety of applications, such as high-performance computing, artificial intelligence, graphics applications, and cryptocurrency or blockchain mining functions.
Inventor(s): Balaji Vembu of Folsom CA (US) for intel corporation, Josh B. Mastronarde of Sacramento CA (US) for intel corporation, Nikos Kaburlasos of Folsom CA (US) for intel corporation
IPC Code(s): G06F1/3287, G06F1/26, G06F1/3296, G06F9/50, G06F13/40
CPC Code(s): G06F1/3287
Abstract: in an example, an apparatus comprises logic, at least partially comprising hardware logic, to power on a first set of processing clusters, dispatch a workload to the first set of processing clusters, detect a full operating state of the first set of processing clusters, and in response to the detection of a full operating state of the first set of processing clusters, to power on a second set of processing clusters. other embodiments are also disclosed and claimed.
Inventor(s): Patrick Leung of Portland OR (US) for intel corporation, Jiancheng Tao of Shanghai (CN) for intel corporation, Trevor Love of Wilsonville OR (US) for intel corporation, Jianfang Zhu of Portland OR (US) for intel corporation, Kristoffer Fleming of Chandler AZ (US) for intel corporation, Jun Liu of Shanghai (CN) for intel corporation, Michael Mallen of Portland OR (US) for intel corporation, Duncan Glendinning of Chandler AZ (US) for intel corporation
IPC Code(s): G06F1/3296
CPC Code(s): G06F1/3296
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed that improve sleep state demotion with a hardware power monitor. an example apparatus includes memory, and processor circuitry to perform at least one of the operations to instantiate: detector circuitry to detect power output data of the computing device via a hardware power monitor, power analyzer circuitry to determine the power output data for sleep states of the computing device based on multiple wake intervals, identifier circuitry to identify crossover thresholds at ones of the multiple wake intervals, and controller circuitry to limit the computing device to the crossover thresholds at ones of the multiple wake intervals.
Inventor(s): Rajiv Mongia of Redwood City CA (US) for intel corporation, Achintya Bhowmik of Milpitas CA (US) for intel corporation, Mark Yahiro of Santa Clara CA (US) for intel corporation, Dana Krieger of Emeryville CA (US) for intel corporation, Ed Mangum of San Mateo CA (US) for intel corporation, Diana Povieng of San Francisco CA (US) for intel corporation
IPC Code(s): G06F3/01, G06F3/0481, G06F3/04812, G06F3/0487, G06F3/04895
CPC Code(s): G06F3/017
Abstract: a mechanism to provide visual feedback regarding computing system command gestures. an embodiment of an apparatus includes a sensing element to sense a presence or movement of a user of the apparatus, a processor, wherein operation of the processor includes interpretation of command gestures of a user to provide input to the apparatus; and a display screen, the apparatus to display one or more icons on the display screen, the one or more icons being related to the operation of the apparatus. the apparatus is to display visual feedback for a user of the apparatus, visual feedback including a representation of one or both hands of the user while the one or both hands are within a sensing area for the sensing element.
20240289033. ROUTING OF MEMORY TRANSACTIONS_simplified_abstract_(intel corporation)
Inventor(s): Kausik GHOSH of Bangalore (IN) for intel corporation, Pratim BOSE of Kolkata (IN) for intel corporation, Arun Venkatasubbaiah HODIGERE of Bangalore (IN) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: an apparatus for processing data is provided comprising persistent memory circuitry, non-persistent memory circuitry and memory controller circuitry. the memory controller circuitry provides two or more memory sub-channels and each memory sub-channel is for routing of memory access transactions for at least one of the persistent memory circuitry and the non-persistent memory circuitry. the memory controller circuitry has channel selection circuitry to detect when there are no non-persistent memory transactions on one of the two or more memory sub-channels and responsive to the detection, is to route any persistent memory transactions to a different one of the two or more memory sub-channels. a memory controller apparatus, a persistent memory dual in-line memory module, a method and computer program are also provided.
Inventor(s): Barry E. Huntley of Hillsboro OR (US) for intel corporation, Jr-Shian Tsai of Portland OR (US) for intel corporation, Gilbert Neiger of Hillsboro OR (US) for intel corporation, Rajesh M. Sankaran of Portland OR (US) for intel corporation, Mesut A. Ergin of Portland OR (US) for intel corporation, Ravi L. Sahita of Beaverton OR (US) for intel corporation, Andrew J. Herdrich of Hillsboro OR (US) for intel corporation, Wei Wang of Nanjing (CN) for intel corporation
IPC Code(s): G06F9/455, G06F9/30, G06F12/02, G06F12/10, G06F12/109, G11C7/10
CPC Code(s): G06F9/45558
Abstract: a processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. the execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.
Inventor(s): Krishnan Ananthanarayanan of Kerala (IN) for intel corporation, Martin Langhammer of Alderbury (GB) for intel corporation, Om Ji Omer of Bangalore (IN) for intel corporation, Bogdan Pasca of Toulouse (FR) for intel corporation, Kamlesh Pillai of Bangalore (IN) for intel corporation, Pramod Udupa of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: systems, apparatuses and methods may provide for technology that identifies a type of a first activation function, identifies a derivative level of the first activation function, and generates a first instruction based on the type of the first activation function and the derivative level of the first activation function. the technology also includes an accelerator having logic coupled to one or more substrates, the logic including a compute engine including a plurality of arithmetic operators, a multiplexer network coupled to the compute engine, and a controller coupled to the multiplexer network, the controller to detect the first instruction, decode the first instruction to identify the first activation function, and drive the multiplexer network to form first connections between two or more of the plurality of arithmetic operators in accordance with the first activation function, wherein the first connections are to cause the compute engine to conduct the first activation function.
20240289181. POWER CONSUMPTION-BASED RATE LIMITING_simplified_abstract_(intel corporation)
Inventor(s): Mateusz Polrola of Lodz (PL) for intel corporation, Maksim Lukoshkov of Clarecastle (IE) for intel corporation, Ciunas Low Bennett of Mallow (IE) for intel corporation
IPC Code(s): G06F9/50, G06F1/3206
CPC Code(s): G06F9/5083
Abstract: a hardware accelerator device is provided with accelerator hardware including a first component to be used in execution of a first job and first power monitoring circuitry to monitor power consumption at the first component associated with execution of the first job. the hardware accelerator further includes a usage controller to limit use of the accelerator hardware by the first job based at least in part on the measured power consumption at the first component associated with execution of the first job.
20240289202. BOOT ERROR REPORTING_simplified_abstract_(intel corporation)
Inventor(s): Divya GUPTA of Hillsboro OR (US) for intel corporation, Raed AL-OMARI of Round Rock TX (US) for intel corporation, Yi ZENG of Shanghai (CN) for intel corporation, Sheng HUANG of Folsom CA (US) for intel corporation
IPC Code(s): G06F11/07, G06F9/4401, G06F13/42
CPC Code(s): G06F11/0787
Abstract: examples described herein relate to a bootable processor that comprises circuitry to load boot firmware. the bootable processor can execute a firmware that is to collect an error log of an error during boot of the bootable processor and that occurred prior to enablement of an out of band (oob) manageability port. the firmware can cause output of the error log to a second circuitry through an interface that is operational prior to enablement of the oob manageability port.
Inventor(s): Qiuxu ZHUO of Shanghai (CN) for intel corporation, Karthik ANANTHANARAYANAN of Milpitas CA (US) for intel corporation, Hsing-Min CHEN of Santa Clara CA (US) for intel corporation, John HOLM of Beaverton OR (US) for intel corporation, Anthony LUCK of San Jose CA (US) for intel corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1048
Abstract: in one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (eccs) associated with the plurality of data blocks to a compacted ecc; and a second circuit to generate a generated ecc for the compacted data block. the apparatus may directly send the plurality of data blocks to a destination circuit without error detection on the plurality of data blocks based at least in part on the compacted ecc and the generated ecc. other embodiments are described and claimed.
Inventor(s): Syed Ahsan of Folsom CA (US) for intel corporation, Michael F. Cole of Folsom CA (US) for intel corporation, Rupali Kumari of Malden MA (US) for intel corporation, Yasmine Omri of Cambridge MA (US) for intel corporation
IPC Code(s): G06F11/22
CPC Code(s): G06F11/2221
Abstract: a computer-implemented system and method comprises injecting a hang of data transfer on at least one of a plurality of interfaces interconnecting simulated, emulated, or physical hardware subcomponents arranged to send or receive data transmitted between the subcomponents. the system and method also include determining activity status of data transfer at the interfaces. then the system and method generates a hang signature to be placed in a hang signature database. the hang signature indicates the activity status of the interfaces that occur when the hang is present and the identification of the hardware subcomponent with the hang.
20240289286. A Concept for Providing Access to Remote Memory_simplified_abstract_(intel corporation)
Inventor(s): Zhonghua SUN of Shanghai (CN) for intel corporation, Changcheng LIU of Shanghai City (CN) for intel corporation, Yi SUN of Shanghai (CN) for intel corporation, Cong ZHANG of Shanghai (CN) for intel corporation, Di ZHANG of Shanghai (CN) for intel corporation, Zhuangzhi LI of Shanghai (CN) for intel corporation
IPC Code(s): G06F13/16, G06F13/40
CPC Code(s): G06F13/1668
Abstract: examples relate to a concept for providing access to remote memory. a network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. the circuitry is configured to translate the memory transaction request to a cache transaction request. the circuitry is configured to provide the cache transaction request to the first host. the circuitry is configured to obtain a response to the cache transaction request from the first host. the circuitry is configured to provide information on the response to the cache transaction request to the second host.
Inventor(s): Sergej DEUTSCH of Hillsboro OR (US) for intel corporation, David M. DURHAM of Beaverton OR (US) for intel corporation, Karanvir GREWAL of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F21/53
CPC Code(s): G06F21/53
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. the machine-readable instructions comprise instructions to obtain a read request for reading data from an address in volatile memory. the machine-readable instructions further comprise instructions to determine whether the address in volatile memory is associated with a trusted domain. the machine-readable instructions further comprise instructions to set, if the address is associated with a trusted domain and the read request is obtained from outside the trusted domain, an identification tag for the trusted domain. the machine-readable instructions further comprise instructions to return, for the read request and subsequent read requests for one or more addresses associated with the trusted domain, poisoned data if the flag is set for the trusted domain.
Inventor(s): Xu QIAN of Shanghai (CN) for intel corporation, Darren CREWS of Portland OR (US) for intel corporation, Yuanyuan LI of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/0495
CPC Code(s): G06N3/0495
Abstract: provided herein are apparatus and methods for reinforcement learning based post-training sparsification. an apparatus includes: a memory; and processor circuitry coupled with the memory, wherein the processor circuitry is to: obtain a first correction parameter indicating a mean shift of a set of weights after sparsification of a model with respect to that before the sparsification of the model; obtain a second correction parameter indicating a variance shift of the set of weights after the sparsification of the model with respect to that before the sparsification of the model; and correct the set of weights at least partially based on the first correction parameter and the second correction parameter, and wherein the memory is to store the corrected set of weights. other embodiments may also be disclosed and claimed.
Inventor(s): Haihao SHEN of Shanghai (CN) for intel corporation, Hengyu MENG of Shanghai (CN) for intel corporation, Feng TIAN of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/08, G06N5/04
CPC Code(s): G06N3/08
Abstract: the application provides a hardware-aware cost model for optimizing inference of a deep neural network (dnn) comprising: a computation cost estimator configured to compute estimated computation cost based on input tensor, weight tensor and output tensor from the dnn; and a memory/cache cost estimator configured to perform memory/cache cost estimation strategy based on hardware specifications, wherein the hardware-aware cost model is used to perform performance simulation on target hardware to provide dynamic quantization knobs to quantization as required for converting a conventional precision inference model to an optimized inference model based on the result of the performance simulation.
Inventor(s): Yanying Sun of Shanghai (CN) for intel corporation, Jianhui Dai of Shanghai (CN) for intel corporation, Kin-Hang Cheung of San Jose CA (US) for intel corporation, Qingfeng Li of Hillsboro OR (US) for intel corporation, Hua Zhang of Shanghai (CN) for intel corporation, Yesheng Xu of Shanghai (CN) for intel corporation
IPC Code(s): G06T5/77, G06T5/20, G06T7/13, G06T7/50, G06T7/90
CPC Code(s): G06T5/77
Abstract: methods and apparatus to perform mask-based depth enhancement for multi-view systems are disclosed herein. an example apparatus to adjust an input depth image of an image frame including the input depth image and an input color image includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to identify a color patch and a depth patch for an image pixel in a border area of the image frame, output an adjusted depth map based on at least one of (i) a mismatch between values of the color patch and a center pixel color of the color patch or (ii) a mismatch between values of the depth patch and a center pixel depth of the depth patch, output an adjusted mask map associated with the input depth image based on a position of at least one camera used to capture the image, and perform iterative depth data gap filling based on the adjusted depth map and the adjusted mask map to obtain an adjusted depth image corresponding to the input depth image.
Inventor(s): Wenlong Yang of Shanghai (CN) for intel corporation, Tomer Rider of Naahryia (IL) for intel corporation, Xiaopei Zhang of Shanghai (CN) for intel corporation
IPC Code(s): G06T5/77, G05B13/02, G05D1/00, G06F18/214, G06F18/24, G06F18/2413, G06F18/25, G06N3/044, G06N3/045, G06N3/08, G06N3/084, G06N5/04, G06T7/00, G06V10/764, G06V10/80, G06V10/82, G06V10/98
CPC Code(s): G06T5/77
Abstract: a mechanism is described for facilitating deep learning-based real-time detection and correction of compromised sensors in autonomous machines according to one embodiment. an apparatus of embodiments, as described herein, includes detection and capturing logic to facilitate one or more sensors to capture one or more images of a scene, where an image of the one or more images is determined to be unclear, where the one or more sensors include one or more cameras. the apparatus further comprises classification and prediction logic to facilitate a deep learning model to identify, in real-time, a sensor associated with the image.
Inventor(s): Longwei Fang of Beijing (CN) for intel corporation, Yikai Fang of Beijing (CN) for intel corporation, Hongzhi Tao of Beijing (CN) for intel corporation, Qiang Li of Beijing (CN) for intel corporation, Hang Zheng of Beijing (CN) for intel corporation
IPC Code(s): G06T17/00, G06T7/246, G06T7/292, G06T7/73, G06T19/20
CPC Code(s): G06T17/00
Abstract: a method and system of multi-view image processing with accurate skeleton reconstruction uses joint confidence values.
Inventor(s): Hector Alfonso Cordourier Maruri of Guadalajara (MX) for intel corporation, Himanshu Bhalla of Bengaluru (IN) for intel corporation, Georg Stemmer of Munich (DE) for intel corporation, Sinem Aslan of Portland OR (US) for intel corporation, Julio Cesar Zamora of West Sacramento CA (US) for intel corporation, Jose Rodrigo Camacho Perez of Guadalajara (MX) for intel corporation, Paulo Lopez Meyer of Guadalajara (MX) for intel corporation, Alejandro Ibarra Von Borstel of Manchaca TX (US) for intel corporation, Jose Israel Torres Ortega of Zapopan (MX) for intel corporation, Juan Antonio Del Hoyo Ontiveros of Tlajomulco (MX) for intel corporation
IPC Code(s): G10L25/30, G06N3/0499, G10L15/06, G10L25/12
CPC Code(s): G10L25/30
Abstract: methods, apparatus, systems, and articles of manufacture for real-time voice type detection in audio data are disclosed. an example non-transitory computer-readable medium disclosed herein includes instructions, which when executed, cause one or more processors to at least identify a first vocal effort of a first audio segment of first audio data and a second vocal effort of a second audio segment of the first audio data, train a neural network including training data, the training data including the first vocal effort, the first audio segment, the second audio segment, and the second vocal effort, and deploy the neural network, the neural network to distinguish between the first vocal effort and the second vocal effort.
Inventor(s): Gowri Somanath of Santa Clara CA (US) for intel corporation, Oscar Nestares of San Jose CA (US) for intel corporation
IPC Code(s): G11B27/036, G06T3/18, G06T3/4007, G06T3/4046, G06T7/246
CPC Code(s): G11B27/036
Abstract: a mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. a method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. the method further includes synthesizing, by a neural network, the multiple images into a single image including a middle image of the multiple images and representing an intermediary view of the multiple views.
Inventor(s): Florian Gstrein of Portland OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Gurpreet Singh of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L23/522
CPC Code(s): H01L21/7681
Abstract: described herein are ic devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. the process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. the polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. a cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.
Inventor(s): Jiun Hann Sir of Gelugor (MY) for intel corporation, Poh Boon Khoo of Bayan Lepas (MY) for intel corporation
IPC Code(s): H01L23/367, H01L21/48, H01L23/373
CPC Code(s): H01L23/367
Abstract: a low-profile memory apparatus that is compatible with system thermal solutions. the apparatus includes a substrate layer with an upper surface and a lower surface, a portion of the substrate layer having a first arrangement of conductive contacts located on the lower surface. a memory package is inverted and attached to the first arrangement of conductive contacts. a heat spreader component comprising a cavity is included. the memory package and the portion of the substrate layer having the first arrangement of conductive contacts located in the cavity. a second arrangement of conductive contacts is located on the lower surface of the substrate layer, external to the heat spreader component, to attach the apparatus to another substrate or printed circuit board in a multi-die assembly.
Inventor(s): Jason Gamba of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Sanjay Tharmarajah of Queen Creek AZ (US) for intel corporation, Rajeev Ranjan of Chandler AZ (US) for intel corporation, Greg Aponte of Maricopa AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/768, H01L23/532
CPC Code(s): H01L23/5384
Abstract: an apparatus comprises a first layer comprising a first dielectric material, and first and second regions on a first side of the first layer. the first regions comprise a first surface in a first plane, and each of the second regions comprise a second surface in a second plane spaced away from the first plane by a first distance. sidewalls extend between the first surface and the second surfaces. the apparatus further comprises a plurality of conductive features, each conductive feature comprising a bottom surface on one of the second surfaces, and a barrier film comprising a second dielectric material that contacts the sidewalls.
Inventor(s): Guowei Xu of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Chiao-Ti Huang of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, David Towner of Portland OR (US) for intel corporation, Orb Acton of Portland OR (US) for intel corporation, Omair Saadat of Portland OR (US) for intel corporation, Feng Zhang of Hillsboro OR (US) for intel corporation, Dax M. Crum of Beaverton OR (US) for intel corporation, Yang Zhang of Rio Rancho NM (US) for intel corporation, Biswajeet Guha of Hillsboro OR (US) for intel corporation, Oleg Golonzka of Beaverton OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/778, H01L29/786
CPC Code(s): H01L27/0924
Abstract: a metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, ic structures, and devices are disclosed. an example ic structure fabricated using metal gate fabrication method described herein may include a first stack of n-type nanoribbons, a second stack of p-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an nwf material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a pwf material between adjacent nanoribbons of the second stack, where the second gate region includes the pwf material at sidewalls of the nanoribbons of the second stack and further includes the nwf material so that the pwf material is between the sidewalls of the nanoribbons of the second stack and the nwf material.
Inventor(s): Glenn A. GLASS of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/3065, H01L21/308, H01L21/8238, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. in some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. in some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. the trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. alternatively, or in addition, the trim may reduce the height of the fins. the techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (soc) applications.
Inventor(s): Chiao-Ti Huang of Portland OR (US) for intel corporation, Guowei Xu of Portland OR (US) for intel corporation, Tao Chu of Portland OR (US) for intel corporation, Robin Chao of Portland OR (US) for intel corporation, Jaladhi Mehta of Beaverton OR (US) for intel corporation, Brian Greene of Portland OR (US) for intel corporation, Chung-Hsun Lin of Portland OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/40, H01L29/423, H01L29/786
CPC Code(s): H01L29/0673
Abstract: fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. an example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.
Inventor(s): Xin ZHANG of Shanghai (CN) for intel corporation, Di LIU of Beijing (CN) for intel corporation
IPC Code(s): H04B7/0452, H04B7/06
CPC Code(s): H04B7/0452
Abstract: processing circuitry for a communication station configured to facilitate multi-user multiple-input multiple output (mu-mimo) service. the processing circuitry can perform a multi-user selection for data transmission on a shared radio resource from a plurality of user equipments (ues). the processing circuitry selects one or more of the plurality of candidate ues in time domain based on time-domain scheduling algorithm, obtain historical throughput data and input for each selected ue. the input includes a channel state indicator including a single-user channel quality indicator (su-cqi), a precoding matrix indicator (pmi), rank indicator, and a channel state matrix. a trained reinforcement learning agent (rl agent) using the obtained input infers a rating score for each of the plurality of ues. the processing circuitry schedules the one or more the ues for transmission respectively on the plurality of radio resources based on the plurality of score ratings and allocate the plurality of radio resources.
Inventor(s): Salvatore Talarico of Los Gatos CA (US) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Toufiqul Islam of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L1/08, H04W16/14, H04W72/23, H04W74/0808
CPC Code(s): H04L1/08
Abstract: an apparatus and system to enable urllc pusch repetitions in the unlicensed spectrum are described. the number of consecutive pusch repetitions indicated in the rrc parameter is reinterpreted as the number of transmission occasions over which the ue is able to attempt cca. an orphan symbol is used to provide a dmrs transmission or cyclic prefix of the pusch transmission causing the orphan symbol. whether a cg-uci is piggybacked in a pusch transmission, and whether dci-dfi is used, is dependent on whether cg-retransmissiontimer is configured.
20240291786. MANAGEMENT CONTROL MESSAGE ROUTING_simplified_abstract_(intel corporation)
Inventor(s): Janusz P. Jurski of Beaverton OR (US) for intel corporation, Mariusz Oriol of Gdynia (PL) for intel corporation, Filip Schmole of Portland OR (US) for intel corporation
IPC Code(s): H04L51/21, H04L45/02
CPC Code(s): H04L51/21
Abstract: a management control message is received to be routed from a first device to a second device in a system. the management control message is determined to include management control data. it is determined whether the second device supports such management control messages and it is determined whether to forward the management control message to the second device based on whether the second device supports management control messages. management control messages are routed to destination devices within the system over a bridge device associated with the management control messages.
Inventor(s): Yejun Guo of Shanghai (CN) for intel corporation
IPC Code(s): H04N19/30, H04N19/172, H04N19/42
CPC Code(s): H04N19/395
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed that distribute video data encoded with scalable video coding. a remote data source analyzes the graphics system of one or more client device(s), generates a full video frame data and a base-layer video frame, encodes an auxiliary-layer bitstream, and transmits the bitstream to the client device(s). the remote data source does not need to encode or transmit a base-layer bitstream. the client device(s) generates a base-layer frame data, decodes the auxiliary-layer bitstream into an auxiliary-layer frame data, and reconstructs a full video frame based on the second base-layer frame data and the auxiliary-layer frame data. the methods, apparatus, systems, and articles of manufacture disclosed herein save bandwidth by transmitting only the auxiliary-layer bitstream to one or more of the client device(s) without a base-layer bitstream. the client device(s) graphics system is utilized to generate its own base-layer frame data.
20240292095. REDUCED POWER CAMERA CONTROL SYSTEM_simplified_abstract_(intel corporation)
Inventor(s): Wei Hu of Shanghai 31 (CN) for intel corporation, Kaijia Zhu of Beijing 11 (CN) for intel corporation, Yu Xia of Beijing 11 (CN) for intel corporation, Fuwen Li of Beijing (CN) for intel corporation, Hongjiang Zheng of Bejing (CN) for intel corporation
IPC Code(s): H04N23/65, G06T1/00, G06T7/254
CPC Code(s): H04N23/651
Abstract: techniques are provided for a camera control system with reduced power consumption. a system implementing the techniques according to an embodiment includes a scene change tracker configured to quantify a level of change between current and previous image frames provided by the camera. the system also includes a general purpose processor to generate camera control parameters using a first processing algorithm, based on the current and previous image frames, if the level of change exceeds a threshold. the system further includes an image signal processor to generate the camera control parameters using a second processing algorithm, based on the current and previous image frames, if the level of change is less than or equal to the threshold. the image signal processor consumes less power than the general purpose processor and the second processing algorithm is less computationally complex than the first processing algorithm.
Inventor(s): Joey CHOU of Scottsdale AZ (US) for intel corporation, Yizhi YAO of Chandler AZ (US) for intel corporation
IPC Code(s): H04W24/08, H04L43/04, H04L43/065, H04W8/18
CPC Code(s): H04W24/08
Abstract: some embodiments are related to a fifth generation (5g) or sixth generation (6g) wireless communications system and network components to generate performance measurements for subscriber data and parameter provisioning in a unified data management system. some embodiments are related to a wireless communications system and network components to generate data volume performance measurement for network functions supporting edge computing. other embodiments are described and claimed.
Inventor(s): Thomas LUETZENKIRCHEN of Taufkirchen (DE) for intel corporation
IPC Code(s): H04W56/00, H04L43/0817, H04W76/25
CPC Code(s): H04W56/001
Abstract: the disclosure is directed to a wireless network including a method for a network node supporting time synchronization services in a wireless time sensitive communication (tsc) network, including initiating a network port management procedure for time synchronization services by exchanging information including port management information and user plane node management information with a centralized network configuration (cnc), the port management information related to one or more ports located in a device side time sensitive network (tsn) translator (ds-tt) in a user equipment and a network-side tns translator (nw-tt) in a network node, encoding information related to port management parameter values to be read, set and deleted by the ds-tt and the nw-tt, and transmitting a deletion operation of a plurality of port management parameter entries at the one or more ports in the ds-tt and the nw-tt.
20240292371. USER EQUIPMENT PAGING MONITORING_simplified_abstract_(intel corporation)
Inventor(s): Seau S. Lim of Swindon (GB) for intel corporation, Sudeep K. Palat of Cheltenham (GB) for intel corporation
IPC Code(s): H04W68/00
CPC Code(s): H04W68/005
Abstract: an apparatus and system of paging using paging early indication (pei) and subgrouping are described. a fifth generation nodeb (gnb) checks paging information of a ue from a limited paging container of the ue provided from the core network to determine whether pei/subgrouping information is present. the limited paging container contains paging information of the ue that is provided in the ue capability and is used by a previous gnb. if the paging information of the ue does not indicate the ability of the ue to use pei and/or subgrouping, the gnb checks the information in the ue capability; if the paging information and the ue capability conflict, the gnb signals the ue to monitor for pei/subgrouping. the gnb updates the paging capability with pei and/or subgrouping support before the ue enters idle mode or inactive state and sends the update to the core network.
Inventor(s): Alexey Khoryaev of Nizhny Novgorod (RU) for intel corporation, Mikhail Shilov of Nizhny Novgorod (RU) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Kilian Roth of München (DE) for intel corporation, Dmitry Belov of Nizhny Novgorod (RU) for intel corporation, Artyom Lomayev of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04W72/02, H04L5/00, H04W72/25, H04W72/563
CPC Code(s): H04W72/02
Abstract: an apparatus and system for new radio (nr) vehicle-to-everything (v2x) sidelink communications are described. a ue receives, from an assisting ue, inter-ue coordination feedback that contains a preferred resource set and a non-preferred resource set based on a reference configuration and uses preferred resources for the v2x sidelink communications. the preferred resources are dependent on the reference configuration and a resource selection configuration of the ue.
20240292409. CELL GROUPING FOR MULTI-CELL SCHEDULING_simplified_abstract_(intel corporation)
Inventor(s): Gang Xiong of Beaverton OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Viktor Sergeev of Lucan, Dublin (IE) for intel corporation
IPC Code(s): H04W72/1268, H04W72/232
CPC Code(s): H04W72/1268
Abstract: a computer-readable storage medium stores instructions to configure a ue for multi-cell scheduling in a 5g nr network, and to cause the ue to perform operations including decoding higher layer signaling. the higher layer signaling indicates a number of cell groups configured to the ue. each cell group of the number of cell groups includes at least two cells. dci received in a pdcch is decoded. the dci includes a scheduling grant with time and frequency allocation for a pusch or a pdsch in the number of cell groups configured to the ue. uplink data transmissions via the pusch are scheduled in the number of cell groups or downlink data receptions via the pdsch are scheduled in the number of cell groups based on the scheduling grant.
Inventor(s): Markus Dominik Mueck of Unterhaching (DE) for intel corporation, John Roman of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W74/0808, H04L5/00
CPC Code(s): H04W74/0808
Abstract: logic to protect intelligent transportation system (its) communications from interference by communications on neighboring channel by actions of an its device, by actions of a wireless communications device on a neighboring channel, or a combination thereof. logic to perform clear channel assessment (cca) on a neighbor channel, the neighbor channel outside an allocation for its channels; cause transmission of a physical layer protocol data unit (ppdu) comprising a network allocation vector (nav) in the neighbor channel, the ppdu to identify the neighbor channel as busy for a period of time to allocate for its communications; monitor an its channel for its communications to determine if the its channel is busy; and perform its communications within the period of time on the its channel after a determination that the its channel is not busy. and logic to monitor a neighbor channel and perform an operation to protect the neighbor channel.
Inventor(s): Juha Paavola of Hillsboro OR (US) for intel corporation, Justin M Huttula of Hillsboro OR (US) for intel corporation, Sami Heinisuo of Dallas OR (US) for intel corporation, Kari Mansukoski of Hillsboro OR (US) for intel corporation
IPC Code(s): H05K1/14, H05K3/36
CPC Code(s): H05K1/141
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device includes a standoff interposer between an overlapping portion of a first circuit board and a second circuit board. in selected examples, electronic devices and methods described show one or more conductive pathways within a standoff interposer that provide electrical communication between circuit boards, such as data signals, power delivery, etc.
Inventor(s): Pharveen Parameswaran of Penang (MY) for intel corporation, Santhosh Ap of Bangalore (IN) for intel corporation, Poh Ling Lee of Penang (MY) for intel corporation, Prasanna Pichumani of Bangalore (IN) for intel corporation, Vijith Halestoph R of Bangalore (IN) for intel corporation, Syed Bukhari Syed Shafi of Penang (MY) for intel corporation, Anas Zakaria of Penang (MY) for intel corporation
IPC Code(s): H05K7/14
CPC Code(s): H05K7/1405
Abstract: a surface-mounted retaining assembly is provided for retaining an electronic component. the electronic component may comprise an internal expansion card of an electronic device, and may comprise an m.2 module. the retaining assembly utilizes a spring-loaded retaining mechanism and may be bonded to a printed circuit board (pcb) via a small footprint solder pad. the retaining assembly eliminates the need for through-hole or surface-mounted standoffs, and thus increases the usable routing area on all layers. additionally, the retaining assembly does not require a threaded component, and is suitable for low profile applications for which threaded components are infeasible.
- Intel Corporation
- G05B19/4155
- H05K7/20
- CPC G05B19/4155
- Intel corporation
- G06F1/3287
- G06F1/26
- G06F1/3296
- G06F9/50
- G06F13/40
- CPC G06F1/3287
- CPC G06F1/3296
- G06F3/01
- G06F3/0481
- G06F3/04812
- G06F3/0487
- G06F3/04895
- CPC G06F3/017
- G06F3/06
- CPC G06F3/0625
- G06F9/455
- G06F9/30
- G06F12/02
- G06F12/10
- G06F12/109
- G11C7/10
- CPC G06F9/45558
- CPC G06F9/5027
- G06F1/3206
- CPC G06F9/5083
- G06F11/07
- G06F9/4401
- G06F13/42
- CPC G06F11/0787
- G06F11/10
- CPC G06F11/1048
- G06F11/22
- CPC G06F11/2221
- G06F13/16
- CPC G06F13/1668
- G06F21/53
- CPC G06F21/53
- G06N3/0495
- CPC G06N3/0495
- G06N3/08
- G06N5/04
- CPC G06N3/08
- G06T5/77
- G06T5/20
- G06T7/13
- G06T7/50
- G06T7/90
- CPC G06T5/77
- G05B13/02
- G05D1/00
- G06F18/214
- G06F18/24
- G06F18/2413
- G06F18/25
- G06N3/044
- G06N3/045
- G06N3/084
- G06T7/00
- G06V10/764
- G06V10/80
- G06V10/82
- G06V10/98
- G06T17/00
- G06T7/246
- G06T7/292
- G06T7/73
- G06T19/20
- CPC G06T17/00
- G10L25/30
- G06N3/0499
- G10L15/06
- G10L25/12
- CPC G10L25/30
- G11B27/036
- G06T3/18
- G06T3/4007
- G06T3/4046
- CPC G11B27/036
- H01L21/768
- H01L23/522
- CPC H01L21/7681
- H01L23/367
- H01L21/48
- H01L23/373
- CPC H01L23/367
- H01L23/538
- H01L23/532
- CPC H01L23/5384
- H01L27/092
- H01L21/8238
- H01L29/06
- H01L29/423
- H01L29/778
- H01L29/786
- CPC H01L27/0924
- H01L21/3065
- H01L21/308
- H01L29/66
- H01L29/78
- H01L21/8234
- H01L27/088
- H01L29/40
- CPC H01L29/0673
- H04B7/0452
- H04B7/06
- CPC H04B7/0452
- H04L1/08
- H04W16/14
- H04W72/23
- H04W74/0808
- CPC H04L1/08
- H04L51/21
- H04L45/02
- CPC H04L51/21
- H04N19/30
- H04N19/172
- H04N19/42
- CPC H04N19/395
- H04N23/65
- G06T1/00
- G06T7/254
- CPC H04N23/651
- H04W24/08
- H04L43/04
- H04L43/065
- H04W8/18
- CPC H04W24/08
- H04W56/00
- H04L43/0817
- H04W76/25
- CPC H04W56/001
- H04W68/00
- CPC H04W68/005
- H04W72/02
- H04L5/00
- H04W72/25
- H04W72/563
- CPC H04W72/02
- H04W72/1268
- H04W72/232
- CPC H04W72/1268
- CPC H04W74/0808
- H05K1/14
- H05K3/36
- CPC H05K1/141
- H05K7/14
- CPC H05K7/1405
