Intel Corporation patent applications on August 22nd, 2024
Patent Applications by Intel Corporation on August 22nd, 2024
Intel Corporation: 39 patent applications
Intel Corporation has applied for patents in the areas of G06T15/00 (4), G06T1/20 (3), G06F9/50 (3), G06F9/54 (3), G06T15/06 (3) G06T15/005 (2), H04N13/246 (1), H01L21/486 (1), H01L21/76831 (1), H01L21/76897 (1)
With keywords such as: circuitry, apparatus, device, memory, processor, data, based, processing, instructions, and interface in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, John C. Weast of Portland OR (US) for intel corporation, Mike B. Macpherson of Portland OR (US) for intel corporation, Dukhwan Kim of San Jose CA (US) for intel corporation, Linda L. Hurd of Cool CA (US) for intel corporation, Sanjeev Jahagirdar of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G05D1/00, G06F9/46, G06F9/48, G06F9/52, G06N3/044, G06N3/045, G06N3/063, G06N3/084, G06T1/20
CPC Code(s): G05D1/0088
Abstract: a mechanism is described for facilitating barriers and synchronization for machine learning at autonomous machines. a method of embodiments, as described herein, includes detecting thread groups relating to machine learning associated with one or more processing devices. the method may further include facilitating barrier synchronization of the thread groups across multiple dies such that each thread in a thread group is scheduled across a set of compute elements associated with the multiple dies, where each die represents a processing device of the one or more processing devices, the processing device including a graphics processor.
Inventor(s): Jiancheng Tao of Shanghai (CN) for intel corporation, Hong W. Wong of Portland OR (US) for intel corporation, Xiaoguo Liang of Shanghai (CN) for intel corporation, Yanbing Sun of Shanghai (CN) for intel corporation, Jun Liu of Shanghai (CN) for intel corporation, Wah Yiu Kwong of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F3/01, G06F3/03, G06F3/04845, G06F40/103, G06T3/40, G06V40/10, G06V40/16, G09G5/00, G09G5/14, G09G5/26
CPC Code(s): G06F3/012
Abstract: methods, apparatus, systems are disclosed for altering displayed content on a display device responsive to a user's proximity. in accord with an example, a computing system includes a display, a sensor to output a signal, machine readable instructions, and programmable circuitry to be programmed in accordance with the instructions to determine a distance between the compute system and a person based on the signal, and cause a size of at least one object to be presented on the display to be adjusted based on the distance.
20240281150. MEMORY READS BASED WITH A LIMITED RESPONSE TIME_simplified_abstract_(intel corporation)
Inventor(s): Yi ZENG of Shanghai (CN) for intel corporation, Kaushik BALASUBRAMANIAN of Beaverton OR (US) for intel corporation, Eti BAYEVSKY of Givat Ze’ev (IL) for intel corporation, Yuli BARCOHEN of Nokdim (IL) for intel corporation, Lukasz GOLAWSKI of Gdynia (PL) for intel corporation, Yaniv NISSIM of Jerusalem (IL) for intel corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: examples described herein relate to an interface to a serial connection and circuitry to: prior to issuance of a read request to a device, issue a command to the device to identify data to be requested to be read and based on an indicator that the identified data is available to be read, send the read request for the identified data via the interface to the device. the command can include an operational code, a starting address, and length.
Inventor(s): Satheesh CHELLAPPAN of Folsom CA (US) for intel corporation, Tomasz PIELASZKIEWICZ of Gdansk (PL) for intel corporation
IPC Code(s): G06F3/16
CPC Code(s): G06F3/162
Abstract: a device system-on-a-chip (soc) includes a streaming audio interface, a local memory, and a device controller coupled to the memory. the device controller is to decode an audio frame to generate a decoded audio frame. the audio frame is received via the streaming audio interface. the decoded audio frame is processed according to a streaming audio protocol to obtain corresponding control data and periodic streaming audio data. the control data is parsed to obtain a memory address pointer. memory access to the local memory is performed based on the memory address pointer.
20240281220. A Concept for Orchestration of Microservices_simplified_abstract_(intel corporation)
Inventor(s): Tat TAN of Bayan Lepas (MY) for intel corporation, Kamarul ABDUL RASHID of Bayan Lepas (MY) for intel corporation
IPC Code(s): G06F8/34, G06F8/10, G06F8/51, G06F8/60
CPC Code(s): G06F8/34
Abstract: an apparatus is provided. the apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. the machine-readable instruction may be stored on a storage device. the machine-readable instructions is to receive, from an interface apparatus, user data indicative of a hardware microservice requested by a user. further, it is to receive, from a database, microservice data indicative of a plurality of hardware microservices. further, it is to determine a hardware microservice based on the plurality of hardware microservices and the requested hardware microservice of the user.
20240281249. LOAD STORE CACHE MICROARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Sreedhar Chalasani of Folsom CA (US) for intel corporation, Eric Liskay of Folsom CA (US) for intel corporation, Prathamesh Raghunath Shinde of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Michael J. Norris of Folsom CA (US) for intel corporation, Rajasekhar Pantangi of Fremont CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/54
CPC Code(s): G06F9/30043
Abstract: one embodiment provides a graphics processor comprising memory access circuitry configured to receive a message from an instruction execution resource and determine a destination for the message, the destination one of shared function circuitry of a graphics core or a set of memory banks within the graphics core. the memory access circuitry then routes the message to the shared function circuitry in response to a determination that the message is directed to the shared function circuitry or routes the message to a message sequencer associated with the instruction execution resource in response to a determination that the message is directed to the set of memory banks.
Inventor(s): Mingqiu SUN of Beaverton OR (US) for intel corporation, Vincent ZIMMER of Issaquah WA (US) for intel corporation, Rajesh POORNACHANDRAN of Portland OR (US) for intel corporation, Gopinatth SELVARAJE of Portland OR (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/455, G06F21/57
CPC Code(s): G06F9/30181
Abstract: various examples relate to an apparatus, device, method, and computer program for extending instructions supported by a processor. the apparatus is configured to identify at least a part of a computer program targeting an instruction unsupported by a pre-defined set of instructions of an instruction set architecture (isa) of the processor. the apparatus is configured to extend the instructions supported by the processor, based on the targeted unsupported instruction. the apparatus is configured to execute the computer program.
20240281257. A Concept for Orchestration of Microservices_simplified_abstract_(intel corporation)
Inventor(s): Tat TAN of Bayan Lepas (MY) for intel corporation, Kamarul ABDUL RASHID of Bayan Lepas (MY) for intel corporation
IPC Code(s): G06F9/44, G06F11/30
CPC Code(s): G06F9/44
Abstract: various examples relate to apparatuses, devices, methods and computer programs for wrapping a monolithic application. in one aspect, such an apparatus is to observe a behavior of the monolithic application, and to provide a wrapper for wrapping the monolithic application, the wrapper comprising an interface that exposes one or more capabilities of the monolithic application to a microservice managing platform, with the interface being based on the observed behavior.
Inventor(s): Jeroen LEIJTEN of Hulsel (NL) for intel corporation
IPC Code(s): G06F9/50, G06F13/16
CPC Code(s): G06F9/5038
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to: control a processing circuitry of a computational system including a plurality of processing circuitries to determine if a number of input data token or tokens is available at one or more input buffers of a memory space; and control the processing circuitry to determine if at least a portion of the memory space for a number of output data token or tokens is available at one or more output buffers assigned to the processing circuitry; and control the processing circuitry to execute an iteration of a first task of an application, the application being modelled by a model, if it is determined that the number of input data token or tokens and memory space for the number of output data token or tokens are available.
Inventor(s): Reshma Lal of Portland OR (US) for intel corporation, Pradeep Pappachan of Tualatin OR (US) for intel corporation, Luis Kida of Beaverton OR (US) for intel corporation, Soham Jayesh Desai of Rochester MN (US) for intel corporation, Sujoy Sen of Beaverton OR (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation, Robert Sharp of Austin TX (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06T1/20, G06T1/60
CPC Code(s): G06F9/5083
Abstract: an apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. the apparatus includes one or more processors to: provide a remote gpu middleware layer to act as a proxy for an application stack on a client platform that is separate from the remote server platform, wherein the remote gpu middleware layer comprises is to expose an abstraction of the remote gpu to userspace components of a remote gpu stack, the userspace components running on the client machine; communicate with a kernel mode driver of the one or more processors to cause the host memory to be allocated for data structures used to communicate commands between the client and the remote gpu; and invoke the kernel mode driver to submit a workload generated by the application stack, the workload submitted for processing by the remote gpu using the data structures allocated in the host memory.
Inventor(s): Subham Sarda of Siliguri (IN) for intel corporation, Anil B Lingambudi of Bendaluru (IN) for intel corporation, Manickam Saravanan of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5094
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to techniques for workload balancing in a computing system with heterogeneous processing engines. a core assignment optimizer selects one or more of the heterogeneous processing engines based on static and heuristic profiling. static factors considered may include user preferences, system capabilities including maximum power consumption and thermals, the workload type and the unique power/performance profile of each heterogeneous processing engine and the like. dynamic or heuristic factors may include processing engine usage over time, current thermal characteristics of the system, current system workload including resource availability, and the like.
Inventor(s): Shijie Liu of Shanghai (CN) for intel corporation, Tao Xu of Shanghai (CN) for intel corporation, Lei Zhu of Shanghai (CN) for intel corporation, Kevin Yufu LI of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed that perform runtime recovery of processor links. an example non-transitory computer readable medium comprises instructions that, when executed, causes a machine to at least determine an onset of an error based on health of a central processor unit (cpu) port, calculate a figure of merit (fom) yield for each of a plurality of adaptation tasks performed on a lane of the cpu port using a first preset coefficient of a plurality of preset coefficients, select a preset coefficient based on the calculated fom, and trigger a link recovery mechanism, using the selected preset coefficient to initiate a link recovery process on the cpu port.
20240281375. TECHNOLOGIES TO EXPAND PIN COUNT_simplified_abstract_(intel corporation)
Inventor(s): Ramamurthy KRITHIVAS of Gilbert AZ (US) for intel corporation, Yi ZENG of Shanghai (CN) for intel corporation, Rahul SHAH of Marlborough MA (US) for intel corporation, Krzysztof WOJCIK of Czeczewo (PL) for intel corporation
IPC Code(s): G06F12/08
CPC Code(s): G06F12/08
Abstract: examples described herein relate to communications with a bootable processor. some examples include allocating memory address space to provide access to communications over general purpose input output (gpio)-consistent pins, wherein the gpio-consistent pins comprise pins coupled to the bootable processor and a pin of the pins coupled to the bootable processor receives or transmits communication for multiple platform gpio pins.
Inventor(s): Narayan RANGANATHAN of Bangalore (IN) for intel corporation, Vamsi SRIPATHI of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F12/0862, G06F12/0811
CPC Code(s): G06F12/0862
Abstract: examples relate to a non-transitory, computer-readable medium, method, and computer system for prefetching data during executing of a computer program. the non-transitory, computer-readable medium comprises machine-readable instructions that, when the program code is executed on a processor, causes the processor to pre-fetch to a processor cache, using data transfer offloading circuitry of the processor, data being accessed by an application program from a main memory of the computer system, and to execute the computer program using the pre-fetched data that is stored in the processor cache.
20240281403. I3C PENDING READ WITH RETRANSMISSION_simplified_abstract_(intel corporation)
Inventor(s): Janusz Jurski of Beaverton OR (US) for intel corporation, Enrico David Carrieri of Placerville CA (US) for intel corporation, Amit Kumar Srivastava of Folsom CA (US) for intel corporation, Matthew A. Schnoor of Hillsboro OR (US) for intel corporation, Myron Loewen of Berthoud CO (US) for intel corporation
IPC Code(s): G06F13/42, G06F9/54, G06F13/24, G06F13/362
CPC Code(s): G06F13/4291
Abstract: embodiments of the present disclosure may relate to apparatus, process, or techniques in a i3c protocol environment that include identifying a pending read notification message by a slave device to be sent to a master device to indicate that the data is available to be read by the master device from a buffer associated with the slave device. the pending read notification may be subsequently transmitted to the master device. subsequently, until the data in the buffer has been read by the master device, the slave device may wait an identified amount of time that is less than a value of a timeout of the master device, and retransmit the pending read notification message to the master device. other embodiments may be described and/or claimed.
Inventor(s): Guy Therien of Sherwood OR (US) for intel corporation
IPC Code(s): G06F15/78, G06F1/28
CPC Code(s): G06F15/7882
Abstract: in one embodiment, a processor includes: a plurality of cores to execute instructions and a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. the processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores, and is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. other embodiments are described and claimed.
Inventor(s): Jeroen LEIJTEN of Hulsel (NL) for intel corporation
IPC Code(s): G06F15/80, G06F9/54
CPC Code(s): G06F15/80
Abstract: it is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to generate a model modelling a computational system for distributed computation of tasks of an application. the model comprises one or more processor types. the computational system comprises a plurality of processing circuitries, physical memory and a respective memory address space, and one or more interconnects for communication between the plurality of processing circuitries and the physical memory. a processor type includes a processing circuitry identifier, a memory identifier, and an interface identifier. the machine readable instructions comprise to generate a first processor type which comprises: providing a first processing circuitry identifier for a first processing circuitry; providing a first memory identifier for a first address space region of the address space; providing a first interface identifier for an interface of the first processing circuitry.
Inventor(s): Guokai MA of Shanghai (CN) for intel corporation, Jiong GONG of Shanghai (CN) for intel corporation, Hongzhen LIU of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/098
CPC Code(s): G06N3/098
Abstract: provided herein are apparatus and methods for batch rebalance in distributed data parallel dnn training. an apparatus includes interface circuitry; and processor circuitry coupled with the interface circuitry, wherein the processor circuitry is to: obtain sorted samples of a mini batch via the interface circuitry, wherein the sorted samples are in an ascend or descend order based on a volume of each of the samples; and assign the sorted samples to each of a plurality of local batches one by one in an order from a first local batch to a last local batch of the plurality of local batches and then from the last local batch to the first local batch until all of the sorted samples are assigned. other embodiments may also be disclosed and claimed.
Inventor(s): Marissa du Bois of Portland OR (US) for intel corporation, Aria Kraft of Santa Clara CA (US) for intel corporation, Adam Lake of Portland OR (US) for intel corporation, Alexander Kharlamov of Santa Clara CA (US) for intel corporation, Anil Alston of Santa Clara CA (US) for intel corporation
IPC Code(s): G06T15/00, G06T15/80
CPC Code(s): G06T15/005
Abstract: methods, systems and apparatuses provide for technology that intercepts one or more commands to set a first shading rate for offscreen regions of a scene, wherein the scene is associated with a plurality of graphics processors and a plurality of displays, and sets, on a per-graphics processor basis and a per-display basis, a second shading rate for the offscreen regions of the scene, wherein the second shading rate is less than the first shading rate.
Inventor(s): Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Abhishek Appu of El Dorado Hills CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/00, G06T15/06
CPC Code(s): G06T15/005
Abstract: apparatus and method for stack throttling. for example, one embodiment of an apparatus comprises: execution circuitry comprising a plurality of functional units to execute a plurality of ray shaders and generate a plurality of primary rays and a corresponding plurality of ray messages; a first in first out (fifo) buffer to queue the ray messages generated by the eus; a cache to store one or more of the plurality of primary rays; a memory-backed stack to store a first subset of the plurality of ray messages in a corresponding plurality of entries; memory-backed stack management circuitry to either store a second subset of the plurality of ray messages to the memory-backed stack, or to temporarily store the one or more the second subset of the plurality of ray messages to a memory subsystem based, at least in part, on a number of entries currently occupied by ray messages in the memory-backed stack; and ray traversal circuitry to read a next ray message from the memory-backed stack, retrieve a next primary ray identified by the ray message from the cache or a memory subsystem, and perform traversal operations on the next primary ray.
Inventor(s): Sven Woop of Volklingen (DE) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Carsten Benthin of Voelklingen (DE) for intel corporation, Joshua Barczak of Forest Hills MD (US) for intel corporation, Saikat Mandal of Sacramento CA (US) for intel corporation
IPC Code(s): G06T15/06, G06T15/00
CPC Code(s): G06T15/06
Abstract: an apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. for example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
Inventor(s): Karthik VAIDYANATHAN of San Francisco CA (US) for intel corporation, Carsten BENTHIN of Voelklingen (DE) for intel corporation, Sven WOOP of Voelklingen (DE) for intel corporation
IPC Code(s): G06T17/10, G06F7/24, G06T1/20, G06T15/00, G06T15/06, G06T15/08, G06T17/20
CPC Code(s): G06T17/10
Abstract: apparatus and method for box-box testing. for example, one embodiment of a processor comprises: a bounding volume hierarchy (bvh) generator to construct a bvh comprising a plurality of hierarchically arranged bvh nodes; traversal circuitry to traverse query boxes through the bvh, the traversal circuitry to read a bvh node from a top of a bvh node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum x, y, and z coordinates of the bvh node and the query box and to generate an overlap indication if overlap is detected for each of the x, y, and z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the bvh node and the query box; and sorting circuitry and/or logic to sort the bvh node within a set of one or more additional bvh nodes based on the distance value.
20240282591. TOOLS AND METHODS FOR SURFACE LEVELING_simplified_abstract_(intel corporation)
Inventor(s): Oladeji FADAYOMI of Maricopa AZ (US) for intel corporation, Shaojiang CHEN of Chandler AZ (US) for intel corporation, Jeremy ECTON of Gilbert AZ (US) for intel corporation, Matthew TINGEY of Mesa AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Leonel ARANA of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L21/48, C23F1/02
CPC Code(s): H01L21/486
Abstract: the present disclosure is directed to a planarization tool having at least one module with a target holder for supporting a target with a metal layer, at least one of a plurality of etch inhibitor dispensers for discharging an etch inhibitor toward the target, and a plurality of nozzles for discharging a chemical etchant at an angle towards the target to perform selective removal of the metal layer for planarization of the target. in an aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be combined as a single unit to discharge the chemical etchant and the etch inhibitor together. in another aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be configured in a single module or separate modules.
Inventor(s): Sean KING of Beaverton OR (US) for intel corporation, Hui Jae YOO of Portland OR (US) for intel corporation, Sreenivas KOSARAJU of Portland OR (US) for intel corporation, Timothy GLASSMAN of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L21/02, H01L23/00, H01L23/522, H01L23/532
CPC Code(s): H01L21/76831
Abstract: conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3d topography. in embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ald) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a pecvd process for a thinner contiguous hermetic diffusion barrier. in further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. in other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
Inventor(s): Oleg GOLONZKA of Beaverton OR (US) for intel corporation, Swaminathan SIVAKUMAR of Beaverton OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L21/28, H01L21/306, H01L21/32, H01L21/8234, H01L23/535, H01L27/02, H01L27/088, H01L29/06, H01L29/66
CPC Code(s): H01L21/76897
Abstract: gate aligned contacts and methods of forming gate aligned contacts are described. for example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. the gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. a plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. a plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. the plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.
Inventor(s): Weston BERTRAND of Tempe AZ (US) for intel corporation, Kyle ARRINGTON of Gilbert AZ (US) for intel corporation, Shankar DEVASENATHIPATHY of Tempe AZ (US) for intel corporation, Aaron MCCANN of Queen Creek AZ (US) for intel corporation, Nicholas NEAL of Gilbert AZ (US) for intel corporation, Zhimin WAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/433, H01L23/367, H01L25/065
CPC Code(s): H01L23/433
Abstract: embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (tsvs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. in embodiments, the first die may be referred to as a base die. embodiments may include thermal blocks in the form of dummy dies that include tsvs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.
20240283197. SOCKETS HAVING FINE PITCH 3D FEATURES_simplified_abstract_(intel corporation)
Inventor(s): Saikat Mondal of Santa Clara CA (US) for intel corporation, Donald T. Tran of Phoenix AZ (US) for intel corporation, Zhichao Zhang of Chandler AZ (US) for intel corporation, Srikant Nekkanty of Chandler AZ (US) for intel corporation
IPC Code(s): H01R13/6474, H01R13/6461
CPC Code(s): H01R13/6474
Abstract: an apparatus and method for fine tuning impedance in a pin arrangement of a socket are described. the socket has a socket body that contains a plurality of coupling bridges. each coupling bridge contains: a surrounding portion that at least partially surrounds a via, and a stub portion extending from the ring-shaped portion. pins inserted in a plurality of vias are arranged in pin pairs configured to support double data rate (ddr) data signals. each first pin of at least some of the pin pairs electromagnetically coupled to a second pin of these pin pairs using one of the coupling bridges.
Inventor(s): Albert MOLINA of Novelda (ES) for intel corporation, Kameran AZADET of San Ramon CA (US) for intel corporation, Martin CLARA of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L25/03, H03M1/06, H03M1/12
CPC Code(s): H04L25/03127
Abstract: an apparatus for equalizing a digital input signal is provided. the apparatus includes an input node configured to receive the digital input signal. further, the apparatus includes a plurality of filters coupled in parallel to the input node. the plurality of filters are configured to filter the digital input signal and generate a respective filtered signal. additionally, the apparatus includes a combiner circuit coupled to the plurality of filters. the combiner circuit is configured to receive the respective filtered signal from the plurality of filters, and to generate an equalized signal by combining the received filtered signals according to a non-linear equalization function.
20240283756. RELIABLE TRANSPORT OFFLOADED TO NETWORK DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Shaopeng HE of Shanghai (CN) for intel corporation, Cunming LIANG of Shanghai (CN) for intel corporation, Jiang YU of Shanghai (CN) for intel corporation, Ziye YANG of Shanghai (CN) for intel corporation, Ping YU of Shanghai (CN) for intel corporation, Bo CUI of Shanghai (CN) for intel corporation, Jingjing WU of Shanghai (CN) for intel corporation, Liang MA of Shannon (IE) for intel corporation, Hongjun NI of Shanghai (CN) for intel corporation, Zhiguo WEN of Shanghai (CN) for intel corporation, Changpeng LIU of Shanghai (CN) for intel corporation, Anjali Singhai JAIN of Portland OR (US) for intel corporation, Daniel DALY of Santa Barbara CA (US) for intel corporation, Yadong LI of Portland OR (US) for intel corporation
IPC Code(s): H04L49/9057, H04L1/1829, H04L47/34, H04L47/56, H04L49/552, H04L49/90
CPC Code(s): H04L49/9057
Abstract: examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (acks), into one or more kernel space queues that are also accessible in user space.
Inventor(s): Aviad Zabatani of Even Yehuda (IL) for intel corporation, Sagy Bareket of Haifa (IL) for intel corporation, Ohad Menashe of Haifa (IL) for intel corporation, Erez Sperling of D.N. Menashe (IL) for intel corporation, Alex Bronstein of Haifa (IL) for intel corporation, Michael Bronstein of Lugano (CH) for intel corporation, Ron Kimmel of Haifa (IL) for intel corporation, Vitaly Surazhsky of Yokneam Illit (IL) for intel corporation
IPC Code(s): H04N13/246, G06F3/01, G06F3/0488, G06T5/80, G06T7/80, H04N13/00, H04N13/243, H04N13/25, H04N13/254
CPC Code(s): H04N13/246
Abstract: an example apparatus includes: a camera to record an image; memory to store instructions; and a processor in circuit with the memory, the processor to execute the instructions to: determine a depth based on: (a) the image and (b) a calibration parameter of the camera; and adjust the calibration parameter based on a temperature of the camera and the depth.
20240283927. ADAPTIVE IN-LOOP FILTERING IN VIDEO ENCODING_simplified_abstract_(intel corporation)
Inventor(s): Ximin Zhang of San Jose CA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation, Keith W. Rowe of Shingle Springs CA (US) for intel corporation
IPC Code(s): H04N19/117, H04N19/124, H04N19/132, H04N19/142, H04N19/147, H04N19/172, H04N19/463
CPC Code(s): H04N19/117
Abstract: in some compression techniques, in-loop filters can be included to effectively remove coding artifacts and improve the objective quality measurement at the same time. to avoid increasing complexity in the encoder, a single pass encoding solution can be implemented to efficiently and effectively make reasonably optimal in-loop filtering decisions. the solution can improve the in-loop filtering bit usage (e.g., reduce bitrate) and reduce the complexity in the encoder at the same time.
Inventor(s): Minzhi Sun of Bellevue WA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation, James Holland of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/189, H04N19/176, H04N19/186, H04N19/46
CPC Code(s): H04N19/189
Abstract: a lightweight but effective adaptive coding tool selection system with content classification can be implemented to reduce complexity and maintain quality in a video encoder. content classification may classify a current frame between at least three classifications: screen content, weak screen content, and natural content. content classification may make use of two statistics, e.g., color number and variance, of blocks that are 8�8 pixels or larger in size. the statistics may be used to calculate three frame-level statistics, e.g., proportion/percentage of blocks with few colors, proportion/percentage of blocks with zero variance, and proportion/percentage of blocks with big/large variance. the frame-level statistics are used to classify the current frame. based on the classification, coding tool control flags or control signals may be generated accordingly to configure the encoder to, e.g., turn on or off certain coding tools, and/or use certain parameter values for the coding tools.
Inventor(s): Rui Huang of Beijing, 11 (CN) for intel corporation, Meng Zhang of Beijing (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Hua Li of Arlington VA (US) for intel corporation, Ilya Bolotin of Nizhny-Novgorod (RU) for intel corporation
IPC Code(s): H04W64/00, H04B17/309, H04L5/00, H04W24/10
CPC Code(s): H04W64/00
Abstract: a computer-readable storage medium stores instructions to configure a ue for nr positioning in a 5g nr network, and to cause the ue to perform operations including decoding configuration signaling received from a location and management function (lmf) node of the 5gnr network. the configuration signaling includes a positioning reference signal (prs) measurement configuration. a number of measurement samples per a successful measurement reporting can be indicated by the prs measurement configuration which depends on a specific conditions (e.g., prs bandwidth, propagation channel, and sinr). a prs received from a base station is decoded. downlink prs (dl-prs) positioning measurements is performed based on the prs. the dl-prs positioning measurements are encoded for transmission to the lmf node using the number of measurement samples.
Inventor(s): Hao SONG of Santa Clara CA (US) for intel corporation, Yoav EISENBERG of Yehud-Monosson (IL) for intel corporation, Qinghua LI of San Ramon CA (US) for intel corporation, Ehud RESHEF of KIRYAT TIVON (IL) for intel corporation, Shlomi VITURI of Tel Aviv (IL) for intel corporation
IPC Code(s): H04W72/04, H04L1/00
CPC Code(s): H04W72/04
Abstract: this disclosure describes systems, methods, and devices related to unequal mcs indication. a device may extract resource unit (ru) or multi-ru (m-ru) allocation through one or more fields of a received frame from an associated access point (ap). a device may extract mcs information through mcs subfield of a user field of a user specific field in eht-sig. the device may extract spatial streams information through a spatial streams subfield of the user field of the user specific field in eht-sig. the device may determine one or more mcs indications based on the mcs information, ru or mru allocation, and spatial streams information, determine its mcs indication.
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Thomas J. KENNEY of Portland OR (US) for intel corporation
IPC Code(s): H04W72/1268
CPC Code(s): H04W72/1268
Abstract: this disclosure describes systems, methods, and devices related to trigger based duplicate. a device may generate a variant trigger frame comprising one or more fields to carry information associated with multiple station devices (stas). the device may include scheduling of a transmission of uplink (ul) trigger based (tb) physical layer (phy) convergence protocol data unit (ppdu) for the multiple stas. the device may cause to send the variant trigger frame to the multiple stas.
Inventor(s): Bishwarup Mondal of San Ramon CA (US) for intel corporation, Avik Sengupta of San Jose CA (US) for intel corporation, Alexei Davydov of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/23, H04W72/0453, H04W72/56
CPC Code(s): H04W72/23
Abstract: various embodiments herein are directed to set physical downlink shared channel (pdsch) default beam behavior for single transmission-reception point (trp), single downlink control information (dci) multi-trp and multi-dci multi-trp operation, as well as physical downlink control channel (pdcch) prioritization based on quasi-colocation (qcl) type-d for multi-panel reception and single panel reception.
20240284501. ENHANCED CHANNEL ACCESS FOR MULTI-LINK DEVICES_simplified_abstract_(intel corporation)
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation, Dmitry AKHMETOV of Hillsboro OR (US) for intel corporation, Dibakar DAS of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W74/00, H04W76/15
CPC Code(s): H04W74/002
Abstract: this disclosure describes systems, methods, and devices related to channel access for multi-link devices (mlds). a mld may identify a first backoff count associated with a first enhanced distributed channel access function (edcaf) for a first communication link used by the mld; identify a second backoff count associated with a second edcaf for a second communication link used by the mld, the first backoff count less than the second backoff count; determine a time period after that the first backoff count reaches zero and during which to refrain from transmitting using the first communication link, the time period based on the second backoff count; determine that the first communication link transitioned from an idle state to a busy state during the time period; and generate a third backoff count associated with the first edcaf based on the first communication link transitioning to the busy state during the time period.
Inventor(s): Alexey Khoryaev of Nizhny Novgorod (RU) for intel corporation, Mikhail Shilov of Nizhny Novgorod (RU) for intel corporation, Sergey Panteleev of Maynooth (IE) for intel corporation, Kilian Peter Anton Roth of München (DE) for intel corporation, Artyom Putilin of Kstovo (RU) for intel corporation
IPC Code(s): H04W74/0808, H04L1/1867
CPC Code(s): H04W74/0808
Abstract: an apparatus and system for new radio (nr) vehicle-to-everything (v2x) sidelink communications are described. feedback channel design for inter-user equipment (ue) feedback includes a single or multi-bit conflict indication that indicates a type of collision between sidelink communications. prioritization between hybrid automatic repeat request (harq) feedback transmission/reception and the inter-ue coordination feedback transmission/reception are described. in addition, control of the number of times the inter-ue coordination feedback is transmitted is provided.
Inventor(s): Peng ZHENG of Portland OR (US) for intel corporation, Varun MISHRA of Hillsboro OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L21/265, H01L21/306, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/10, H01L29/167, H01L29/36, H01L29/66
CPC Code(s): H10B10/12
Abstract: embodiments disclosed herein include transistor devices with depopulated channels. in an embodiment, the transistor device comprises a source region, a drain region, and a vertical stack of semiconductor channels between the source region and the drain region. in an embodiment, the vertical stack of semiconductor channels comprises first semiconductor channels, and a second semiconductor channel over the first semiconductor channels. in an embodiment, first concentrations of a dopant in the first semiconductor channels are less than a second concentration of the dopant in the second semiconductor channel.
- Intel Corporation
- G05D1/00
- G06F9/46
- G06F9/48
- G06F9/52
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/084
- G06T1/20
- CPC G05D1/0088
- Intel corporation
- G06F3/01
- G06F3/03
- G06F3/04845
- G06F40/103
- G06T3/40
- G06V40/10
- G06V40/16
- G09G5/00
- G09G5/14
- G09G5/26
- CPC G06F3/012
- G06F3/06
- CPC G06F3/0619
- G06F3/16
- CPC G06F3/162
- G06F8/34
- G06F8/10
- G06F8/51
- G06F8/60
- CPC G06F8/34
- G06F9/30
- G06F9/54
- CPC G06F9/30043
- G06F9/455
- G06F21/57
- CPC G06F9/30181
- G06F9/44
- G06F11/30
- CPC G06F9/44
- G06F9/50
- G06F13/16
- CPC G06F9/5038
- G06F9/38
- G06T1/60
- CPC G06F9/5083
- CPC G06F9/5094
- G06F11/07
- CPC G06F11/076
- G06F12/08
- CPC G06F12/08
- G06F12/0862
- G06F12/0811
- CPC G06F12/0862
- G06F13/42
- G06F13/24
- G06F13/362
- CPC G06F13/4291
- G06F15/78
- G06F1/28
- CPC G06F15/7882
- G06F15/80
- CPC G06F15/80
- G06N3/098
- CPC G06N3/098
- G06T15/00
- G06T15/80
- CPC G06T15/005
- G06T15/06
- CPC G06T15/06
- G06T17/10
- G06F7/24
- G06T15/08
- G06T17/20
- CPC G06T17/10
- H01L21/48
- C23F1/02
- CPC H01L21/486
- H01L21/768
- H01L21/02
- H01L23/00
- H01L23/522
- H01L23/532
- CPC H01L21/76831
- H01L21/28
- H01L21/306
- H01L21/32
- H01L21/8234
- H01L23/535
- H01L27/02
- H01L27/088
- H01L29/06
- H01L29/66
- CPC H01L21/76897
- H01L23/433
- H01L23/367
- H01L25/065
- CPC H01L23/433
- H01R13/6474
- H01R13/6461
- CPC H01R13/6474
- H04L25/03
- H03M1/06
- H03M1/12
- CPC H04L25/03127
- H04L49/9057
- H04L1/1829
- H04L47/34
- H04L47/56
- H04L49/552
- H04L49/90
- CPC H04L49/9057
- H04N13/246
- G06F3/0488
- G06T5/80
- G06T7/80
- H04N13/00
- H04N13/243
- H04N13/25
- H04N13/254
- CPC H04N13/246
- H04N19/117
- H04N19/124
- H04N19/132
- H04N19/142
- H04N19/147
- H04N19/172
- H04N19/463
- CPC H04N19/117
- H04N19/189
- H04N19/176
- H04N19/186
- H04N19/46
- CPC H04N19/189
- H04W64/00
- H04B17/309
- H04L5/00
- H04W24/10
- CPC H04W64/00
- H04W72/04
- H04L1/00
- CPC H04W72/04
- H04W72/1268
- CPC H04W72/1268
- H04W72/23
- H04W72/0453
- H04W72/56
- CPC H04W72/23
- H04W74/00
- H04W76/15
- CPC H04W74/002
- H04W74/0808
- H04L1/1867
- CPC H04W74/0808
- H10B10/00
- H01L21/265
- H01L21/8238
- H01L27/092
- H01L29/08
- H01L29/10
- H01L29/167
- H01L29/36
- CPC H10B10/12
