Intel Corporation patent applications on August 1st, 2024
Patent Applications by Intel Corporation on August 1st, 2024
Intel Corporation: 34 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (5), G06F17/16 (4), G06F9/38 (4), H01L23/00 (3), G06N3/045 (3) B23K26/082 (1), H01L23/5381 (1), H05K7/20236 (1), H05K1/181 (1), H04W72/231 (1)
With keywords such as: memory, apparatus, data, processing, information, based, substrate, circuitry, embodiments, and cores in patent application abstracts.
Patent Applications by Intel Corporation
20240253157. METHOD AND APPARATUS FOR MODIFYING A SUBSTRATE_simplified_abstract_(intel corporation)
Inventor(s): Richard Laming of Santa Clara CA (US) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): B23K26/082, B23K26/06, B23K26/0622, B23K26/70, B23K103/00
CPC Code(s): B23K26/082
Abstract: the present application relates to a method for modifying a substrate, which comprises generating a pulsed laser beam comprising a train of laser pulses, the train of laser pulses including at least three consecutive laser pulses, and controlling a direction of the pulsed laser beam and/or a position of the substrate from laser pulse to laser pulse so that the at least three consecutive laser pulses sequentially irradiate at least three regions of the substrate according to a predetermined spatial sequence which defines the relative spatial positions of the at least three regions of the substrate and the order of irradiation of the at least three regions of the substrate. the present application relates also to an apparatus () for modifying a substrate (). the method and apparatus () may be used, in particular though not exclusively, for forming an optical device.
Inventor(s): Naveen Mellempudi of Bangalore (IN) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Shuai Mu of San Diego CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Wei Xiong of Fremont CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38, G06F9/48, G06F17/16, G06N20/00
CPC Code(s): G06F9/30014
Abstract: an apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
Inventor(s): Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Menachem ADELMAN of Haifa (IL) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Milind B. GIRKAR of Sunnyvale CA (US) for intel corporation, Zeev SPERBER of Zichron Yackov (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Rinat RAPPOPORT of Haifa (IL) for intel corporation, Jesus CORBAL of King City OR (US) for intel corporation, Stanislav SHWARTSMAN of Haifa (IL) for intel corporation, Igor YANOVER of Yokneam Illit (IL) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation, Barukh ZIV of Haifa (IL) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Yuri GEBIL of Nahariya (IL) for intel corporation, Raanan SADE of Kibutz Sarid (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/485, G06F7/487, G06F7/76, G06F9/38, G06F17/16
CPC Code(s): G06F9/30036
Abstract: embodiments detailed herein relate to matrix operations. in particular, the loading of a matrix (tile) from memory. for example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.
20240256283. COMPUTING ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Joshua B. Fryman of Corvallis OR (US) for intel corporation, Byoungchan Oh of Portland OR (US) for intel corporation, Sai Dheeraj Polagani of Hillsboro OR (US) for intel corporation, Kevin P. Ma of Beaverton OR (US) for intel corporation, Robert S. Pawlowski of Beaverton OR (US) for intel corporation, Bharadwaj Coimbatore Krishnamurthy of Hillsboro OR (US) for intel corporation, Shruti Sharma of Hillsboro OR (US) for intel corporation, Smitha P. Vasantha Kumar of Hillsboro OR (US) for intel corporation, Jason Howard of Portland OR (US) for intel corporation, Daniel S. Klowden of Portland OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F11/34
CPC Code(s): G06F9/3851
Abstract: a system is provided that includes a set of graph processing cores and a set of dense compute cores. where the set of graph processing cores and the set of dense cores are interconnected in a network. the dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications. the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.
20240256456. DATA PREFETCHING FOR GRAPHICS DATA PROCESSING_simplified_abstract_(intel corporation)
Inventor(s): Vikranth Vemulapalli of FOLSOM CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Mike MacPherson of Portland OR (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Ben Ashbaugh of Folsom CA (US) for intel corporation, Murali Ramadoss of Folsom CA (US) for intel corporation, William B. Sadler of Folsom CA (US) for intel corporation, Jonathan Pearce of Portland OR (US) for intel corporation, Scott Janus of Loomis CA (US) for intel corporation, Brent Insko of Portland OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Kamal Sinha of Folsom CA (US) for intel corporation, Arthur Hunter, Jr. of Cameron Park CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Nicolas Galoppo von Borries of Portland OR (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, ElMoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Sungye Kim of Folsom CA (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation
IPC Code(s): G06F12/0862, G06T1/20, G06T1/60
CPC Code(s): G06F12/0862
Abstract: embodiments are generally directed to data prefetching for graphics data processing. an embodiment of an apparatus includes one or more processors including one or more graphics processing units (gpus); and a plurality of caches to provide storage for the one or more gpus, the plurality of caches including at least an l1 cache and an l3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first gpu of the one or more gpus including measuring a hit rate for the li cache; upon determining that the hit rate for the l1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the l3 cache, and upon determining that the hit rate for the l1 cache is less than a threshold value, allowing the prefetch of data to the l1 cache.
20240256483. GRAPHICS PROCESSOR DATA ACCESS AND SHARING_simplified_abstract_(intel corporation)
Inventor(s): Altug Koker of El Dorado Hills CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Niranjan Cooray of Folsom CA (US) for intel corporation, Nicolas Galoppo Von Borries of Portland OR (US) for intel corporation, Mike MacPherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, ElMoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, David Puffer of Tempe AZ (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ankur N. Shah of Folsom CA (US) for intel corporation, Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Saurabh Tangri of Folsom CA (US) for intel corporation
IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06T1/20, G06T1/60, H03M7/46, G06N3/08, G06T15/06
CPC Code(s): G06F15/7839
Abstract: embodiments are generally directed to graphics processor data access and sharing. an embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.
20240256685. REMOTE POOLED MEMORY DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Mark Schmisseur of Phoenix AZ (US) for intel corporation, Thomas Willhalm of Sandhausen (DE) for intel corporation
IPC Code(s): G06F21/60, G06F3/06, H04W12/50
CPC Code(s): G06F21/606
Abstract: an embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to process memory operation requests from a memory controller, and provide a front end interface to remote pooled memory hosted at a near edge device. an embodiment of another electronic apparatus may include local memory and logic communicatively coupled the local memory, the logic to allocate a range of the local memory as remote pooled memory, and provide a back end interface to the remote pooled memory for memory requests from a far edge device. other embodiments are disclosed and claimed.
Inventor(s): Liwei Ma of Beijing (CN) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Barath Lakshmanan of Chandler AZ (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Jingyi Jin of Folsom CA (US) for intel corporation, Jeremy Bottleson of Rancho Cordova CA (US) for intel corporation, Mike B. Macpherson of Portland OR (US) for intel corporation, Kevin Nealis of San Jose CA (US) for intel corporation, Dhawal Srivastava of Phoenix AZ (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ping T. Tang of Edison NJ (US) for intel corporation, Michael S. Strickland of Sunnyvale CA (US) for intel corporation, Xiaoming Chen of Shanghai (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Tatiana Shpeisman of Menlo Park CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06N3/04, G06N3/044, G06N3/045, G06N3/063, G06N3/082, G06T1/20
CPC Code(s): G06N3/04
Abstract: a library of machine learning primitives is provided to optimize a machine learning model to improve the efficiency of inference operations. in one embodiment a trained convolutional neural network (cnn) model is processed into a trained cnn model via pruning, convolution window optimization, and quantization.
Inventor(s): Xu QIAN of Shanghai (CN) for intel corporation, Haiyun HONG of Shanghai (CN) for intel corporation, Peiqing JIANG of Shanghai (CN) for intel corporation, Yuanyuan LI of Shanghai (CN) for intel corporation, Sijia LOU of Shanghai (CN) for intel corporation
IPC Code(s): G06N3/0464
CPC Code(s): G06N3/0464
Abstract: an apparatus, method, device, and medium for accelerating computation of a process engine are provided. the apparatus includes interface circuitry configured to receive weight data and activation data stored in a batch-height-width-channel (nhwc) memory layout; and processor circuitry configured to in response to that a input channel size is not an integer multiple of a process capacity of a process engine, pad a number of zeroes after a last element of weight data belonging to a filter and a last element of corresponding activation data respectively, slice all weight data elements belonging to the filter and padded zeroes into weight data slices, and corresponding activation data elements and padded zeroes into corresponding activation data slices, in a scale of the process capacity, and feed the process engine with each weight data slice and a corresponding activation data slice sequentially.
Inventor(s): Jiaxiang Jiang of Santa Clara CA (US) for intel corporation, Mahesh Subedar of Portland OR (US) for intel corporation
IPC Code(s): G06N3/047, G06N3/0464
CPC Code(s): G06N3/047
Abstract: methods, systems, articles of manufacture, apparatus and methods are disclosed to generate flow and audio multi-modal output. an example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit programmed by the machine-readable instructions to train an unsupervised image model to generate flow tensors based on a reference frame and a driver frame, the flow tensors representing at least one of rotation information or translation information. the example apparatus also includes at least one processor circuit programmed by the machine-readable instructions to train a denoising diffusion probabilistic model (ddpm) based on (a) the flow tensors, (b) audio distributions and (c) prompt signals, the trained ddpm to temporally align the flow tensors with the audio distributions.
Inventor(s): Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Deborah Marr of Portland OR (US) for intel corporation, Eugene Wang of Pittsburgh PA (US) for intel corporation, Saritha Dwarakapuram of Sunnyvale CA (US) for intel corporation, Sabareesh Ganapathy of Santa Clara CA (US) for intel corporation
IPC Code(s): G06N3/063, G06F7/52, G06F16/901, G06F17/16, G06F18/214, G06N3/04, G06N3/044, G06N3/045, G06N3/047, G06N3/08, G06N3/084, G06N20/00, G06T1/20, G06T15/00
CPC Code(s): G06N3/063
Abstract: an apparatus to facilitate processing of a sparse matrix for arbitrary graph data is disclosed. the apparatus includes a graphics processing unit having a data management unit (dmu) that includes a scheduler for scheduling matrix operations, an active logic for tracking active input operands, and a skip logic for tracking unimportant input operands to be skipped by the scheduler. processing circuitry is coupled to the dmu. the processing circuitry comprises a plurality of processing elements including logic to read operands and a multiplication unit to multiply two or more operands for the arbitrary graph data and customizable circuitry to provide custom functions.
Inventor(s): Shekar Ramachandran of Bengaluru (IN) for intel corporation, Rupali Agrahari of Sultanpur (IN) for intel corporation, Himanshu Singh of Bangalore (IN) for intel corporation, Rudra Nath Palit of Kolkata (IN) for intel corporation, Anmol Bhasin of Bengaluru (IN) for intel corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: an example apparatus disclosed includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of execute or instantiate the machine readable instructions to send a global model to one or more collaborator models, the one or more collaborator models training on a local dataset associated with a collaborator model, receive one or more collaborator models trained on the local dataset, compute a similarity measurement between the global model and at least one collaborator model, determine aggregation for the global model based on the computed similarity measurement, aggregate one or more one or more collaborator models based on the determined aggregation, and update the global model based on the aggregation.
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Narayan Srinivasa of Portland OR (US) for intel corporation, Feng Chen of Shanghai (CN) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation, Nicolas C. Galoppo Von Borries of Portland OR (US) for intel corporation, Eriko Nurvitadhi of Hillsboro OR (US) for intel corporation, Balaji Vembu of Folsom CA (US) for intel corporation, Tsung-Han Lin of Campbell CA (US) for intel corporation, Kamal Sinha of Rancho Cordova CA (US) for intel corporation, Rajkishore Barik of Santa Clara CA (US) for intel corporation, Sara S. Baghsorkhi of San Jose CA (US) for intel corporation, Justin E. Gottschlich of Santa Clara CA (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Nadathur Rajagopalan Satish of Santa Clara CA (US) for intel corporation, Farshad Akhbari of Chandler AZ (US) for intel corporation, Dukhwan Kim of San Jose CA (US) for intel corporation, Wenyin Fu of Folsom CA (US) for intel corporation, Travis T. Schluessler of Hillsboro OR (US) for intel corporation, Josh B. Mastronarde of Sacramento CA (US) for intel corporation, Linda L. Hurd of Cool CA (US) for intel corporation, John H. Feit of Folsom CA (US) for intel corporation, Jeffery S. Boles of Folsom CA (US) for intel corporation, Adam T. Lake of Portland OR (US) for intel corporation, Karthik Vaidyanathan of Berkeley CA (US) for intel corporation, Devan Burke of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F8/41, G06F9/455, G06F9/50, G06N3/044, G06N3/045, G06N3/063, G06N3/084
CPC Code(s): G06T1/20
Abstract: embodiments provide mechanisms to facilitate compute operations for deep neural networks. one embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. the plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. the first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
Inventor(s): Anbang Yao of Beijing 11 (CN) for intel corporation, Ming Lu of Beijing 11 (CN) for intel corporation, Yikai Wang of Beijing (CN) for intel corporation, Shandong Wang of Beijing 11 (CN) for intel corporation, Yurong Chen of Beijing 11 (CN) for intel corporation, Sungye Kim of Folsom CA (US) for intel corporation, Attila Tamas Afra of Satu Mare (RO) for intel corporation
IPC Code(s): G06T5/50, G06N3/02, G06T7/13, G06V40/16
CPC Code(s): G06T5/50
Abstract: the present disclosure provides an apparatus and method of guided neural network model for image processing. an apparatus may comprise a guidance map generator, a synthesis network and an accelerator. the guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. the synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. the accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.
Inventor(s): Xuesong Shi of Beijing (CN) for intel corporation, Sangeeta Manepalli of Chandler AZ (US) for intel corporation, Rita Chattopadhyay of Chandler AZ (US) for intel corporation, Peng Wang of Beijing (CN) for intel corporation, Yimin Zhang of Beijing (CN) for intel corporation
IPC Code(s): G06T7/579, G06T7/73
CPC Code(s): G06T7/579
Abstract: an apparatus to facilitate learning reliable keypoints in situ with introspective self-supervision is disclosed. the apparatus includes one or more processors to provide a view-overlapped keyframe pair from a pose graph that is generated by a visual simultaneous localization and mapping (vslam) process executed by the one or more processors: determine a keypoint match from the view-overlapped key frame pair based on a keypoint detection and matching process, the keypoint match corresponding to a keypoint: calculate an inverse reliability score based on matched pixels corresponding to the keypoint match in the view-overlapped keyframe pair: identify a supervision signal associated with the keypoint match, the supervision signal comprising a keypoint reliability score of the keypoint based on a final pose output of the vslam process; and train a keypoint detection neural network using the keypoint match, the inverse reliability score, and the keypoint reliability score.
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Karthik Vaidyanathan of San Francisco CA (US) for intel corporation, Saikat Mandal of Sacramento CA (US) for intel corporation, Michael Norris of Folsom CA (US) for intel corporation
IPC Code(s): G06T15/00, G06F3/06, G06T15/06
CPC Code(s): G06T15/005
Abstract: apparatus and method for asynchronous ray tracing. for example, one embodiment of a processor comprises: a bounding volume hierarchy (bvh) generator to construct a bvh comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the bvh; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the bvh by reading a next bvh node from a top of a bvh node stack and determining whether the next ray intersects the next bvh node.
Inventor(s): Zhiguo Wei of Shanghai (CN) for intel corporation, Yanyang Tan of Sherwood OR (US) for intel corporation, John Vancleve Lovelace of Driftwood TX (US) for intel corporation
IPC Code(s): G11C29/12, G11C29/30, G11C29/44
CPC Code(s): G11C29/1201
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to select addresses for memory training. an example non-transitory computer readable medium comprising instructions that, when executed, cause a machine to determine a first memory address at which to perform memory input/output training based on an identification of a second memory address that is associated with an error, and cause the memory input/output training to be performed at the first memory address.
Inventor(s): Edvin CETEGEN of Chandler AZ (US) for intel corporation, Jacob VEHONSKY of Gilbert AZ (US) for intel corporation, Nicholas S. HAEHN of Scottsdale AZ (US) for intel corporation, Thomas HEATON of Mesa AZ (US) for intel corporation, Steve S. CHO of Chandler AZ (US) for intel corporation, Rahul JAIN of Gilbert AZ (US) for intel corporation, Tarek IBRAHIM of Mesa AZ (US) for intel corporation, Antariksh Rao Pratap SINGH of Gilbert AZ (US) for intel corporation, Nicholas NEAL of Scottsdale AZ (US) for intel corporation, Sergio CHAN ARGUEDAS of Chandler AZ (US) for intel corporation, Vipul MEHTA of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/16, H01L23/00, H01L23/31, H01L23/498, H01L25/065
CPC Code(s): H01L23/16
Abstract: embodiments disclosed herein include electronic packages with underfill flow control features. in an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. in an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. in an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. in an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
Inventor(s): Robert Alan MAY of Chandler AZ (US) for intel corporation, Wei-Lun Kane JEN of Chandler AZ (US) for intel corporation, Jonathan L. ROSCH of Mesa AZ (US) for intel corporation, Islam A. SALAMA of Scottsdale AZ (US) for intel corporation, Kristof DARMAWIKARTA of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/683, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L23/5381
Abstract: a device and method for providing enhanced bridge structures is disclosed. a set of conducting and insulating layers are deposited and lithographically processed. the conducting layers have ufls routing. a bridge with ufls contacts and die disposed on the underlying structure such that the die are connected with the ufls contacts and ufls routing. for core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. for coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.
20240258296. MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Georgios Dogiamis of Chandler AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Zhiguo Qian of Chandler AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/00, H01L23/532, H01L23/538, H01L23/66
CPC Code(s): H01L25/18
Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a package substrate having a surface; a first die, having opposing first and second surfaces, in a first dielectric layer, wherein the first dielectric layer is between a second dielectric layer and the surface of the package substrate, and the first surface of the first die is coupled to the surface of the package substrate; a second die, having opposing first and second surfaces, in the second dielectric layer, and wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer; a third die, having opposing first and second surfaces, in the third dielectric layer, wherein the first surface of the third die is coupled to the surface of the package substrate by a conductive pillar; and a conductive, radio frequency shield structure surrounding the conductive pillar.
Inventor(s): Ryan KEECH of Portland OR (US) for intel corporation, Benjamin CHU-KUNG of Portland OR (US) for intel corporation, Subrina RAFIQUE of Hillsboro OR (US) for intel corporation, Devin MERRILL of McMinnville OR (US) for intel corporation, Ashish AGRAWAL of Hillsboro OR (US) for intel corporation, Harold KENNEL of Portland OR (US) for intel corporation, Yang CAO of Beaverton OR (US) for intel corporation, Dipanjan BASU of Hillsboro OR (US) for intel corporation, Jessica TORRES of Portland OR (US) for intel corporation, Anand MURTHY of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L29/08, H01L29/10, H01L29/165, H01L29/167, H01L29/45, H01L29/66
CPC Code(s): H01L29/7848
Abstract: integrated circuit structures having source or drain structures and germanium n-channels are described. in an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. a gate stack is over the upper fin portion of the fin. a first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. a second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. the first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.
Inventor(s): Guotong WANG of Santa Clara CA (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00, H04L27/26, H04W72/1268, H04W72/232
CPC Code(s): H04L5/0051
Abstract: systems, apparatuses, methods, and computer-readable media are directed to enhancements to sounding reference signal (srs) configurations for fifth-generation (5g) systems. in embodiments disclosed herein, an apparatus comprises: memory to store sounding reference signal (srs) configuration information for an uplink transmission with up to eight layers by a user equipment (ue); and processing circuitry, coupled with the memory, to: retrieve srs configuration information from the memory, wherein the srs configuration information includes a maximum number of cyclic shifts for a comb value, and wherein the maximum number of cyclic shifts is an integer multiple of eight; and encode a message for transmission to the ue that includes the srs configuration information.
Inventor(s): Santosh Ghosh of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/06
CPC Code(s): H04L9/0631
Abstract: techniques for implementing advanced encryption standard (aes)-256 encryption. an implementation includes a time-shared round data path with a depth-2 pipeline that results in an atomic execution of two 14-round aes-256 encryption operations in 30 cycles while operating at the same high-frequency clock used for processing cores of a computing system. the technology described herein uses only two cycles of latency per round while supporting a very high maximum operating clock speed.
Inventor(s): Fatemeh HAMIDI-SEPEHR of San Jose CA (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Yujian ZHANG of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L27/26, H04L1/1829
CPC Code(s): H04L27/265
Abstract: various embodiments herein are directed to efficient handling of user equipment (ue) processing capability and time dimensioning. for example, some embodiments are directed to transceiver processing task parallelization. an apparatus comprises memory to store a plurality of code blocks (cbs) within one orthogonal frequency division multiplexing (ofdm) symbol that are mapped into frequency resources of a plurality of fast fourier transform (fft) operations, and processing circuitry to retrieve the plurality of cbs from the memory, and process fft operations of the plurality of cbs in parallel independently of each other.
Inventor(s): Joey CHOU of Santa Clara CA (US) for intel corporation, Yizhi YAO of Chandler AZ (US) for intel corporation
IPC Code(s): H04L41/40, H04L41/0895, H04L67/52, H04W84/04
CPC Code(s): H04L41/40
Abstract: various embodiments herein may relate to edge computing network deployments, and in particular, some embodiments may be directed to instantiating edge application server (eas) virtual network functions (vnfs). an edge computing service provider (ecsp) management system is to: receive a request for instantiation of a virtual network function (vnf) that includes deployment requirements comprising software image information associated with the instantiation of the vnf; and instantiate the vnf based on the deployment requirements.
Inventor(s): Qian Xu of Folsom CA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation
IPC Code(s): H04N19/147, H04N19/105, H04N19/137, H04N19/176
CPC Code(s): H04N19/147
Abstract: different approaches for reducing complexity and computations in inter-prediction encoding are described. the approaches may involve one or more of quantization parameter and motion information being used to make a precision decision at a picture level that can improve compression efficiency. the approaches may involve finding prediction costs for the motion vector difference candidates and then performing rate-distortion optimization using the selected motion vector difference candidate having the lowest prediction cost. prediction costs may be determined using sums of absolute transformed differences, which can be calculated efficiently in hardware. the rate-distortion cost of using merge mode with motion vector difference with the selected motion vector difference candidate may be compared against one or more other rate-distortion costs. in addition, in some scenarios, the approaches may involve finding prediction costs for a subset of the motion vector difference candidates to further reduce computations.
Inventor(s): Jing ZHU of Portland OR (US) for intel corporation, Ching-Yu LIAO of Portland OR (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Dario SABELLA of Munich (DE) for intel corporation, Miltiadis FILIPPOU of Muenchen (DE) for intel corporation
IPC Code(s): H04W28/02, H04W76/11
CPC Code(s): H04W28/0252
Abstract: disclosed embodiments are related to techniques for implementing multiple access management services (mams), multi-access edge computing (mec), and 3gpp fifth generation (5g) technologies. embodiments include enhanced application programming interfaces (apis) that allow applications to influence multi-access (ma) traffic steering decisions, and also get informed of various ma traffic steering modes. disclosed embodiments also include techniques to enable coexistence between mec-based mams systems and 5g ma traffic steering mechanisms. other embodiments may be described and/or claimed.
Inventor(s): Sunku RANGANATH of Beaverton OR (US) for intel corporation, Hassnaa MOUSTAFA of San Jose CA (US) for intel corporation, Hosein NIKOPOUR of San Jose CA (US) for intel corporation, John BROWNE of Limerick (IE) for intel corporation, Stephen T. PALERMO of Chandler AZ (US) for intel corporation, Valerie J. PARKER of Portland OR (US) for intel corporation
IPC Code(s): H04W28/18, H04W24/10, H04W28/24
CPC Code(s): H04W28/18
Abstract: the present disclosure is related to edge and cloud computing frameworks, telemetry and telemetering systems, telemetry awareness and intelligence in managing telemetering systems, and radio access network (ran) and ran intelligent controller (ric) implementations. in particular, the present disclosure provides ric-based resource management for individual ric applications, which is based on the collection and analysis of platform telemetry data as well as measurements collected by user equipment and access network infrastructure elements.
Inventor(s): Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation
IPC Code(s): H04W72/0446, H04L5/00, H04W72/231, H04W72/232
CPC Code(s): H04W72/0446
Abstract: a user equipment (ue) configured for multi-slot physical downlink control channel (pdcch) monitoring may decode higher-layer signalling comprising configuration information received from a gnodeb (gnb) that configure the ue with search space (ss) sets for multi-slot pdcch monitoring. at least some slots of the ss sets may be indicated to have a pdcch monitoring occasion (mo). a ss set may be configured in a number (y) of consecutive non-overlapping slots (mo slots) within slot groups of a number (x) of consecutive non-overlapping slots. the number (x) of consecutive slots of the slot group may be at least twice the number (y) of consecutive mo slots within each ss set. the number (x) of consecutive slots of the slot group and the number (y) of consecutive mo slots within each ss set that comprise the pdcch mo may also be based on a subcarrier spacing (scs).
Inventor(s): Dong Han of Sunnyvale CA (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation, Avik Sengupta of San Jose CA (US) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation
IPC Code(s): H04W72/1268, H04L1/08, H04L5/00, H04W72/21
CPC Code(s): H04W72/1268
Abstract: a user equipment (ue configured for multi-transmission-reception point (m-trp) operation in a fifth-generation (5g) new radio (nr) network with dci activated pucch repetition with tx beam cycling may multiplex uci on a scheduled pusch transmission to a first trp, multiplex the uci on a scheduled pusch transmission to a second trp and drop repetitions of the pucch when a first repetition of the pucch overlaps the scheduled pusch transmission to the first trp and the second repetition of the pucch overlaps with a scheduled pusch transmission to the second trp. for multiplexing the uci and dropping the pucch repetitions, a timeline condition may also need to be satisfied.
20240260052. NON-TERRESTRIAL USER EQUIPMENT MEASUREMENTS_simplified_abstract_(intel corporation)
Inventor(s): Meng Zhang of Beijing (CN) for intel corporation, Andrey Chervyakov of Nizhny Novgorod (RU) for intel corporation, Rui Huang of Beijing, 11 (CN) for intel corporation, Hua LI of Arlington VA (US) for intel corporation, IIya Bolotin of Nizhny-Novgorod (RU) for intel corporation
IPC Code(s): H04W72/231, H04W56/00, H04W72/51, H04W84/06
CPC Code(s): H04W72/231
Abstract: an apparatus and system of enabling reference signal measurements in a non-terrestrial network (ntn) system are described. the ue provides capability information that indicates a maximum number of synchronization signal block (ssb)-based measurement timing configurations (smtcs) simultaneously supported by the ue for measurement of reference signals from cells in the ntn system and receives smtcs based on the capability information and a real time estimate of timing differences among the cells. the ue sends/receives data based on the smtcs and whether the ue supports simultaneous data communication and measurement. broadcast system information contains a flag that indicates which of dynamic and semi-static configuration is used, the maximum smtc's dependent on the flag value. radio resource control (rrc) signalling is used to send sets of smtcs that have different offsets. different sets are activated using dynamic signaling according to real time estimates of the timing differences.
20240260193. DECOUPLING CAPACITOR BOOSTER MODULE_simplified_abstract_(intel corporation)
Inventor(s): Herh Nan Chen of Georgetown (MY) for intel corporation, Kean Huat Leong of Georgetown (MY) for intel corporation, Sze Lin Mak of Pulau Pinang (MY) for intel corporation, Muhammad Danial Asyraf Abd Rahman of Kedah (MY) for intel corporation
IPC Code(s): H05K1/18, H05K1/11, H05K1/14, H05K3/34
CPC Code(s): H05K1/181
Abstract: microelectronic devices and systems include a decoupling capacitor module having any number of capacitors attached to a surface of a substrate such as a cored or coreless microelectronics board. the decoupling capacitor module is attached, by an opposing surface of the substrate, to a number of capacitors that are, in turn, mounted on a board such as a motherboard. substrate mounted capacitors are vertically aligned with corresponding board mounted capacitors to provide vertically stacked capacitors.
Inventor(s): Jimmy Chuang of Taipei (TW) for intel corporation, Jin Yang of Hillsboro OR (US) for intel corporation, Yuan-Liang Li of Taipei (TW) for intel corporation, David Shia of Portland OR (US) for intel corporation, Yuehong Fan of Shanghai (CN) for intel corporation, Hao Zhou of Shanghai (CN) for intel corporation, Sandeep Ahuja of Portland OR (US) for intel corporation, Peng Wei of Shanghai (CN) for intel corporation, Ming Zhang of Shanghai (CN) for intel corporation, Je-Young Chang of Tempe AZ (US) for intel corporation, Paul J. Gwin of Orangevale CA (US) for intel corporation, Ra'anan Sover of Tirat Carmel (IL) for intel corporation, Lianchang Du of Kunshan (CN) for intel corporation, Eric D. McAfee of Portland OR (US) for intel corporation, Timothy Glen Hanna of Tigard OR (US) for intel corporation, Liguang Du of Shanghai (CN) for intel corporation, Qing Jiang of Shanghai (CN) for intel corporation, Xicai Jing of Shanghai (CN) for intel corporation, Liu Yu of Shanghai (CN) for intel corporation, Guoliang Ying of Shanghai (CN) for intel corporation, Cong Zhou of Shanghai (CN) for intel corporation, Yinglei Ren of Shanghai (CN) for intel corporation, Xinfeng Wang of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20236
Abstract: immersion cooling systems, apparatus, and related methods for cooling electronic computing platforms and/or associated electronic components are disclosed herein. an example apparatus includes a first chamber including a first coolant disposed therein, the first coolant having a first boiling point. the example apparatus further includes a second chamber disposed in the first chamber, the second chamber to receive an electronic component therein. the second chamber includes a second coolant having a second boiling point different that the first boiling point. the second chamber is to separate the electronic component and the second coolant from the first coolant.
20240260233. DIMM COOLING ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Ming Zhang of Shanghai (CN) for intel corporation, Yuehong Fan of Shanghai (CN) for intel corporation, Peng Wei of Shanghai (CN) for intel corporation, Chuanlou Wang of Shanghai (CN) for intel corporation, Rajiv K. Mongia of Portland OR (US) for intel corporation, Guocheng Zhang of Shanghai (CN) for intel corporation, Yingqiong Bu of Shanghai (CN) for intel corporation, Berhanu Wondimu of Beaverton OR (US) for intel corporation, Guixiang Tan of Portland OR (US) for intel corporation, Xiang Que of Suzhou (CN) for intel corporation, Qing Jiang of Shanghai (CN) for intel corporation, Liu Yu of Shanghai (CN) for intel corporation, Wei-Ming Chu of New Taipei City (TW) for intel corporation, Chen Zhang of Shanghai (CN) for intel corporation, Hao Zhou of Shanghai (CN) for intel corporation, Feng Qi of Shanghai (CN) for intel corporation, Catharina Biber of Bend OR (US) for intel corporation, Devdatta Prakash Kulkarni of Portland OR (US) for intel corporation, Xiang Li of Portland OR (US) for intel corporation, Yechi Zhang of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/20, G06F1/20, H01L23/40, H01L23/427, H01L23/473
CPC Code(s): H05K7/20336
Abstract: heat pipes and vapor chambers that are components of a dimm cooling assembly are described.
- Intel Corporation
- B23K26/082
- B23K26/06
- B23K26/0622
- B23K26/70
- B23K103/00
- CPC B23K26/082
- Intel corporation
- G06F9/30
- G06F9/38
- G06F9/48
- G06F17/16
- G06N20/00
- CPC G06F9/30014
- G06F7/485
- G06F7/487
- G06F7/76
- CPC G06F9/30036
- G06F11/34
- CPC G06F9/3851
- G06F12/0862
- G06T1/20
- G06T1/60
- CPC G06F12/0862
- G06F15/78
- G06F7/544
- G06F7/575
- G06F7/58
- G06F9/50
- G06F12/02
- G06F12/06
- G06F12/0802
- G06F12/0804
- G06F12/0811
- G06F12/0866
- G06F12/0871
- G06F12/0875
- G06F12/0882
- G06F12/0888
- G06F12/0891
- G06F12/0893
- G06F12/0895
- G06F12/0897
- G06F12/1009
- G06F12/128
- G06F15/80
- G06F17/18
- H03M7/46
- G06N3/08
- G06T15/06
- CPC G06F15/7839
- G06F21/60
- G06F3/06
- H04W12/50
- CPC G06F21/606
- G06N3/04
- G06N3/044
- G06N3/045
- G06N3/063
- G06N3/082
- CPC G06N3/04
- G06N3/0464
- CPC G06N3/0464
- G06N3/047
- CPC G06N3/047
- G06F7/52
- G06F16/901
- G06F18/214
- G06N3/084
- G06T15/00
- CPC G06N3/063
- CPC G06N20/00
- G06F8/41
- G06F9/455
- CPC G06T1/20
- G06T5/50
- G06N3/02
- G06T7/13
- G06V40/16
- CPC G06T5/50
- G06T7/579
- G06T7/73
- CPC G06T7/579
- CPC G06T15/005
- G11C29/12
- G11C29/30
- G11C29/44
- CPC G11C29/1201
- H01L23/16
- H01L23/00
- H01L23/31
- H01L23/498
- H01L25/065
- CPC H01L23/16
- H01L23/538
- H01L21/48
- H01L21/683
- H01L25/00
- CPC H01L23/5381
- H01L25/18
- H01L23/532
- H01L23/66
- CPC H01L25/18
- H01L29/78
- H01L21/02
- H01L29/08
- H01L29/10
- H01L29/165
- H01L29/167
- H01L29/45
- H01L29/66
- CPC H01L29/7848
- H04L5/00
- H04L27/26
- H04W72/1268
- H04W72/232
- CPC H04L5/0051
- H04L9/06
- CPC H04L9/0631
- H04L1/1829
- CPC H04L27/265
- H04L41/40
- H04L41/0895
- H04L67/52
- H04W84/04
- CPC H04L41/40
- H04N19/147
- H04N19/105
- H04N19/137
- H04N19/176
- CPC H04N19/147
- H04W28/02
- H04W76/11
- CPC H04W28/0252
- H04W28/18
- H04W24/10
- H04W28/24
- CPC H04W28/18
- H04W72/0446
- H04W72/231
- CPC H04W72/0446
- H04L1/08
- H04W72/21
- CPC H04W72/1268
- H04W56/00
- H04W72/51
- H04W84/06
- CPC H04W72/231
- H05K1/18
- H05K1/11
- H05K1/14
- H05K3/34
- CPC H05K1/181
- H05K7/20
- CPC H05K7/20236
- G06F1/20
- H01L23/40
- H01L23/427
- H01L23/473
- CPC H05K7/20336
