Intel Corporation patent applications on August 15th, 2024
Patent Applications by Intel Corporation on August 15th, 2024
Intel Corporation: 32 patent applications
Intel Corporation has applied for patents in the areas of H01L23/00 (3), G06F1/3206 (2), H04L9/40 (2), H01L29/66 (2), G06F9/48 (2) C08K3/041 (1), G06V10/7715 (1), H05K7/20272 (1), H04W28/10 (1), H04W28/0268 (1)
With keywords such as: based, device, optical, apparatus, circuit, network, data, region, interface, and portion in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Clay Arrington of Queen Creek AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Jose Waimin of Gilbert AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation
IPC Code(s): C08K3/04, B82Y30/00, B82Y40/00, C08K9/04
CPC Code(s): C08K3/041
Abstract: capillary underfill formulations that may include fillers. the fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. the surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.
Inventor(s): Artyom Lomayev of Nizhny Novgorod (RU) for intel corporation, Alexey Khoryaev of Nizhny Novgorod (RU) for intel corporation, Sergey Sosnin of Zavolzhie (RU) for intel corporation
IPC Code(s): G01S5/02, G01S5/00
CPC Code(s): G01S5/0273
Abstract: an apparatus and system of user equipment (ue) location determination using transmission-reception points (trps) are described. uplink angle of arrival (ul-aoa). ul relative time of arrival (ul-rtoa), and/or ul sounding reference signal reference signal received power (srs-rsrp) measurements use an ul antenna reference point (arp) identifier (id), which is associated with a ul arp location (trp panel) that is relative to the trp geographical coordinates. the location management function (lmf) requests additional path reporting for ue positioning for downlink time difference of arrival (dl-tdoa), ul-tdoa, and multi-round trip time (rtt) reporting. the additional path information includes relative time difference and path quality indicator values and possibly a path rsrp value. the lmf indicates a maximum number of additional paths to be reported. the expected value and uncertainty range for each trp is reported for downlink angle of departure (dl-aod) measurements.
Inventor(s): Richard Laming of Santa Clara CA (US) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/32, G02B6/26
CPC Code(s): G02B6/32
Abstract: an optical interconnect arrangement for use in transmitting light between a photonic integrated circuit and a plurality of optical fibres, comprises a plurality of primary optical beam management elements, a plurality of secondary optical beam management elements, and a plurality of optical fibre alignment structures. each optical fibre alignment structure is configured to receive a corresponding optical fibre so that the end of the corresponding optical fibre is aligned with, but separated from, a corresponding one of the secondary optical beam management elements, and the optical interconnect arrangement defines a plurality of optical paths, each optical path extending from a surface of the optical interconnect arrangement to the end of a corresponding one of the optical fibre alignment structures via a corresponding one of the primary optical beam management elements and a corresponding one of the secondary optical beam management elements. an optical system is also disclosed which comprises the optical interconnect arrangement, a photonic integrated circuit, and a plurality of optical fibres.
Inventor(s): Xiaoqian Li of Chandler AZ (US) for intel corporation, Omkar G. Karhade of Chandler AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/42
CPC Code(s): G02B6/4278
Abstract: an architecture for v-groove fiber attach for a photonic integrated circuit (pic). the architecture is characterized by a pic with a thickness of less than 100 microns. a carrier layer is attached to the non-active surface of the pic and v-grooves are etched into the active surface of the pic wafer. the carrier layer functions as an etch stop during the etching of the v-grooves, thereby becoming a floor for the v-grooves and enabling the v-grooves to extend to a depth equal to the thickness of the pic. the carrier layer can be a glass layer. the carrier layer can also be an electronic integrated circuit (eic).
Inventor(s): Joshua KEVEK of Portland OR (US) for intel corporation, Mitchell SENGER of Portland OR (US) for intel corporation
IPC Code(s): G02B21/16, G02B21/00
CPC Code(s): G02B21/16
Abstract: this disclosure describes systems, methods, and devices related to fault isolation via electron photoemission microscopy (fivepm). a system may attach a device under test (dut) comprising a region of interest (roi) for fault isolation to a tester device, wherein the dut is an integrated circuit. the system may pulse an ultraviolet uv beam targeting the roi on the
Inventor(s): Joshua KEVEK of Portland OR (US) for intel corporation, Mitchell SENGER of Portland OR (US) for intel corporation
IPC Code(s): G02B21/16, G02B21/00
CPC Code(s): G02B21/16
Abstract: dut using a uv laser. the system may capture, using a detector, excited electrons as signals based on the uv beam targeting the roi. the system may synchronize a time domain electrical signal analyzer to a reference frequency. the system may generate a rastered image associated with the fault isolation.
Inventor(s): Charles Cameron Mokhtarzadeh of Portland OR (US) for intel corporation, Sanjana Vijay Karpe of Hillsboro OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, James Munro Blackwell of Portland OR (US) for intel corporation, Lauren Elizabeth Doyle of Portland OR (US) for intel corporation, Brandon Jay Holybee of Portland OR (US) for intel corporation
IPC Code(s): G03F7/004, C23C16/40, C23C16/455, C23C16/56, G03F7/00, G03F7/16, G03F7/20, H01L21/033
CPC Code(s): G03F7/0042
Abstract: tin carboxylate precursors for metal oxide resist layers and related methods are disclosed herein. an example method of fabricating a semiconductor device disclosed herein includes synthesizing a precursor including tin, depositing a metal oxide resist layer on a base material by applying the precursor, the metal oxide resist layer including tin-6 clusters, and patterning the metal oxide resist layer.
Inventor(s): Shouwei Sun of Shanghai (CN) for intel corporation, Lili Ma of Shanghai (CN) for intel corporation, Ke Han of Shanghai (CN) for intel corporation, Hemin Han of Shanghai (CN) for intel corporation, Xiaodong Cai of Shanghai (CN) for intel corporation
IPC Code(s): G06F1/16
CPC Code(s): G06F1/1633
Abstract: particular embodiments described herein provide for an electronic device that can be configured to include a first housing, one or more sensors located in the first housing, a second housing, and a slope located in the second housing to reflect light radiation to the one or more sensors when the first housing is over the second housing. the electronic device can be a laptop computer where the first housing is a lid that includes a display and the second housing is a base that includes a keyboard and the one or more sensors face the keyboard when the first housing is over the second housing when the laptop computer is in a closed configuration.
20240272701. HYBRID CORE ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Suranjan Chakraborty of Bangalore (IN) for intel corporation, Venkatesh Satnur of Bengaluru (IN) for intel corporation, Anil Bindu Lingambudi of Bengaluru (IN) for intel corporation, Ashwini Khandekar of Bengaluru (IN) for intel corporation, Stephen H. Gunther of Beaverton OR (US) for intel corporation
IPC Code(s): G06F1/3296, G06F1/3206, G06F1/324
CPC Code(s): G06F1/3296
Abstract: systems, apparatuses and methods may provide for technology that determines a selected priority corresponding to a selected region in a microprocessor, determines an adjacent priority corresponding to an adjacent region in the microprocessor, wherein the adjacent region is adjacent to the selected region, and places the adjacent region in a first reduced power state if the selected priority is greater than the adjacent priority and temperature of the selected region is less than a selected temperature threshold associated with the selected region.
Inventor(s): Ramamurthy KRITHIVAS of Gilbert AZ (US) for intel corporation, Eswaramoorthi NALLUSAMY of Cedar Park TX (US) for intel corporation, Anand K. ENAMANDRAM of Folsom CA (US) for intel corporation, Mahesh S. NATU of Folsom CA (US) for intel corporation, Eric J. DEHAEMER of Shrewsbury MA (US) for intel corporation, Filip SCHMOLE of Portland OR (US) for intel corporation, Bharat S. PILLILLI of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4403
Abstract: examples described herein relate to an apparatus that includes an interface and circuitry to: prior to boot of a processor, configure a memory address decoder to increase a memory region size associated with firmware access from a first size to a second size, wherein the second size is larger than the first size. in some examples, the memory address decoder is to decode an address space in a serial peripheral interface (spi) flash device to determine a location of a firmware interface table (fit) in the second size of the memory region and the second circuitry is to access an entry in the fit to determine a location of a boot firmware.
Inventor(s): Yong Jiang of Shanghai (CN) for intel corporation, Yuanyuan Li of Shanghai (CN) for intel corporation, Jianghong Du of Shanghai (CN) for intel corporation, Kuilin Chen of Hillsboro OR (US) for intel corporation, Thomas A. Tetzlaff of Portland OR (US) for intel corporation
IPC Code(s): G06F9/48, G06F8/41, G06F9/30, G06F9/52, G06T1/20
CPC Code(s): G06F9/4843
Abstract: embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. one embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and broadcast a result of an operation specified in association with the barrier synchronization request.
20240273028. ENERGY CONSUMPTION MEASUREMENT_simplified_abstract_(intel corporation)
Inventor(s): Corey D. GOUGH of Portland OR (US) for intel corporation, Yuval BUSTAN of Moshav Mismeret (IL) for intel corporation, Arvind RAMAN of Austin TX (US) for intel corporation, Mariusz ORIOL of Gdynia (PL) for intel corporation, Nilanjan PALIT of Northborough MA (US) for intel corporation, Philip ABRAHAM of Rye NY (US) for intel corporation, Priyanka GANESH of Redmond WA (US) for intel corporation, Daniel G. CARTAGENA of Chandler AZ (US) for intel corporation, Mateusz DUCHALSKI of Bydgoszcz (PL) for intel corporation
IPC Code(s): G06F12/0842, G06F1/3206, G06F1/3293, G06F12/084
CPC Code(s): G06F12/0842
Abstract: examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. the circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. the energy usage of the process can be based on dynamic capacitance (cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.
Inventor(s): Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Akhilesh S. Thyagaturu of Ruskin FL (US) for intel corporation, Marcos Carranza of Portland OR (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation
IPC Code(s): G06F16/28, G06F21/60
CPC Code(s): G06F16/285
Abstract: systems, apparatuses and methods include technology that identifies first data that is autonomously generated, where the first data is associated with a first source. the technology may further determine that the first data is to be marked with an indication that the first data is associated with the first source, generate an identifier associated with the first data based on the first data being determined to be marked, where the identifier indicates that the first data is associated with the first source, and store the identifier to an entry in a storage that is remotely accessible.
Inventor(s): Souvik Kundu of Los Angeles CA (US) for intel corporation, Sharath Nittur Sridhar of San Diego CA (US) for intel corporation, Anahita Bhiwandiwalla of San Jose CA (US) for intel corporation
IPC Code(s): G06F30/27
CPC Code(s): G06F30/27
Abstract: methods, apparatus, systems, and articles of manufacture design and test electronics using artificial intelligence are disclosed. an example apparatus includes programmable circuitry to instantiate: use a first trained artificial intelligence (ai)-based model to generate verification code based on an input design; execute the verification code to generate a verifiability score for the input design; and based on the verifiability score, use a second trained ai-model to adjust the input design.
Inventor(s): Sourav Saha of Bangalore (IN) for intel corporation, Sagarkumar Ashokbhai Rana of Bharuch (IN) for intel corporation
IPC Code(s): G06F30/31
CPC Code(s): G06F30/31
Abstract: example systems, methods, apparatus, and articles of manufacture to implement localized context configuration for electronic design automation (eda) are disclosed. examples disclosed herein partition a circuit design into a plurality of contexts based on output data from a first execution iteration of an eda tool, the output data including a netlist representative of the circuit design, the output data based on a first set of configuration parameters applied globally to the circuit design by the eda tool. disclosed examples also identify an outlier context in the plurality of contexts based on the output data. disclosed examples further provide the eda tool with a second set of configuration parameters to apply locally to the outlier context in a second execution iteration of the eda tool, the eda tool to apply the first set of configuration parameters to other ones of the contexts not identified as outliers.
20240273411. ARTIFICIAL INTELLIGENCE REGULATORY MECHANISMS_simplified_abstract_(intel corporation)
Inventor(s): Markus Dominik MUECK of Unterhaching (DE) for intel corporation, John M. ROMAN of Beaverton OR (US) for intel corporation, Amit ELAZARI BAR ON of Pacifica CA (US) for intel corporation
IPC Code(s): G06N20/00, H04L9/32
CPC Code(s): G06N20/00
Abstract: the present disclosure is related to mechanisms for enforcing compliance with artificial intelligence (ai) and machine learning (ml) regulatory frameworks. the ai regulatory enforcement mechanisms are capable of testing ai systems for quality, accuracy, and robustness, as well as for compliance with ai regulatory requirements. ai regulatory enforcement mechanisms provide restrictions and safeguards by controlling actions of ai systems and/or other components to prevent erroneous or biased ai system predictions from being used, and potentially causing harm to individuals or objects. the ai regulatory enforcement mechanisms ensure that ai systems function in ways that are secure, trustworthy, and ethical.
Inventor(s): Chen WANG of San Jose CA (US) for intel corporation, Yi-Jen CHIU of San Jose CA (US) for intel corporation, Huan DOU of Beijing (CN) for intel corporation, Ying ZHANG of Los Gatos CA (US) for intel corporation
IPC Code(s): G06T5/60, G06T5/20
CPC Code(s): G06T5/60
Abstract: this disclosure describes systems. methods. and devices related to deep learning-based video processing. a system may include a first neural network associated with generating kernel weights for the dl vp. the first neural network using a first hardware device: and a second neural network associated with filtering image pixels for the dlvp. the second neural network using a second hardware device, wherein the first neural network receives image data and generates the kernel weights based on the image data, and wherein the second neural network receives the image data and the kernel weights. and generates filtered image data based on the image data and the kernel weights.
Inventor(s): Changliang Wang of Bellevue WA (US) for intel corporation, Juan Zhao of Shanghai (CN) for intel corporation, Gang Shen of Hillsboro OR (US) for intel corporation, Wei Zong of Beijing (CN) for intel corporation
IPC Code(s): G06V10/10, G06T5/50, G06T7/11, G06T9/00
CPC Code(s): G06V10/16
Abstract: methods and apparatus for tile-based stitching and encoding of images are disclosed. an example apparatus to stitch and encode images includes tile generation circuitry to generate first input tiles from a first image and second input tiles from a second image, the first image from a first camera and the second image from a second camera. the example apparatus also includes stitching circuitry to process the first input tiles and the second input tiles to convert the first input tiles into corresponding first stitched tiles and to convert the second input tiles into corresponding second stitched tiles. the example apparatus further includes encoding circuitry to encode the first stitched tiles and the second stitched tiles in parallel, wherein the tile generation circuitry is to generate the first input tiles and the second input tiles based on division information associated with the encoding circuitry.
Inventor(s): Dongqi Cai of Beijing (CN) for intel corporation, Anbang Yao of Beijing (CN) for intel corporation, Yurong Chen of Beijing (CN) for intel corporation
IPC Code(s): G06V10/77, G06V10/32, G06V10/82
CPC Code(s): G06V10/7715
Abstract: techniques related to application of deep neural networks to video for video recognition and understanding are discussed. a feature map of a deep neural network for a current time stamp of input video is standardized to a standardized feature map and pooled to a feature vector. the feature vector and transform parameters for a prior time stamp are used to generate transform parameters for the current time stamp based on application of a meta temporal relay. the resultant current time stamp transform parameters, such as a hidden state and a cell state of the meta temporal relay, are used to transform the standardized feature map to a normalized feature map for use by a subsequent layer of the deep neural network.
20240274148. SOUND SOURCE SEPARATION USING ANGULAR LOCATION_simplified_abstract_(intel corporation)
Inventor(s): Jesus Ferrer Romero of Guadalajara (MX) for intel corporation, Hector Cordourier Maruri of Guadalajara (MX) for intel corporation, Georg Stemmer of Munich (DE) for intel corporation, Willem Beltman of West Linn OR (US) for intel corporation
IPC Code(s): G10L21/0272, G10L25/30
CPC Code(s): G10L21/0272
Abstract: systems and methods for audio source separation. a deep learning-based system uses an azimuth angle location to separate an audio signal originating from a selected location from other sound. techniques are disclosed for steering a virtual direction of a microphone towards a selected speaker. a deep-learning based audio regression method, which can be implemented as a neural network, learns to separate out various speakers by leveraging spectral and spatial characteristics of all sources. the neural network can focus on multiple sources in multiple respective target directions, and cancel out other sounds. a user can choose which source to listen to. the network can use the time-domain signal and a frequency-domain signal to separate out the target signal and generate a separated audio output. the direction of the selected speaker relative to the microphone array can be input to the system as a vector.
Inventor(s): Chenghai Yan of Shanghai (CN) for intel corporation, Lei Wang of Shanghai (CN) for intel corporation, Maoxin Yin of Shanghai (CN) for intel corporation, Wenzhi Wang of Shanghai (CN) for intel corporation
IPC Code(s): H01L23/498, H01L23/00, H01L23/66
CPC Code(s): H01L23/49838
Abstract: methods, apparatus, systems, and articles of manufacture to reduce impedance discontinuities and crosstalk in integrated circuit packages are disclosed. a disclosed apparatus includes: a package substrate, and a ball grid array on a first surface of the package substrate. the ball grid array includes a first ball and a second ball adjacent the first ball. the ball grid array is to enable the package substrate to be electrically coupled to a circuit board. the apparatus further includes a metal interconnect within the package substrate. the metal interconnect is electrically coupled to the first ball. the metal interconnect includes an inductive loop that extends toward the second ball.
Inventor(s): Adel Elsherbini of Tempe AZ (US) for intel corporation, Shawna Liff of Scottsdale AZ (US) for intel corporation, Johanna Swan of Scottsdale AZ (US) for intel corporation, Gerald Pasdast of San Jose CA (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/304, H01L21/48, H01L23/00
CPC Code(s): H01L23/5385
Abstract: techniques and mechanisms for high interconnect density communication with an interposer. in some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. a first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. a second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. in another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
20240274576. DIRECT BONDING IN MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Feras Eid of Chandler AZ (US) for intel corporation, Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L23/00
CPC Code(s): H01L25/0655
Abstract: disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. for example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region including metal contacts that are distributed non-uniformly. in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact.
Inventor(s): Cory BOMBERGER of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anupama BOWONDER of Portland OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/165, H01L29/66
CPC Code(s): H01L29/7853
Abstract: fin smoothing, and integrated circuit structures resulting therefrom, are described. for example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. the semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. the sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. a gate stack is over and conformal with the protruding fin portion of the semiconductor fin. a first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation
IPC Code(s): H04L5/00, H04W76/20, H04W76/30
CPC Code(s): H04L5/0051
Abstract: various embodiments herein provide techniques related to configuration that may be provided to a user equipment (ue). the configuration information may include: a resource configuration that indicates that the ue is to transmit a first reference signal (rs) on a first component carrier of a plurality of component carriers, wherein the first rs is an rs of a first rs set; and a resource configuration that indicates that the ue is to transmit a second rs on a second component carrier of the plurality of component carriers, wherein the second rs is an rs of a second rs set, wherein the first rs resource set and the second rs resource set are linked for bandwidth aggregation. other embodiments may be described and/or claimed.
Inventor(s): Yaron Klein of Rosh HaAyin (IL) for intel corporation, Dan Horovitz of Rishon Letzion (IL) for intel corporation, Yoni Kahana of Ein Sarid (IL) for intel corporation, Ilil Blum Shem-Tov of Kiryat Tivon (IL) for intel corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/0872
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to generate location-based cryptographic keys. an example includes a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least determine an encryption key, and combine the encryption key with a parameter based on a physical characteristic of a wireless network environment to generate a cryptographic key.
20240275724. OFFLOAD OF ACKNOWLEDGEMENTS TO A NETWORK DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Bo CUI of Shanghai (CN) for intel corporation, Stephen DOYLE of Ennis (IE) for intel corporation
IPC Code(s): H04L47/12, H04L1/1812, H04L9/40, H04L69/22
CPC Code(s): H04L47/12
Abstract: examples described herein relate to a network device apparatus that includes a network interface card to process a received packet. in some examples, based on the received packet only including one or more frames for which acknowledgement of receipt is offloaded to the network interface card, generate an acknowledgement (ack) message to acknowledge receipt of the received packet. in some examples, a frame for which acknowledgement of receipt is offloaded to the network interface card comprises a stream frame compatible with quick user datagram protocol (udp) internet connections (quic). in some examples, a computing platform is coupled to the network interface card. in some examples, based on the received packet only including any frame for which acknowledgement of receipt is not offloaded to the network interface, the computing platform is to generate an ack message for the received packet.
Inventor(s): Tarun Viswanathan of El Dorado Hills CA (US) for intel corporation, Uri Kahana of Givat-Ada (IL) for intel corporation, Alan Ross of Shingle Springs CA (US) for intel corporation, Eran Birk of Haifa (IL) for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/205
Abstract: technologies for providing policy-based secure containers for multiple enterprise applications include a client computing device and an enterprise policy server. the client computing device sends device attribute information and a request for access to an enterprise application to the enterprise policy server. the enterprise policy server determines a device trust level based on the device attribute information and a data sensitivity level based on the enterprise application, and sends a security policy to the client computing device based on the device trust level and the data sensitivity level. the client computing device references or creates a secure container for the security policy, adds the enterprise application to the secure container, and enforces the security policy while executing the enterprise application in the secure container. multiple enterprise applications may be added to each secure container. other embodiments are described and claimed.
20240275921. VIDEO FRAMING_simplified_abstract_(intel corporation)
Inventor(s): Uzi Cohen of Petah-Tikva (IL) for intel corporation, Hava Matichin of Petah Tikva (IL) for intel corporation, Anatoly Litvinov of Binyamina (IL) for intel corporation, Dor Barber of Herzliya (IL) for intel corporation
IPC Code(s): H04N7/15, G06T3/40, G06T5/50, G06V10/25, G06V40/16, H04N7/14
CPC Code(s): H04N7/15
Abstract: framing a video effectively and efficiently in video conferencing, video recording, and live streaming can be a challenge. the framing decision preferably captures users and their actions without degrading the user experience. to address this challenge, a framing pipeline can be implemented to include a plurality of detectors, a multi-detector fusion, and a motion planner. multi-detector fusion can merge detections produced by different detectors at different rates. motion planner can change the framing decision based on a merged region of interest and a target region of interest produced by multi-detector fusion. the framing pipeline includes one or more features that can achieve a robust, temporally stable, and visually pleasing framed video frames that smoothly tracks users over time without causing unpleasant artifacts in the video conferencing experience.
Inventor(s): Sangeetha BANGOLAE of Portland OR (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation, Sudeep PALAT of Cheltenham (GB) for intel corporation, Alexandre Saso STOJANOVSKI of Paris (FR) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Youn Hyoung HEO of Seoul (KR) for intel corporation, Thomas LUETZENKIRCHEN of Taufkirchen (DE) for intel corporation, Ching-Yu LIAO of Portland OR (US) for intel corporation, Abhijeet KOLEKAR of Portland OR (US) for intel corporation
IPC Code(s): H04W28/02, G06F9/48
CPC Code(s): H04W28/0268
Abstract: this disclosure describes systems, methods, and devices related to ran compute qos modeling. a device may decode a compute task request message received from a user equipment (ue), the compute task request message comprising an indication of a compute task to be offloaded to the ran and data of the compute task. the device may establish a ran compute service function (sf) based on support initiated by a service orchestration and chaining function (socf). the device may establish a ran compute bearer based on ran compute qos flow with the ue, wherein the ran compute qos flow spans between the ue, the ran, and the ran compute sf.
Inventor(s): Jing ZHU of Portland OR (US) for intel corporation, Menglei ZHANG of Portland OR (US) for intel corporation, Mustafa AKDENIZ of San Jose CA (US) for intel corporation
IPC Code(s): H04W28/10, H04L47/34, H04W40/02
CPC Code(s): H04W28/10
Abstract: the present disclosure is related to multi-access management services (mams), which is a programmable framework that provides mechanisms for the flexible selection of network paths in a multi-access (mx) communication environment, based on an application's needs. generic multi-access (gma) functions are also integrated into the mams framework. the present disclosure discusses keep-alive and probing mechanisms, and traffic splitting update techniques. other implementations may be disclosed and/or claimed.
Inventor(s): Prabhakar Subrahmanyam of San Jose CA (US) for intel corporation, Vishnu Prasadh Sugumar of Santa Clara CA (US) for intel corporation, Patrick L. Connor of Beaverton OR (US) for intel corporation, Ying Feng Pang of San Jose CA (US) for intel corporation, Mark Lawrence Bianco of Mountain View CA (US) for intel corporation
IPC Code(s): H05K7/20, B05B1/16, B05B15/68, B05B15/70, G06F1/20
CPC Code(s): H05K7/20272
Abstract: systems, apparatus, articles of manufacture, and methods to mitigate hotspots in integrated circuit packages using gimballing nozzles and jet vectoring impingement are disclosed. an apparatus includes an array of nozzles to direct a cooling fluid toward an integrated circuit package. the array of nozzles includes a first nozzle and a second nozzle. the apparatus further includes a plate to carry the array of nozzles. the first nozzle is selectively moveable relative to the integrated circuit package and relative to the second nozzle. movement of the first nozzle relative to the integrated circuit package including rotational movement and translational movement.
Inventor(s): Tahir GHANI of Portland OR (US) for intel corporation, Byron HO of Hillsboro OR (US) for intel corporation, Curtis W. WARD of Hillsboro OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation, Christopher P. AUTH of Portland OR (US) for intel corporation
IPC Code(s): H10B10/00, H01L27/06, H01L27/092, H01L29/66
CPC Code(s): H10B10/15
Abstract: embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. in an example, an integrated circuit structure includes a fin. a first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. a gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. a second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
- Intel Corporation
- C08K3/04
- B82Y30/00
- B82Y40/00
- C08K9/04
- CPC C08K3/041
- Intel corporation
- G01S5/02
- G01S5/00
- CPC G01S5/0273
- G02B6/32
- G02B6/26
- CPC G02B6/32
- G02B6/42
- CPC G02B6/4278
- G02B21/16
- G02B21/00
- CPC G02B21/16
- G03F7/004
- C23C16/40
- C23C16/455
- C23C16/56
- G03F7/00
- G03F7/16
- G03F7/20
- H01L21/033
- CPC G03F7/0042
- G06F1/16
- CPC G06F1/1633
- G06F1/3296
- G06F1/3206
- G06F1/324
- CPC G06F1/3296
- G06F9/4401
- CPC G06F9/4403
- G06F9/48
- G06F8/41
- G06F9/30
- G06F9/52
- G06T1/20
- CPC G06F9/4843
- G06F12/0842
- G06F1/3293
- G06F12/084
- CPC G06F12/0842
- G06F16/28
- G06F21/60
- CPC G06F16/285
- G06F30/27
- CPC G06F30/27
- G06F30/31
- CPC G06F30/31
- G06N20/00
- H04L9/32
- CPC G06N20/00
- G06T5/60
- G06T5/20
- CPC G06T5/60
- G06V10/10
- G06T5/50
- G06T7/11
- G06T9/00
- CPC G06V10/16
- G06V10/77
- G06V10/32
- G06V10/82
- CPC G06V10/7715
- G10L21/0272
- G10L25/30
- CPC G10L21/0272
- H01L23/498
- H01L23/00
- H01L23/66
- CPC H01L23/49838
- H01L23/538
- H01L21/304
- H01L21/48
- CPC H01L23/5385
- H01L25/065
- CPC H01L25/0655
- H01L29/78
- H01L29/165
- H01L29/66
- CPC H01L29/7853
- H04L5/00
- H04W76/20
- H04W76/30
- CPC H04L5/0051
- H04L9/08
- CPC H04L9/0872
- H04L47/12
- H04L1/1812
- H04L9/40
- H04L69/22
- CPC H04L47/12
- CPC H04L63/205
- H04N7/15
- G06T3/40
- G06V10/25
- G06V40/16
- H04N7/14
- CPC H04N7/15
- H04W28/02
- CPC H04W28/0268
- H04W28/10
- H04L47/34
- H04W40/02
- CPC H04W28/10
- H05K7/20
- B05B1/16
- B05B15/68
- B05B15/70
- G06F1/20
- CPC H05K7/20272
- H10B10/00
- H01L27/06
- H01L27/092
- CPC H10B10/15
