Intel Corporation patent applications on April 4th, 2024
Patent Applications by Intel Corporation on April 4th, 2024
Intel Corporation: 125 patent applications
Intel Corporation has applied for patents in the areas of H01L23/15 (20), H01L27/088 (19), H01L23/498 (18), H01L21/48 (15), H01L29/0673 (13)
With keywords such as: layer, surface, structure, gate, material, substrate, data, device, dielectric, and glass in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): Rajesh Poornachandran of Portland OR (US) for intel corporation, Ned M. Smith of Beaverton OR (US) for intel corporation, Kathiravetpillai Sivanesan of Portland OR (US) for intel corporation, Satish Chandra Jha of Portland OR (US) for intel corporation, Vesh Raj Sharma Banjade of Portland OR (US) for intel corporation, Arvind Merwaday of Beaverton OR (US) for intel corporation, S M Iftekharul Alam of Hillsboro OR (US) for intel corporation, Andradige Silva of Portland OR (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation
IPC Code(s): B60K35/00, G06N20/00
Abstract: various systems and methods for content adaptation based on seat position or occupant position in a vehicle are described herein. an example implementation for content adaptation based on seat position in a vehicle includes: obtaining sensor data, the sensor data including a seat position of a seat in the vehicle; identifying audiovisual content for output to a human occupant in the vehicle; identifying an occupant position of the human occupant, based on the seat position, for a user experience of the output of the audiovisual content; and cause one or more adjustments to the output of the audiovisual content in the vehicle, via an output device, based on the identified position of the human occupant.
20240110975.Secure Remote Debugging_simplified_abstract_(intel corporation)
Inventor(s): Tsvika Kurts of Haifa (IL) for intel corporation, Vladislav Mladentsev of Haifa (IL) for intel corporation, Elias Khoury of Haifa (IL) for intel corporation, Rakesh Kandula of Doddakannelli (IN) for intel corporation, Reuven Elbaum of Haifa (IL) for intel corporation, Boris Dolgunov of San Jose CA (US) for intel corporation
IPC Code(s): G01R31/317, H04L9/08, H04L9/32, H04L9/40
Abstract: methods and apparatus relating to techniques to provide secure remote debugging are described. in an embodiment, a debugging entity generates and transmits a host token to a device via an interface. the interface provides encrypted communication between the debugging entity and the device. the debugging entity generates a session key based at least in part on the host token and a device token. the debugging entity transmits an acknowledgement signal to the device after generation of the session key to initiate a debug session. the debugging entity transmits a debug unlock key to the device to cause the device to be unlocked for the debug session. other embodiments are also disclosed and claimed.
20240111089.NANOROD COATING BETWEEN TWO OPTICAL MEDIUMS_simplified_abstract_(intel corporation)
Inventor(s): Yi YANG of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Robert Alan MAY of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/12, B82Y20/00, G02B1/115, G02B6/122, G02B6/132, G02B6/136, G02B6/43
Abstract: embodiments herein relate to systems, apparatuses, techniques, or processes for improving the refractive index of the coating that optically couples with an optical medium, wherein the coating includes one or more layers that include a plurality of nanorods. the plurality of nanorods within each of the one or more layers may have a similar orientation in the chemical composition. the nanorods within separate layers may have different characteristics, including different orientations, different sizes, and/or different chemical compositions. other embodiments may be described and/or claimed.
20240111090.DIRECTLY COUPLED OPTICAL INTERPOSER_simplified_abstract_(intel corporation)
Inventor(s): Robert A. May of Chandler AZ (US) for intel corporation, Tarek Ibrahim of Mesa AZ (US) for intel corporation, Shriya Seshadri of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Lilia May of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Zhichao Zhang of Chandler AZ (US) for intel corporation, Duye Ye of Phoenix AZ (US) for intel corporation, Yosuke Kanaoka of Chandler AZ (US) for intel corporation, Robin McRee of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/12, G02B6/13
Abstract: a device comprises a substrate and an ic die, which may be a photonic ic. the substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. the hole comprises a first sidewall. the optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. the ic die is within the hole and comprises a second sidewall and an optical port at the second sidewall. the second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. the substrate may include a recess to receive another device comprising a socket.
20240111092.PILLAR STRUCTURES ON AN OPTICAL WAVEGUIDE_simplified_abstract_(intel corporation)
Inventor(s): Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation, Jeremy D. ECTON of Gilbert AZ (US) for intel corporation, Suddhasattwa NAD of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/122, G02B6/13
Abstract: embodiments herein relate to systems, apparatuses, techniques for an optical waveguide that includes a plurality of pillar structures that are in an optical path between the optical waveguide and a pic. in embodiments, the plurality of pillar structures form an evanescent coupling structure that increases the alignment tolerance between the pic and the optical waveguide. in embodiments, an end of each of the plurality of pillar structures may include a mass of material, such as gold, silver, or copper, that light from the pic interacts with in a plasmon effect to focus the light on to the optical waveguide. other embodiments may be described and/or claimed.
Inventor(s): Benjamin Duong of Phoenix AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Sandeep Gaan of Phoenix AZ (US) for intel corporation
IPC Code(s): G02B6/122, G02B6/13
Abstract: various embodiments disclosed relate to routing optical signals from silicon photonics, such as a photonic integrated circuit. the present disclosure includes a glass recirculatory layer with waveguides at varying heights to allow re-routing of such optical signals from silicon photonics, such as a photonic integrated circuit. re-routing of optical signals can be accomplished in the glass recirculatory layer with reduced losses due to reduced intersections of waveguides therein.
Inventor(s): Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation
IPC Code(s): G02B6/122
Abstract: a hybrid plasmonic waveguide and associated methods are disclosed. in one example, the electronic device includes combining an electromagnetic wave propagating in a waveguide with a high refractive index and a surface plasmon from a metal surface to create a hybrid plasmon wave in a low refractive index material separating the dielectric waveguide and metal surface. in selected examples, surface mounted hybrid plasmonic waveguides are shown. in selected examples hybrid plasmonic waveguides embedded in glass interposers are shown.
Inventor(s): Vineeth ABRAHAM of Phoenix AZ (US) for intel corporation, Wesley MORGAN of Lake Oswego OR (US) for intel corporation, Eric MORET of Beaverton OR (US) for intel corporation, Paul DIGLIO of Gaston OR (US) for intel corporation, Srikant NEKKANTY of Chandler AZ (US) for intel corporation
IPC Code(s): G02B6/30, G02B6/42
Abstract: the present disclosure relates to a method including providing a die including a cavity therein, wherein the die further may include a die fiducial on a top surface. the method further includes placing a lens structure in the cavity of the die, wherein the lens structure may include a lens fiducial on a front surface. the method also includes moving the lens structure in the cavity to a position until a lens fiducial image may be captured in an image processing system when the lens fiducial and the die fiducial coincide and lie in a plane orthogonal to the top surface of the die. a corresponding system is also disclosed herein.
Inventor(s): Mohammad HAGHIGHIPANAH of Tigard OR (US) for intel corporation, Rita CHATTOPADHYAY of Chandler AZ (US) for intel corporation
IPC Code(s): G05D1/02, G01S17/86, G01S17/89, G06T7/20
Abstract: a method for motion tracking is provided including receive first data, receive second data, transform the second data to generate transformed second data corresponding to the first frame; determine a first weighting factor for the first data and a second weighting factor for the transformed second data; weight the first data using the first weighting factor to generate first weighted data; weight the transformed second data using the second weighting factor to generate second weighted data; and combine the weighted first data and the weighted second data to generate combined image data. the first data include a first frame of a first scene of an environment detected by a camera or image sensor. the second data include a second frame of a second scene of an environment detected by a light detection and ranging (lidar) sensor. at least a subset of the second scene corresponds to the first scene.
Inventor(s): Barnes Cooper of Hillsboro OR (US) for intel corporation, Aleksander Magi of Portland OR (US) for intel corporation, Arvind Kumar of Beaverton OR (US) for intel corporation, Giuseppe Raffa of Portland OR (US) for intel corporation, Wendy March of Portland OR (US) for intel corporation, Marko Bartscherer of Chula Vista CA (US) for intel corporation, Irina Lazutkina of Hillsboro OR (US) for intel corporation, Duck Young Kong of Beaverton OR (US) for intel corporation, Meng Shi of Hillsboro OR (US) for intel corporation, Vivek Paranjape of Hillsboro OR (US) for intel corporation, Vinod Gomathi Nayagam of San Jose CA (US) for intel corporation, Glen J. Anderson of Beaverton OR (US) for intel corporation
IPC Code(s): G06F1/16, G06F3/16, G06F9/54, G06F21/32, G06V40/16
Abstract: methods and apparatus to operate closed-lid portable computers are disclosed. an example portable computer includes a first display on a lid of the portable computer, the first display to be deactivated when the lid is in a closed position; a second display distinct from the first display, the second display to be visible when the lid is in the closed position; instructions; and processor circuitry to execute the instructions to cause activation of the first display in response to a user interaction with the second display while the lid is in the closed position.
Inventor(s): Deepak Dasalukunte of Beaverton OR (US) for intel corporation, Amy Whitcombe of Saratoga CA (US) for intel corporation, Finbarr O'Regan of Innishannon (IE) for intel corporation, Conor O'Keeffe of Cork (IE) for intel corporation, Sundar Krishnamurthy of Dublin CA (US) for intel corporation
IPC Code(s): G06F1/26
Abstract: an apparatus can include at least two circuit portions having separate power sequencer circuitry. the apparatus can further include processing circuitry configured to control at least one portion of the at least two circuit portions to operate at an initial low power level and subsequent higher power levels to full operation.
Inventor(s): Sakthi Priyan B S of Bangalore (IN) for intel corporation, Shashi Shekhar SINGH of BANGALORE (IN) for intel corporation, Subhajit GHOSH of Bengaluru (IN) for intel corporation, Ankita Vilas GAWADE of Pune (IN) for intel corporation, Gokul SANKER V G of Kollam (IN) for intel corporation, Mandar Chandrakant THORAT of Bengaluru (IN) for intel corporation, Vikrant THIGLE of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/28
Abstract: a method is described. the method includes receiving system level power information. the method includes causing a power supply unit's voltage conversion switching frequency to change based on the system level power information. the power supply unit supplies power to a system that includes at least a processor and memory. the system level power information describes power consumed by at least the processor and memory.
Inventor(s): Samuel Coward of London (GB) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, George A. Constantinides of Santa Clara CA (US) for intel corporation, Emiliano Morini of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F1/324
Abstract: described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. a framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.
Inventor(s): Javier MARTIN LANGERWERF of Toenisvorst (DE) for intel corporation, Jeroen LEIJTEN of Hulsel (NL) for intel corporation, Gerard EGELMEERS of Eindhoven (NL) for intel corporation, Venkata Sudhir KONJETI of Eindhoven (NL) for intel corporation
IPC Code(s): G06F3/06, G06F1/10
Abstract: examples include techniques to reduce power consumption for a distributed computational model mapped onto a multi-processing node system. examples are described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall consuming compute circuitry based on availability of data to consume. examples are also described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall producing compute circuitry based on available buffer capacity at a consuming compute circuitry.
20240111459.STORAGE COMMAND COMPRISING TIME PARAMETER_simplified_abstract_(intel corporation)
Inventor(s): Daniel Christian Biederman of Saratoga CA (US) for intel corporation, Jackson L. Ellis of Fort Collins CO (US) for intel corporation
IPC Code(s): G06F3/06
Abstract: an apparatus comprising first circuitry to determine a time parameter associated with a storage operation; and second circuitry to generate a storage command, the storage command including the time parameter, a location for the storage operation, and an opcode specifying the storage operation.
Inventor(s): Robert VAUGHN of Portland OR (US) for intel corporation
IPC Code(s): G06F8/33
Abstract: examples relate to an apparatus, device, method and computer program for generating code. the apparatus is to obtain information on an existing application architecture of a modular application, the information on the existing application architecture comprising, for components of the existing architecture, a formal description of the functionality and usage of the component of the existing architecture, obtain a prompt of a user for generating code for implementing an additional component for the modular application, the prompt comprising a textual description of a desired functionality of the additional component, provide the information on the existing application architecture and the prompt as input for a large language model (llm), obtain an output of the llm, the output comprising a portion of the code for implementing the additional component, and provide the code for implementing the additional component based on the output of the llm.
Inventor(s): Stephen T. PALERMO of Chandler AZ (US) for intel corporation, Srihari MAKINENI of Portland OR (US) for intel corporation, Shubha BOMMALINGAIAHNAPALLYA of East Brunswick NJ (US) for intel corporation, Neelam CHANDWANI of Portland OR (US) for intel corporation, Rany T. ELSAYED of Folsom CA (US) for intel corporation, Udayan MUKHERJEE of Portland OR (US) for intel corporation, Lokpraveen MOSUR of Gilbert AZ (US) for intel corporation, Adwait PURANDARE of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
Abstract: methods for frequency scaling for per-core accelerator assignments and associated apparatus. a processor includes a cpu (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. under this approach, some cores can be configured to support a selective set of avx instructions (such as avx3/5g-isa instructions) and/or amx instructions, while other cores are configured to not support these avx/amx instructions. in one aspect, the selective avx/amx instructions are implemented in one or more isa extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. this enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective avx/amx instructions using other cores. these capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced avx/amx instructions to support accelerated workloads.
Inventor(s): Menachem ADELMAN of Haifa (IL) for intel corporation, Robert VALENTINE of Kriyat Tivon (IL) for intel corporation, Zeev SPERBER of Zikhron Yaakov (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Rinat RAPPOPORT of Haifa (IL) for intel corporation, Jesus CORBAL of King City OR (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation, Elmoustaha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Yuri GEBIL of Nahariya (IL) for intel corporation, Raanan SADE of Kibutz Sarid (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/485, G06F7/487, G06F7/76, G06F9/38, G06F17/16
Abstract: embodiments detailed herein relate to matrix (tile) operations. for example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
20240111534.DETERMINISTIC BROADCASTING FROM SHARED MEMORY_simplified_abstract_(intel corporation)
Inventor(s): Fangwen Fu of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation, Biju George of Folsom CA (US) for intel corporation, Jorge Parra of El Dorado Hills CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/30, G06F9/54
Abstract: embodiments described herein provide a technique enable a broadcast load from an l1 cache or shared local memory to register files associated with hardware threads of a graphics core. one embodiment provides a graphics processor comprising a cache memory and a graphics core coupled with the cache memory. the graphics core includes a plurality of hardware threads and memory access circuitry to facilitate access to memory by the plurality of hardware threads. the graphics core is configurable to process a plurality of load request from the plurality of hardware threads, detect duplicate load requests within the plurality of load requests, perform a single read from the cache memory in response to the duplicate load requests, and transmit data associated with the duplicate load requests to requesting hardware threads.
Inventor(s): Jason Agron of San Jose CA (US) for intel corporation, Andreas Kleen of Portland OR (US) for intel corporation, Rangeen Basu Roy Chowdhury of Beaverton OR (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
Abstract: techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. in an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. the page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. in another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.
Inventor(s): Marian HORGAN of Cork (IE) for intel corporation, Mateusz POLROLA of Lodz (PL) for intel corporation, Fei Z. WANG of Shannon (IE) for intel corporation, John J. BROWNE of Limerick (IE) for intel corporation, Laurent COQUEREL of Limerick (IE) for intel corporation
IPC Code(s): G06F9/50, G06F9/54
Abstract: examples described herein relate to an accelerator that includes an interface and circuitry coupled to the interface. in some examples, the circuitry is configured to access compressed data, decompress the compressed data, and output the decompressed data based on a call to an application programming interface (api). in some examples, based on a first call to the api having first values, the circuitry is to decompress at least a subset of the data and output at least one strict subset of the decompressed data. in some examples, based on a second call to the api having second values, the circuitry is to decompress an entirety of the data and output the decompressed data.
20240111590.ORDERED THREAD DISPATCH FOR THREAD TEAMS_simplified_abstract_(intel corporation)
Inventor(s): Biju George of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Ben Ashbaugh of Folsom CA (US) for intel corporation, Roland Schulz of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/50, G06T1/20
Abstract: an apparatus to facilitate ordered thread dispatch for thread teams is disclosed. the apparatus includes one or more processors including a graphic processor, the graphics processor including a plurality of processing resources, and wherein the graphics processor is to: allocate a thread team local identifier (id) for respective threads of a thread team comprising a plurality of hardware threads that are to be executed solely by a processing resource of the plurality of processing resources; and dispatch the respective threads together into the processing resource, the respective threads having the thread team local id allocated.
20240111598.SEQUENCING CIRCUIT FOR A PROCESSOR_simplified_abstract_(intel corporation)
Inventor(s): Shidlingeshwar Khatakalle of Gadhinglaj (IN) for intel corporation, Vijay Anand Mathiyalagan of Austin TX (US) for intel corporation, Diyanesh Babu Chinnakkonda Vidyapoornachary of Kaggadasapura (IN) for intel corporation
IPC Code(s): G06F9/50
Abstract: in an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. the sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.
Inventor(s): Biju George of Folsom CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, James Valerio of North Plains OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation
IPC Code(s): G06F9/52, G06F9/30
Abstract: low-latency synchronization utilizing local team barriers for thread team processing is described. an example of an apparatus includes one or more processors including a graphics processor, the graphics processor including a plurality of processing resources; and memory for storage of data including data for graphics processing, wherein the graphics processor is to receive a request for establishment of a local team barrier for a thread team, the thread team being allocated to a first processing resource, the thread team including multiple threads; determine requirements and designated threads for the local team barrier; and establish the local team barrier in a local register of the first processing resource based at least in part on the requirements and designated threads for the local barrier.
Inventor(s): Marcos Carranza of Portland OR (US) for intel corporation, Cesar Martinez-Spessot of Hillsboro OR (US) for intel corporation, Mateo Guzman of Beaverton OR (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Karthik Kumar of Chandler AZ (US) for intel corporation, Rajesh Poornachandran of Portland OR (US) for intel corporation, Kshitij Arun Doshi of Tempe AZ (US) for intel corporation
IPC Code(s): G06F9/54, H04L67/133
Abstract: embodiments described herein are generally directed to the use of sidecars to perform dynamic api contract generation and conversion. in an example, a first sidecar of a source microservice intercepts a first call to a first api exposed by a destination microservice. the first call makes use of a first api technology specified by a first contract and is originated by the source microservice. an api technology is selected from multiple api technologies. the selected api technology is determined to be different than the first api technology. based on the first contract, a second contract is dynamically generated that specifies an intermediate api that makes use of the selected api technology. a second sidecar of the destination microservice is caused to generate the intermediate api and connect the intermediate api to the first api.
Inventor(s): Raoul Rivas Toledano of Hillsboro OR (US) for intel corporation, Udayan Kapaley of Hillsboro OR (US) for intel corporation, Ahmad Yasin of Haifa (IL) for intel corporation, Karthik Gopalakrishnan of Folsom CA (US) for intel corporation, Marc Torrant of Folsom CA (US) for intel corporation
IPC Code(s): G06F11/34, G06F9/30
Abstract: detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. in some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. for example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.
Inventor(s): Ahmad Yasin of Haifa (IL) for intel corporation, Anton Hanna of Nof Hagalil (IL) for intel corporation, Yuval Alon of Haifa (IL) for intel corporation, Amandeep Kaur of Ropar (IN) for intel corporation
IPC Code(s): G06F11/34, G06F9/30
Abstract: techniques and mechanisms for circuitry of a processor to determine a count of prefetch instructions which have been retired, or are designated for retirement. in an embodiment, a performance monitoring unit (pmu) monitors the execution of an instruction sequence by a core of said processor. the pmu detects the retirement of a first instruction, and further makes a first determination that the instruction is of a prefetch instruction type. based on the first determination, counter circuitry of the processor updates a count of one or more instruction retirements, wherein each such retired instruction is of the prefetch instruction type. the pmu further makes a second determination that another retired second instruction is of a non-prefetch instruction type. in another embodiment, the counter circuitry prevents any updating of that same count based on the second determination.
Inventor(s): Seth Pugsley of Hillsboro OR (US) for intel corporation, Mark Dechene of Hillsboro OR (US) for intel corporation, Ryan Carlson of Hillsboro OR (US) for intel corporation, Manjunath Shevgoor of Beaverton OR (US) for intel corporation
IPC Code(s): G06F12/0862, G06F9/345, G06F12/0882
Abstract: techniques for prefetching by a hardware processor are described. in certain examples, a hardware processor includes execution circuitry, cache memories, and prefetcher circuitry. the execution circuitry is to execute instructions to access data at a memory address. the cache memories include a first cache memory at a first cache level and a second cache memory at a second cache level. the prefetcher circuitry is to prefetch the data from a system memory to at least one of the plurality of cache memories, and it includes a first-level prefetcher to prefetch the data to the first cache memory, a second-level prefetcher to prefetch the data to the second cache memory, and a plurality of prefetch filters. one of the prefetch filters is to filter exclusively for the first-level prefetcher. another of the prefetch filters is to maintain a history of demand and prefetch accesses to pages in the system memory and to use the history to provide training information to the second-level prefetcher.
20240111691.TIME-AWARE NETWORK DATA TRANSFER_simplified_abstract_(intel corporation)
Inventor(s): Daniel Christian Biederman of Saratoga CA (US) for intel corporation, Kenneth Keels of Austin TX (US) for intel corporation, Renuka Vijay Sapkal of Milpitas CA (US) for intel corporation, Tony Hurson of Austin TX (US) for intel corporation
IPC Code(s): G06F12/14, G06F15/173
Abstract: techniques for time-aware remote data transfers. a time may be associated with a remote direct memory access (rdma) operation in a translation protection table (tpt). the rdma operation may be permitted or restricted based on the time in the tpt.
Inventor(s): Aruni P. Nelson of Folsom CA (US) for intel corporation, Enrico David Carrieri of Placerville CA (US) for intel corporation, Rolf Kuehnis of Portland OR (US) for intel corporation, Peter Onufryk of Flanders NJ (US) for intel corporation, Sridhar Muthrasanallur of Bangalore (IN) for intel corporation
IPC Code(s): G06F13/40, G06F13/22, G06F13/42
Abstract: embodiments herein relate to a universal component interconnect express (ucie) link that includes a mainband and a sideband. one or more pieces of logic may identify a data that is to be transmitted on the sideband. the logic may then identify, based on factors such as a characteristic of the data or a characteristic of the link, whether to transmit the data on the mainband. other embodiments may be described and/or claimed.
Inventor(s): Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Changwon Rhee of Rocklin CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Gregory Henry of Hillsboro OR (US) for intel corporation, Peter Caday of Hillsboro OR (US) for intel corporation, Kristopher Wong of San Diego CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F7/483
Abstract: an apparatus to facilitate single precision support for systolic pipeline in a graphics environment is disclosed. the apparatus includes a processor comprising systolic array hardware including a plurality of data processing units, wherein the systolic array hardware is to: receive data for performance of a matrix multiplication operation in a first precision format; convert an original value of the data into two split values with a second precision format having a lower precision than the first precision format; perform the matrix multiplication operation using the two split values in the second precision format, the matrix multiplication operation comprising a split-term operation that utilizes two passes through the systolic array hardware with feedback wiring and local reduction; and generate an emulated result for the matrix multiplication operation in the first precision format.
Inventor(s): Jiasheng Chen of El Dorado Hills CA (US) for intel corporation, Kevin Hurd of Flagler Beach FL (US) for intel corporation, Changwon Rhee of Rocklin CA (US) for intel corporation, Jorge Parra of El Dorado Hills CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, William Zorn of Woodinville WA (US) for intel corporation, Peter Caday of Hillsboro OR (US) for intel corporation, Gregory Henry of Hillsboro OR (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, Farzad Chehrazi of Hillsboro OR (US) for intel corporation, Amit Karande of Hillsboro OR (US) for intel corporation, Turbo Majumder of Portland OR (US) for intel corporation, Xinmin Tian of Union City CA (US) for intel corporation, Milind Girkar of Hillsboro OR (US) for intel corporation, Hong Jiang of Los Altos CA (US) for intel corporation
IPC Code(s): G06F17/16, G06F7/544, G06T1/20
Abstract: an apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. the apparatus includes matrix acceleration hardware having double-precision (dp) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a dp floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the dp matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the dp matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the dp floating-point format.
Inventor(s): Umer Iftikhar Cheema of Hillsboro OR (US) for intel corporation, Robert Simofi of Dumbravita, Timis (RO) for intel corporation, Deepak Abraham Mathaikutty of Chandler AZ (US) for intel corporation, Arnab Raha of San Jose CA (US) for intel corporation, Dinakar Kondru of Frisco TX (US) for intel corporation
IPC Code(s): G06F17/17, G06F1/03
Abstract: a non-linear activation function in a neural network may be approximated by one or more linear functions. the input range may be divided into input segments, each of which corresponds to a different exponent in the input range of the activation function and includes input data elements having the exponent. target accuracies may be assigned to the identified exponents based on a statistics analysis of the input data elements. the target accuracy of an input segment will be used to determine one or more linear functions that approximate the activation function for the input segment. an error of an approximation of the activation function by a linear function for the input segment may be within the target accuracy. the parameters of the linear functions may be stored in a look-up table (lut). during the execution of the dnn, the lut may be used to execute the activation function.
Inventor(s): Ned SMITH of Beaverton OR (US) for intel corporation, Kshitij A. DOSHI of Tempe AZ (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Kapil SOOD of Washougal WA (US) for intel corporation, Tarun VISWANATHAN of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F21/60, G06F15/173, H04L9/32
Abstract: examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. in some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. access to the memory region can be specified to be one or more of: create, read, update, delete, write, or notify. a memory region can be a page or sub-page sized region. different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.
Inventor(s): Samuel Coward of London (GB) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, George A. Constantinides of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F30/20, G06F8/51
Abstract: described herein are techniques for automated hardware power optimization via e-graph based automatic rtl exploration. these techniques provide a tool that automatically performs rtl optimization and generates power optimized rtl without requiring design engineers to perform labor and knowledge intensive manual optimizations.
20240112006.DEEP LEARNING HARDWARE_simplified_abstract_(intel corporation)
Inventor(s): Horace H. Lau of Mountain View CA (US) for intel corporation, Prashant Arora of Fremont CA (US) for intel corporation, Olivia K. Wu of Los Altos CA (US) for intel corporation, Tony L. Werner of Los Altos CA (US) for intel corporation, Carey K. Kloss of Los Altos CA (US) for intel corporation, Amir Khosrowshahi of San Diego CA (US) for intel corporation, Andrew Yang of Cupertino CA (US) for intel corporation, Aravind Kalaiah of San Jose CA (US) for intel corporation, Vijay Anand R. Korthikanti of Milpitas CA (US) for intel corporation
IPC Code(s): G06N3/063, G06F17/16, G06N3/04, G06N3/08
Abstract: a network of matrix processing units (mpus) is provided on a device, where each mpu is connected to at least one other mpu in the network, and each mpu is to perform matrix multiplication operations. computer memory stores tensor data and a master control central processing unit (mcc) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. the mcc invokes a set of operations on one or more of the mpus based on the instruction, where the set of operations includes operations on the tensor operands. a result is generated from the set of operations, the result embodied as a tensor value.
Inventor(s): Amit Bleiweiss of Yad Binyamin (IL) for intel corporation, Itamar Ben-Ari of Givat HaShlosha (IL) for intel corporation, Michael Behar of Zichron Yaakov (IL) for intel corporation, Guy Jacob of Netanya (IL) for intel corporation, Gal Leibovich of Kiryat Yam (IL) for intel corporation, Jacob Subag of Kiryat Haim (IL) for intel corporation, Lev Faivishevsky of Kfar Saba (IL) for intel corporation, Yaniv Fais of Tel Aviv (IL) for intel corporation, Tomer Schwartz of Even Yehuda (IL) for intel corporation
IPC Code(s): G06N3/082, G06F8/52, G06F9/445, G06N3/04, G06N3/10, G06N5/04
Abstract: in an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. other embodiments are also disclosed and claimed.
Inventor(s): Ganmei YOU of Beijing (CN) for intel corporation, Zhigang WANG of Beijing (CN) for intel corporation, Dawei WANG of Beijing (CN) for intel corporation
IPC Code(s): G06N3/084, G06F18/213, G06N3/04, G06V10/44, G06V10/764, G06V10/82, G06V20/56, G06V20/58, G06V20/64
Abstract: techniques related to training and implementing convolutional neural networks for object recognition are discussed. such techniques may include applying, at a first convolutional layer of the convolutional neural network, 3d filters of different spatial sizes to an 3d input image segment to generate multi-scale feature maps such that each feature map has a pathway to fully connected layers of the convolutional neural network, which generate object recognition data corresponding to the 3d input image segment.
Inventor(s): Fabian OBORIL of Karlsruhe (DE) for intel corporation, Frederik PASCH of Karlsruhe (DE) for intel corporation, Cornelius BUERKLE of Karlsruhe (DE) for intel corporation
IPC Code(s): G06Q50/30
Abstract: disclosed herein are systems, devices, and methods for monitoring and improving utilization of a public transport vehicle. the transport control system determines an in-vehicle status of a passenger transport vehicle based on in-vehicle sensor data about an interior of the passenger transport vehicle. the transport control system also determines a station status at a station stop for the passenger transport vehicle based on station sensor data about the station stop. the transport control system also determines a situational status based on the in-vehicle status and the station status. the transport control system also generates a notification message with movement control information for the passenger transport vehicle or for a passenger, wherein the movement control information is based on the situational status.
Inventor(s): Biju George of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Supratim Pal of Folsom CA (US) for intel corporation, Jorge Parra of El Dorado Hills CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Maxim Kazakov of San Diego CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation
IPC Code(s): G06T1/20, G06F9/30, G06F9/38
Abstract: shared local registers for thread team processing is described. an example of an apparatus includes one or more processors including a graphic processor having multiple processing resources; and memory for storage of data, the graphics processor to allocate a first thread team to a first processing resource, the first thread team including hardware threads to be executed solely by the first processing resource; allocate a shared local register (slr) space that may be directly reference in the isa instructions to the first processing resource, the slr space being accessible to the threads of the thread team and being inaccessible to threads outside of the thread team; and allocate individual register spaces to the thread team, each of the individual register spaces being accessible to a respective thread of the thread team.
20240112369.HUMAN-ROBOT INTERACTIVE WORKSPACE_simplified_abstract_(intel corporation)
Inventor(s): David Gonzalez Aguirre of Portland OR (US) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, Javier Felix Rendon of Zapopan (MX) for intel corporation, Arturo Tellez Velazquez of Huajuapan de Leon (MX) for intel corporation
IPC Code(s): G06T7/80, B25J9/16, G06T7/70, H04N17/00
Abstract: various aspects of techniques, systems, and use cases include provide instructions for calibrating or object identification in a human-robot interactive environment. a technique may include displaying a back illumination image having at least two distinct sections, capturing a scene including the first back illumination image and an object obstructing a portion of one of the at least two distinct sections of the first back illumination image, and identifying, using an orientation of the display screen relative to the camera (e.g., obtained via calibration), location information of the object relative to a robotic device based on the first scene. the technique may include outputting the location information.
Inventor(s): Narayan Srinivasa of San Jose CA (US) for intel corporation
IPC Code(s): G06V20/00, G06F18/214, G06F30/34, G06N3/08, G06V10/44, G06V10/764, G06V10/774, G09G3/20, G09G3/36
Abstract: apparatuses, methods, and articles of manufacture are disclosed. an example apparatus includes processor circuitry to assign a location value hyperdimensional vector (hdv) to a location in an image of a first patch of one or more pixels, assign at least a first channel hdv to the first patch, determine at least one pixel intensity value hdv for each of the one or more pixels in the first patch, bind together each of the pixel intensity value hdvs into at least one patch intensity value hdv, bind together the at least first channel hdv and the at least one patch intensity value hdv to produce a patch consensus intensity hdv, and generate a first hyperdimensional representation patch value hdv of the first patch by binding together at least a combination of the patch consensus intensity hdv and the location value hdv.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, S M Iftekharul Alam of Hillsboro OR (US) for intel corporation, Ignacio J. Alvarez of Portland OR (US) for intel corporation, Kshitij Doshi of Tempe AZ (US) for intel corporation, Francesc Guim Bernat of () for intel corporation, Satish Jha of Portland OR (US) for intel corporation, Arvind Merwaday of Hillsboro OR (US) for intel corporation, Vesh Raj Sharma Banjade of Portland OR (US) for intel corporation, Kathiravetpillai Sivanesan of Portland OR (US) for intel corporation
IPC Code(s): G07C5/00, H04W74/00
Abstract: a dtaas architecture is described to support communication-side optimization and to reduce communication overhead while meeting necessary reliability and latency requirements. the disclosure describe techniques for utilizing dt resources for v2x environments using both virtual and physical “twin” resources to achieve improved resiliency. moreover, to optimize redundancy costs, the ratio of virtual dt nodes to physical dt nodes may be asymmetrical. an asymmetric approach to dt redundancies involving both virtual and physical resources enables greater flexibility in managing deployment costs.
Inventor(s): Nazila Haratipour of Portland OR (US) for intel corporation, Christopher Neumann of Portland OR (US) for intel corporation, Brian Doyle of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Bernal Granados Alpizar of Beaverton OR (US) for intel corporation, Sarah Atanasov of Beaverton OR (US) for intel corporation, Matthew Metz of Portland OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Jack Kavalieros of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation
IPC Code(s): G11C11/22, H01L27/11507, H01L49/02
Abstract: a memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. the shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. the memory device may include an integrated circuit die and be coupled to a power supply. forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.
Inventor(s): Sou-Chi Chang of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Saima Siddiqui of HIllsboro OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation
IPC Code(s): G11C13/00, G11C11/22, H01L45/00
Abstract: techniques and mechanisms for storing data with a memory cell which comprises a ferroelectric (fe) resistive junction. in an embodiment, a memory cell comprises a transistor and a fe resistive junction structure which is coupled to the transistor. the fe resistive junction structure comprises electrode structures, and a layer of a material which is between said electrode structures, wherein the material is a fe oxide or a fe semiconductor. the fe resistive junction structure selectively provides any of various levels of resistance, each to represent a respective one or more bits. a current flow through the fe resistive junction structure is characterized by thermionic emission through a schottky barrier at an interface with one of the electrode structures. in another embodiment, the fe resistive junction structure further comprises one or more dielectric layers each between the layer of material and a different respective one of the electrode structures.
Inventor(s): Sou-Chi Chang of Portland OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Saima Siddiqui of HIllsboro OR (US) for intel corporation, Sarah Atanasov of Beaverton OR (US) for intel corporation, Bernal Granados Alpizar of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation
IPC Code(s): G11C13/00, G11C11/22, H01L45/00
Abstract: techniques and mechanisms for operating a ferroelectric (fe) circuit element as a cell of a crossbar memory array. in an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. the data storage cell is a fe circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. one such layer comprises a fe nitride or a fe oxide. the fe circuit element is operable to selectively enable, or disable, operation as a diode. in another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the fe circuit element to a particular data bit value.
Inventor(s): Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Chun C. Kuo of Hillsboro OR (US) for intel corporation, Andrew Arnold of Hillsboro OR (US) for intel corporation, Reza Bayati of Portland OR (US) for intel corporation
IPC Code(s): H01L21/28, H01L21/02, H01L21/8234, H01L27/088, H01L29/06, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/775
Abstract: techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. in an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. conductive contacts formed over the source and drain regions along a source/drain trench. the gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. the contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.
Inventor(s): Philip Yashar of Portland OR (US) for intel corporation, Gokul Malyavanatham of Hillsboro OR (US) for intel corporation, Hema Vijwani of Edmonds WA (US) for intel corporation
IPC Code(s): H01L21/768, H01L23/498
Abstract: integrated circuit interconnect structures including a niobium-based barrier material. in some embodiments, a layer of essentially niobium may be sputter deposited, for example to a thickness of less than 8 nm at a bottom of an interconnect via. a copper-based fill material may then be deposited over the niobium barrier material. integrated circuit interconnect metallization may comprise some layers of metallization that have a tantalum-based barrier and other layers of metallization that have a niobium-based barrier.
Inventor(s): Hui Jae YOO of Portland OR (US) for intel corporation, Tejaswi K. INDUKURI of Boise ID (US) for intel corporation, Ramanan V. CHEBIAM of Hillsboro OR (US) for intel corporation, James S. CLARKE of Portland OR (US) for intel corporation
IPC Code(s): H01L21/768, H01L23/532
Abstract: a dielectric layer and a method of forming thereof. an opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity �1 and the core material exhibits a second resistivity �2 and �2 is less than �1.
20240112962.DESIGN OF VOLTAGE CONTRAST PROCESS MONITOR_simplified_abstract_(intel corporation)
Inventor(s): Xiao WEN of Beaverton OR (US) for intel corporation, Dipto THAKURTA of Portland OR (US) for intel corporation, Sairam SUBRAMANIAN of Portland OR (US) for intel corporation, David SANCHEZ of Portland OR (US) for intel corporation, Amit PALIWAL of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/66, G01R31/52
Abstract: embodiments disclosed herein include an apparatus for alignment detection. in an embodiment, the apparatus comprises a substrate, and a plurality of devices on the substrate, where each of the plurality of devices comprises a process monitor structure with different offsets from a target value. in an embodiment, a plurality of electrically conductive traces are on the substrate, where each of the plurality of electrically conductive traces has a first end and a second end opposite the first end, and where each of the plurality of electrically conductive traces is electrically coupled at the first end, respectively, with each of the plurality of devices. in an embodiment, the second end of the each of the plurality of electrical traces is within a scan area on the substrate, and where the each of the plurality of electrically conductive traces are not directly electrically coupled with each other.
Inventor(s): Hanyu Song of Chandler AZ (US) for intel corporation, Vinith Bejugam of Chandler AZ (US) for intel corporation, Yonggang Li of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Aaron Garelick of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/13, H01L23/498
Abstract: an integrated circuit (ic) device comprises a substrate comprising a glass core. the glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. a first build-up layer is on at least the first surface. in some embodiments, the corner region comprises a recess and a dielectric material within the recess. in other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. the second region comprises a second compressive stress. the first compressive stress is greater than the second compressive stress.
Inventor(s): Yiqun Bai of Chandler AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Ziyin Lin of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Kyle Arrington of Gilbert AZ (US) for intel corporation, Bohan Shan of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/02, H01L23/495
Abstract: an integrated circuit (ic) device comprises a substrate comprising a glass core. the glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. the glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. the glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. a first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. a first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
Inventor(s): Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, G02B6/42, G02B6/43
Abstract: disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. the microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. the organic substrate may define through substrate vias. the photonic integrated glass layer may be attached to the organic substrate. the photonic integrated glass layer may include photo detectors. the glass interposer may be attached to the organic substrate. the glass interposer may define through glass vias in optical communication with the photo detectors.
20240112973.METHODS AND APPARATUSES FOR THROUGH-GLASS VIAS_simplified_abstract_(intel corporation)
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/498
Abstract: through-glass vias (tgvs) are formed without the use of a planarization step to planarize the tgv fill material after filling holes that extend through a glass layer with the fill material. after the holes are filled with the fill material, the fill material is etched and the glass layer is etched. after etching of the glass is performed, the top and bottom surfaces of the glass layer are recessed relative to the top and bottom surfaces of the fill material in the holes, resulting in formation of fill material stubs. tgv pads are then formed on the fill material stubs. the resulting pads can have protrusions that extend away from a surface of the glass layer. if the tgvs are plated through-holes, a portion of the metal lining the inner wall of a tgv hole can extend past a surface of the glass layer and into a tgv pad.
Inventor(s): Jieying Kong of Chandler AZ (US) for intel corporation, Houssam Jomaa of San Diego CA (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation, Whitney Bryks of Tempe AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Phoenix AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: an electronic system comprising can have a substrate with a core layer formed from at least one layer of glass. the glass layers can each be stacked with a dielectric material disposed between each layer of glass. the glass layers can be prepatterned before assembly of the layered glass core system.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Ravindranath V. Mahajan of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Beomseok Choi of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/15, H01L49/02
Abstract: an electronic device includes a substrate including a core layer; buildup layers on a first surface of the core layer, the buildup layers including first contact pads below the top surface of the buildup layers and second contact pads on a top surface of the buildup layers; and a discrete passive electronic component disposed in the buildup layers, the discrete component including bottom contact pads on a bottom surface of the discrete component and top contact pads on a top surface of the discrete component. the bottom contact pads of the discrete component are bonded to the first contacts pads of the buildup layers and the top contact pads of the discrete component are electrically connected to the second contact pads of the buildup layers.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Aleksandar Aleksov of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Xavier Brun of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/13
Abstract: microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. a cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. a portion of the dielectric material is within the cavity.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L23/14, H01L23/538, H01L23/66, H01L25/065
Abstract: embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of ic dies. a first ic die in the plurality of ic dies is coupled to the substrate by first interconnects, a second ic die in the plurality of ic dies is embedded in the organic dielectric material of the substrate, the second ic die is coupled to the first ic die by second interconnects, the second ic die is coupled to the first side of the interposer structure by third interconnects, and a third ic die in the plurality of ic dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.
Inventor(s): Benjamin Duong of Phoenix AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48
Abstract: microelectronic integrated circuit package structures include a first substrate comprising a first bond plane structure on a surface of the first substrate, and a second substrate comprising a second bond plane structure on a surface of the second substrate, where the first and second bond plane structures are in direct physical contact. a conductive trace on the surface of the first substrate is adjacent to a bonding interface between the first and second bond plane structures and over a recessed surface of the first substrate. a first air gap is between the conductive trace and the recessed surface of the first substrate and a second air gap is between the conductive trace and the bonding interface.
20240113009.POROUS POLYMER DIELECTRIC LAYER ON CORE_simplified_abstract_(intel corporation)
Inventor(s): Whitney Bryks of Tempe AZ (US) for intel corporation, Aaditya Candadai of Chandler AZ (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation, Junxin Wang of Gilbert AZ (US) for intel corporation, Peumie Abeyratne Kuragama of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, B05D3/02, B05D3/04, B05D5/00, H01L21/48, H01L23/14, H01L23/15, H01L23/538
Abstract: an electronic device can include an interposer, a first porous polymer layer, and one or more die. the interposer can include a metallic through via extending from a first surface of the interposer to a second surface of the interposer. the first polymer layer can be adjacent to the first surface of the interposer. the one or more dies can be coupled to the first porous polymer layer and connected to the metallic through via.
20240113017.PLUG IN A METAL LAYER_simplified_abstract_(intel corporation)
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Gurpreet SINGH of Beaverton OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/768
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug within a metal layer of a semiconductor device, where the plug is formed within a cavity that is created through the metal layer. the plug may extend through the metal layer and into a layer below the metal layer, which may be a layer that includes a dielectric and one or more electrical routing features. the plug may include an electrical insulator material. the cavity may be formed by placing a mask above the metal layer and performing an etch through the metal layer subsequently filled with a dielectric, where the plug will be tapered and wider at the top of the plug and become narrower as the plug continues through the metal layer and reaches the layer below the metal layer. other embodiments may be described and/or claimed.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Nikhil MEHTA of Portland OR (US) for intel corporation, Charles H. WALLACE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation
IPC Code(s): H01L23/528, H01L21/768, H01L23/522
Abstract: embodiments of the disclosure are in the field of integrated circuit structure fabrication. in an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ild) layer, the plurality of conductive lines on a same level and along a same direction. a second ild layer is over the plurality of conductive lines and over the first ild layer. a first conductive via is in a first opening in the second ild layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. a second conductive via is in a second opening in the second ild layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation, Pushkar RANADE of San Jose CA (US) for intel corporation, Sagar SUTHRAM of Portland OR (US) for intel corporation, Wilfred GOMES of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation
IPC Code(s): H01L23/532, H01L23/528
Abstract: embodiments disclosed herein include an integrated circuit structure. in an embodiment, the integrated circuit structure comprises an interlayer dielectric (ild), and an opening in the ild. in an embodiment, a first layer lines the opening, and a second layer lines the first layer. in an embodiment, the second layer comprises a semi-metal or transition metal dichalcogenide (tmd). the integrated circuit structure may further comprise a third layer over the second layer.
Inventor(s): Abhishek Anil SHARMA of Portland OR (US) for intel corporation
IPC Code(s): H01L23/532, H01L23/522, H01L23/528
Abstract: embodiments disclosed herein include an integrated circuit structure. in an embodiment, the integrated circuit structure comprises an interlayer dielectric (ild). and an interconnect over the ild. in an embodiment, the interconnect comprises a plurality of first layers, where the first layers comprise a metal, and a plurality of second layer in an alternating pattern with the plurality of first layers. in an embodiment, the second layers comprise a two-dimensional (2d) material.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L23/13, H01L23/15, H01L25/16
Abstract: multi-die packages including at least one glass substrate within a space between two adjacent ic dies or surrounding an interconnect bridge die. the various ic dies may be placed within recesses formed in the glass substrate. the ic die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. the bridge die may be directly bonded or soldered to the adjacent ic dies, providing fine pitch interconnect. the opposite side of the adjacent ic dies and glass substrate may be attached to a host component or may be built up with package dielectric material. metallization features formed on the second side of the glass substrate may electrically interconnect the ic dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.
Inventor(s): Eng Huat GOH of Ayer Itam (MY) for intel corporation, Jiun Hann SIR of Gelugor (MY) for intel corporation, Poh Boon KHOO of Perai (MY) for intel corporation, Hazwani JAFFAR of Kepala Batas (MY) for intel corporation, Hooi San LAM of Air Itam (MY) for intel corporation
IPC Code(s): H01L23/538, H01L23/31, H01L25/00, H01L25/065, H01L25/18
Abstract: embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a die, which may be a processor die, coupled with a first side of a substrate and one or more dies, which may be one or more memory dies, that are coupled with a second side of the substrate opposite the first side of the substrate. all or part of the memory dies may be directly below the die with respect to a plane of the substrate and may be partially or completely within a molding. other embodiments may be described and/or claimed.
Inventor(s): Tayseer Mahdi of Hillsboro OR (US) for intel corporation, Grant Kloster of Lake Oswego OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/02, H01L23/29
Abstract: methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. a backside layer is applied to the wafer prior to chucking. the chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.
Inventor(s): Jason Scott Steill of Phoenix AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Srinivasan Raman of Chandler AZ (US) for intel corporation, Yi Yang of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/62, H01L21/48, H01L23/00, H01L23/15, H01L23/498, H01L23/64
Abstract: various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. the present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
Inventor(s): Srinivasan Raman of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Kripa Chauhan of Santa Clara CA (US) for intel corporation
IPC Code(s): H01L23/64
Abstract: various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. the present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
Inventor(s): Srinivasan Raman of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Jason Scott Steill of Phoenix AZ (US) for intel corporation, Shayan Kaviani of Phoenix AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Yi Yang of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L23/64, H01L21/48, H01L23/15, H01L23/498
Abstract: various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. the present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.
20240113049.PACKAGE SUBSTRATE WITH OPEN AIR GAP STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Cemil S. Geyik of Gilbert AZ (US) for intel corporation, Kemal Aygun of Tempe AZ (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Wei-Lun Jen of Phoenix AZ (US) for intel corporation, Zhiguo Qian of Chandler AZ (US) for intel corporation, Dilan Seneviratne of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/66, H01L23/498, H01L23/538
Abstract: embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (ic) dies coupled to the package substrate on the first side. the plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.
20240113052.SEMICONDUCTOR PACKAGES WITH ANTENNAS_simplified_abstract_(intel corporation)
Inventor(s): Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Adel A. Elsherbini of Chandler AZ (US) for intel corporation, Sasha Oster of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/66, H01L21/48, H01L23/498
Abstract: in various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). the asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. in further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.
Inventor(s): Whitney Bryks of Tempe AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, B23K26/364, H01L21/48, H01L21/56, H01L23/15, H01L23/498
Abstract: an integrated circuit (ic) device comprises a substrate comprising a glass core. the glass core includes a first surface, a second surface opposite the first surface, and a sidewall between the first surface and the second surface. a build-up layer is on at least the first surface. a plurality of regions is on the sidewall. each region comprises a cavity in the sidewall, wherein the cavity spans a first distance in a first direction from the first surface toward the second surface. in addition, the cavity comprises a concave surface having a first depth at the first surface and a second depth at the first distance, the second depth being less than the first depth.
Inventor(s): Xavier F. BRUN of Chandler AZ (US) for intel corporation, Trianggono WIDODO of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L25/065, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/498, H01L23/538, H01L25/00
Abstract: embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. during a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. during a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. the planarization may reveal one or more tsv at the side of the die which is now finished and ready for electrical coupling with other components. as a result, a side of the molding at a side of the die to be coplanar. other embodiments may be described and/or claimed.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon Marin of Gilbert AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L21/52, H01L23/538
Abstract: multi-die packages including a glass substrate within a space between adjacent ic dies. two or more ic die may be placed within recesses formed in a glass substrate. the ic die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. organic package dielectric material may then be built up on both sides of the ic dies and glass substrate. metallization features formed within package dielectric material built up on a first side of the ic die may electrically interconnect the ic dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. metallization features formed within package dielectric material built up on a second side of the first and second ic dies may electrically interconnect the first ic die to the second ic die.
Inventor(s): Brandon Marin of Gilbert AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Srinivas Pietambaram of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation, Ravindranath Mahajan of Chandler AZ (US) for intel corporation, Rahul Manepalli of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/10, H01L21/48, H01L23/00, H01L23/13, H01L23/16, H01L23/473, H01L23/538, H01L25/00, H01L25/18
Abstract: an apparatus is provided which comprises: an interposer comprising glass, one or more redistribution layers on a first interposer surface, one or more conductive contacts on a second interposer surface opposite the first interposer surface, one or more vias through the interposer coupling at least one of the conductive contacts on the second interposer surface with the redistribution layers on the first interposer surface, an integrated circuit device embedded within a cavity in the interposer between the first and second interposer surfaces, the embedded integrated circuit device coupled with a first redistribution layers surface, a stack of two or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface, and mold material surrounding at least one side of the stack of two or more integrated circuit devices. other embodiments are also disclosed and claimed.
Inventor(s): Omkar Karhade of Chandler AZ (US) for intel corporation, Nitin Deshpande of Chandler AZ (US) for intel corporation, Harini Kilambi of Portland OR (US) for intel corporation, Jagat Shakya of Hillsboro OR (US) for intel corporation, Debendra Mallik of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/10, H01L21/66, H01L23/00, H01L23/31
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (ic) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.
Inventor(s): Sourav Dutta of Hillsboro OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Vachan Kumar of Hillsboro OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation
IPC Code(s): H01L27/06, H01L29/08, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/778, H01L49/02
Abstract: techniques are provided herein to form a semiconductor device that has a capacitor structure integrated with the source or drain region of the semiconductor device. a given semiconductor device includes one or more semiconductor regions extending in a first direction between corresponding source or drain regions. a gate structure extends in a second direction over the one or more semiconductor regions. a capacitor structure is integrated with one of the source or drain regions of the integrated circuit such that a first electrode of the capacitor contacts the source or drain region and a second electrode of the capacitor contacts a conductive contact formed over the capacitor structure. the capacitor structure may include a ferroelectric capacitor having a ferroelectric layer between the electrodes.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234, H01L21/84, H01L27/092, H01L27/12
Abstract: techniques are provided to form semiconductor devices that include a gate cut that passes through a plurality of semiconductor bodies (e.g., nanoribbons or nanosheets) such that the gate cut acts as a dielectric spine in a forksheet arrangement with the semiconductor bodies on either side of the gate cut. in an example, two semiconductor devices in a forksheet arrangement include semiconductor bodies directly on either side of a dielectric spine. a gate structure includes a gate dielectric (e.g., high-k gate dielectric material) and a gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) that extends around each of the semiconductor bodies of both semiconductor devices. the dielectric spine interrupts the entire height of the gate structure between the two devices and includes dielectric material (e.g., low-k dielectric), and the gate dielectric of the gate structure is not present along sidewalls of the spine between adjacent bodies.
Inventor(s): Alison V. Davis of Portland OR (US) for intel corporation, Bern Youngblood of Hillsboro OR (US) for intel corporation, Reza Bayati of Portland OR (US) for intel corporation, Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation, Jeffrey Miles Tan of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/762, H01L23/522, H01L29/06, H01L29/423, H01L29/786
Abstract: techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5� difference in width) but substantially the same height (e.g., less than 5 nm difference in height). a given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. according to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.
20240113106.ETCH STOP LAYER FOR METAL GATE CUT_simplified_abstract_(intel corporation)
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Nikhil J. Mehta of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Daniel J. Harris of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234
Abstract: an integrated circuit includes laterally adjacent first and second devices. the first device includes (i) first source and drain regions, (ii) a first body including semiconductor material laterally extending between the first source and drain regions, (iii) a first sub-fin below the first body, and (iv) a first gate structure on the first body. the second device includes (i) second source and drain regions, (ii) a second body including semiconductor material laterally extending from the second source and drain regions, (iii) a second sub-fin below the second body, and (iv) a second gate structure on the second body. a second dielectric material is laterally between the first and second sub-fins. a third dielectric material is laterally between the first and second sub-fins, and above the second dielectric material. a gate cut including first dielectric material is laterally between the first and second gate structures, and above the third dielectric material.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Marni Nabors of Portland OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/762, H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/778, H01L29/786
Abstract: an integrated circuit includes a first device and a laterally adjacent second device. the first device includes a first body including semiconductor material extending from a first source region to a first drain region, and a first gate structure on the first body. the second device includes a second body including semiconductor material extending from a second source region to a second drain region, and a second gate structure on the second body. a gate cut including dielectric material is between and laterally separates the first gate structure and the second gate structure. the first body is separated laterally from the gate cut by a first distance, and the second body is separated laterally from the gate cut by a second distance. in an example, the first and second distances differ by at least 2 nanometers. in an example, the first and second devices are fin-based devices or gate-all-around devices.
Inventor(s): Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Hongqian SUN of Sammamish WA (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Baofu ZHU of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/764, H01L21/8234, H01L29/06, H01L29/423, H01L29/786
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. other embodiments may be described and/or claimed.
20240113109.PLUG BETWEEN TWO GATES OF A SEMICONDUCTOR DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Robert JOACHIM of Beaverton OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Hongqian SUN of Sammamish WA (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L21/8234, H01L23/00
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a plug between two gates within a transistor layer of a semiconductor device. in embodiments, the plug includes a cap at a top of the plug and a liner surrounding at least a portion of the cap, and a base below the cap and the liner. the cap may include a metal. a top of the cap may be even with, or substantially even with, the top of the two gates. the plug may provide a more even surface at a top of a transistor layer where the plug fills in for a gate cut. other embodiments may be described and/or claimed.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Clifford ONG of Portland OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/088, H01L29/06, H01L29/08, H01L29/786
Abstract: integrated circuit structures having fin isolation regions recessed for gate contact are described. in an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. a gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. a dielectric structure is laterally spaced apart from the gate structure. the dielectric structure is not over a channel structure but is on a second sub-fin. a dielectric gate cut plug is between the gate structure and the dielectric structure. a recess is in the dielectric structure and in the dielectric gate cut plug. a conductive structure is in the recess, the conductive structure in lateral contact with a gate electrode of the gate structure.
Inventor(s): Dan S. LAVRIC of Beaverton OR (US) for intel corporation, YenTing CHIU of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation, Mohammad HASAN of Aloha OR (US) for intel corporation, Aryan NAVABI-SHIRAZI of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Wonil CHUNG of Hillsboro OR (US) for intel corporation, Allen B. GARDINER of Portland OR (US) for intel corporation
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. other embodiments may be described and/or claimed.
Inventor(s): Tao Chu of Portland OR (US) for intel corporation, Minwoo Jang of Portland OR (US) for intel corporation, Yanbin Luo of Portland OR (US) for intel corporation, Paul A. Packan of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/092
Abstract: integrated circuit dies, apparatuses, systems, and techniques, are described herein related to low and ultra-low threshold voltage transistor cells. a first transistor cell includes separate semiconductor bodies contacted by separate gate electrodes having a dielectric material therebetween. a second transistor cell includes separate semiconductor bodies contacted by a shared gate electrode that couples to both semiconductor bodies. transistors of the second transistor cell may be operated at a lower threshold voltage than those of the first transistor cell due to increased strain on the semiconductor bodies from the shared gate electrode.
Inventor(s): Elijah V. Karpov of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation
IPC Code(s): H01L27/118
Abstract: an apparatus is provided which comprises: a plurality of logic blocks comprising transistors on a substrate, the logic blocks to implement logic functions; a plurality of input/output (i/o) blocks connecting the logic blocks with components external to the apparatus; a plurality of interconnect layers comprising wires and vias surrounded by interlayer dielectric above the substrate, the wires and vias conductively coupling the plurality of logic blocks and the plurality of i/o blocks; a plurality of programmable switches to configure connections between the plurality of logic blocks and the plurality of i/o blocks; and a ferroelectric material in a capacitor coupled to the gate or on the gate dielectric itself of one or more of the transistors. other embodiments are also disclosed and claimed.
Inventor(s): Walid M. HAFEZ of Portland OR (US) for intel corporation, Jeng-Ya D. YEH of Portland OR (US) for intel corporation, Curtis TSAI of Beaverton OR (US) for intel corporation, Joodong PARK of Portland OR (US) for intel corporation, Chia-Hong JAN of Portland OR (US) for intel corporation, Gopinath BHIMARASETTI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, H01L21/02, H01L21/28, H01L21/8234, H01L21/84, H01L29/423, H01L29/51, H01L29/66
Abstract: high voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. for example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. a first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. the first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. the first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. the semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. the second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. the second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
Inventor(s): Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Changhua Liu of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation
IPC Code(s): H01L49/02, H01L25/16
Abstract: disclosed herein are microelectronics package architectures utilizing in-situ high surface area capacitor in substrate packages and methods of manufacturing the same. the substrates may include an anode material, a cathode material, and a conductive material. the anode material may have an anode surface that may define a plurality of anode peaks and anode valleys. the cathode material may have a cathode surface that may define a plurality of cathode peaks and cathode valleys complementary to the plurality of anode peaks and anode valleys. the conductive material may be located at the anode peaks.
20240113161.TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN_simplified_abstract_(intel corporation)
Inventor(s): Willy RACHMADY of Beaverton OR (US) for intel corporation, Cheng-Ying HUANG of Portland OR (US) for intel corporation, Matthew V. METZ of Portland OR (US) for intel corporation, Nicholas G. MINUTILLO of Beaverton OR (US) for intel corporation, Sean T. MA of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Jack T. KAVALIEROS of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation, Gilbert DEWEY of Beaverton OR (US) for intel corporation
IPC Code(s): H01L29/06, H01L29/08, H01L29/10, H01L29/205, H01L29/423, H01L29/78
Abstract: a transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. a gate structure contacts the top surface of the body. a source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. a first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. a second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., finfet transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
20240113177.STACKED SOURCE OR DRAIN CONTACT FLYOVER_simplified_abstract_(intel corporation)
Inventor(s): Sukru Yemenicioglu of Portand OR (US) for intel corporation, Quan Shi of Portland OR (US) for intel corporation, Marni Nabors of Portland OR (US) for intel corporation, Charles H. Wallace of Portland OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation, Tahir Ghani of Portland OR (US) for intel corporation, Andy Chih-Hung Wei of Yamhill OR (US) for intel corporation, Mohit K. Haran of Forest Grove OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Sivakumar Venkataraman of Hillsboro OR (US) for intel corporation, Reken Patel of Portland OR (US) for intel corporation, Richard Schenker of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/778, H01L29/786
Abstract: an integrated circuit includes a first device having a first source or drain region, and a second device having a second source or drain region that is laterally adjacent to the first source or drain region. a conductive source or drain contact includes (i) a lower portion in contact with the first source or drain region, and extending above the first source or drain region, and (ii) an upper portion extending laterally from above the lower portion to above the second source or drain region. a dielectric material is between at least a section of the upper portion of the conductive source or drain contact and the second source or drain region. in an example, each of the first and second devices is a gate-all-around (gaa) device having one or more nanoribbons, nanowires, or nanosheets as channel regions, or is a finfet structure having a fin-based channel region.
Inventor(s): Mekha George of Hillsboro OR (US) for intel corporation, Seda Cekli of Portland OR (US) for intel corporation, Kilhyun Bang of Portland OR (US) for intel corporation, Krishna Ganesan of Portland OR (US) for intel corporation
IPC Code(s): H01L29/423, H01L21/311, H01L27/088, H01L29/06, H01L29/786
Abstract: materials and techniques for recessing heterogenous materials in integrated circuit (ic) dies. a first etch may reveal a surface at a desired depth, and a second etch may remove material laterally to reveal sidewalls down to the desired depth of the recess. the first etch may be a cyclical etch, and the second etch may be a continuous etch. the first and second etches may occur in a same chamber. the first and second etches may each be selective to materials with similarities. an ic die may have different, substantially coplanar materials at a recessed surface between and below sidewalls of another material. the recess may have squared profile. the recess may be over transistor structures.
20240113212.TECHNOLOGIES FOR PEROVSKITE TRANSISTORS_simplified_abstract_(intel corporation)
Inventor(s): Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Tristan A. Tronic of Aloha OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation, Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Gauri Auluck of Hillsboro OR (US) for intel corporation, I-Cheng Tung of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/775, H01L21/02, H01L21/465, H01L29/06, H01L29/24, H01L29/423, H01L29/49, H01L29/66
Abstract: technologies for a field effect transistor (fet) with a ferroelectric gate dielectric are disclosed. in an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. the perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers, such as undoped semiconductor layers. growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. the lattice-matched layers can be preferentially etched away, leaving the doped semiconductor layers as fins for a ribbon fet. in another embodiment, an interlayer can be deposited on top of a semiconductor layer, and a ferroelectric layer can be deposited on the interlayer. the interlayer can bridge a gap in lattice parameters between the semiconductor layer and the ferroelectric layer.
Inventor(s): Arnab Sen Gupta of Hillsboro OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Matthew V. Metz of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Raseong Kim of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Kevin P. O'Brien of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation, Jason C. Retasket of Beaverton OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Dominique A. Adams of Portland OR (US) for intel corporation, Carly Rogan of North Plains OR (US) for intel corporation, Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Brandon Holybee of Portland OR (US) for intel corporation, Rachel A. Steinhardt of Beaverton OR (US) for intel corporation, Sudarat Lee of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/78, H01L21/02, H01L29/20, H01L29/24, H01L29/51, H01L29/66, H01L29/76
Abstract: technologies for a transistor with a thin-film ferroelectric gate dielectric are disclosed. in the illustrative embodiment, a transistor has a thin layer of scandium aluminum nitride (scaln) ferroelectric gate dielectric. the channel of the transistor may be, e.g., gallium nitride or molybdenum disulfide. in one embodiment, the ferroelectric polarization changes when voltage is applied and removed from a gate electrode, facilitating switching of the transistor at a lower applied voltage. in another embodiment, the ferroelectric polarization of a gate dielectric of a transistor changes when the voltage is past a positive threshold value or a negative threshold value. such a transistor can be used as a one-transistor memory cell.
Inventor(s): Leonard P. GULER of Hillsboro OR (US) for intel corporation, Sukru YEMENICIOGLU of Portland OR (US) for intel corporation, Shengsi LIU of Portland OR (US) for intel corporation, Shao Ming KOH of Tigard OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation
IPC Code(s): H01L29/786, H01L29/06, H01L29/423, H01L29/78
Abstract: embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for techniques for creating a wall within a forkfet transistor structure, where the wall is adjacent to a first stack of nanoribbons on a first side of the wall and a second stack of nanoribbons on a second side of the wall opposite the first side of the wall. in embodiments, the wall extends beyond the top of the first stack of nanoribbons and electrically isolates a first gate metal coupled with the first stack of nanoribbons and a second gate metal coupled with the second stack of nanoribbons from each other. other embodiments may be described and/or claimed.
Inventor(s): Zhen ZHOU of Chandler AZ (US) for intel corporation, Shuhei YAMADA of Hillsboro OR (US) for intel corporation, Renzhi LIU of Portland OR (US) for intel corporation, Tae Young YANG of Portland OR (US) for intel corporation, Tolga ACIKALIN of San Jose CA (US) for intel corporation, Kenneth P. FOUST of Beaverton OR (US) for intel corporation
IPC Code(s): H01Q9/16
Abstract: a package-to-package communication system is provided including a first package having integrated on a first substrate a first antenna, a second antenna, and a first transceiver coupled to the first antenna and the second antenna. the first antenna is arranged along a first edge of the first substrate. the second antenna is arranged along a second edge of the first substrate. a second package having integrated on a second substrate a third antenna, a fourth antenna and a second transceiver coupled to the third antenna and the fourth antenna. the third antenna is arranged along a third edge of the second substrate. the fourth antenna is arranged along a fourth edge of the second substrate. the first antenna and the third antenna are configured to communicate signals of a vertical polarization. the second antenna and the fourth antenna are configured to communicate signals of a horizontal polarization.
Inventor(s): Kai Xiao of Portland OR (US) for intel corporation, Phil Geng of Washougal WA (US) for intel corporation, Carlos Alberto Lizalde Moreno of Guadalajara (MX) for intel corporation, Raul Enriquez Shibayama of Zapopan (MX) for intel corporation, Steven A. Klein of Chanlder AZ (US) for intel corporation
IPC Code(s): H01R13/6597, H01R12/71, H01R13/50, H01R13/6471, H01R33/74, H01R43/18, H01R43/20
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. an example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. the ground structure defines a plurality of third openings. the third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. a plurality of ground pins are located in respective ones of the second openings and third openings. the ground structure is to electrically couple the ground pins. a plurality of signal pins are located in respective ones of the first openings of the housing. the signal pins are electrically isolated from the ground structure.
Inventor(s): Ofir Degani of Nes-Ammin (IL) for intel corporation, Naor Roi Shay of Rehovot (IL) for intel corporation, Assaf Ben-Bassat of Haifa (IL) for intel corporation, Limor Zohar of Tel-Aviv (IL) for intel corporation, Yishai Eilat of Alonei Aba (IL) for intel corporation
IPC Code(s): H03F3/24, H03F3/45, H04B1/04
Abstract: for example, an apparatus may include an input to receive an input signal in a first voltage domain; a multi-mode power amplifier switchable between a plurality of power modes to generate an output signal based on the input signal; and an output to provide the output signal. for example, the multi-mode power amplifier may be configured to provide the output signal in the first voltage domain at a first power mode, and to provide the output signal in a second voltage domain at a second power mode. for example, a maximal voltage of the second voltage domain may be at least two times a maximal voltage of the first voltage domain.
20240113696.APPARATUS, SYSTEM AND METHOD OF PHASE SHIFTING_simplified_abstract_(intel corporation)
Inventor(s): Elan Banin of Raanana (IL) for intel corporation, Rotem Banin of Even-Yehuda (IL) for intel corporation, Ashoke Ravi of Portland OR (US) for intel corporation, Assaf Ben-Bassat of Haifa (IL) for intel corporation, Ofir Degani of Nes-Ammin (IL) for intel corporation
IPC Code(s): H03H11/16, G06F1/08
Abstract: for example, a phase shifter may include an input to receive an input clock signal having an input frequency and an input phase. for example, the phase shifter may include a quadrature phase-shift generator configured to generate a first signal and a second signal based on the input clock signal, the first and second signals having the input frequency, wherein a phase of the first signal is based on the input phase, wherein a phase of the second signal is shifted by a quadrature phase-shift relative to the phase of the first signal. for example, the phase shifter may include an output to provide an output based on the first signal and the second signal.
20240113698.IN-MEMORY ANALOG CHANNEL EQUALIZATION_simplified_abstract_(intel corporation)
Inventor(s): Richard DORRANCE of Hillsboro OR (US) for intel corporation, Peter SAGAZIO of Portland OR (US) for intel corporation, Renzhi LIU of Portland OR (US) for intel corporation, Hechen WANG of Portland OR (US) for intel corporation, Deepak DASALUKUNTE of Beaverton OR (US) for intel corporation, Brent R. CARLTON of Portland OR (US) for intel corporation
IPC Code(s): H03H17/02
Abstract: a radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.
Inventor(s): Martin Langhammer of Alderbury (GB) for intel corporation
IPC Code(s): H03H17/06, H03M1/82
Abstract: integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. an integrated circuit may include programmable logic circuitry and digital signal processor (dsp) blocks. the dsp blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. the first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. the second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.
20240113700.TECHNIQUES FOR DUTY CYCLE CORRECTION_simplified_abstract_(intel corporation)
Inventor(s): Christopher P. MOZAK of Portland OR (US) for intel corporation, Ralph S. LI of Portland OR (US) for intel corporation, Chin Wah LIM of Bayan Lepas (MY) for intel corporation, Mahmoud ELASSAL of King City OR (US) for intel corporation, Anant BALAKRISHNAN of Hillsboro OR (US) for intel corporation, Isaac ALI of Folsom CA (US) for intel corporation
IPC Code(s): H03K3/017, G06F11/16, H03K5/135, H03K5/156, H03L7/081
Abstract: examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. the reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. a magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.
Inventor(s): Hechen Wang of Portland OR (US) for intel corporation, Renzhi Liu of Portland OR (US) for intel corporation, Richard Dorrance of Hillsboro OR (US) for intel corporation, Deepak Dasalukunte of Beaverton OR (US) for intel corporation, Brent Carlton of Portland OR (US) for intel corporation
IPC Code(s): H03M1/46, G11C7/16
Abstract: systems, apparatuses and methods may provide for technology that includes a capacitor ladder, a plurality of memory cells coupled to the capacitor ladder, the plurality of memory cells to control the capacitor ladder to conduct multi-bit multiply accumulate (mac) operations during a computation phase, and a successive approximation register (sar) coupled to the capacitor ladder, the sar to control the capacitor ladder to digitize results of the multi-bit mac operations during a digitization phase.
20240113743.ACTIVE ELECTRONIC SIGNAL CROSSTALK CANCELLATION_simplified_abstract_(intel corporation)
Inventor(s): Harry Muljono of San Ramon CA (US) for intel corporation, Changhong Lin of Cupertino CA (US) for intel corporation, Mohammad Mamunur Rashid of Hillsboro OR (US) for intel corporation
IPC Code(s): H04B3/32
Abstract: an improved circuit for generating a crosstalk noise cancellation signal may be used for combining the crosstalk noise cancellation signal with a victim signal without a crosstalk cancelling capacitor. the improved crosstalk cancellation circuit may be used to provide improved tx crosstalk cancellation, and may be used to provide improved performance of increasingly higher speed memory systems regardless of memory process technology, enabling improvements to existing and future memory systems and other communication systems. the improved crosstalk cancellation circuit may include a transmission amplifier to receive a first digital signal and generate a first analog output signal, a crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal, and a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal.
Inventor(s): Juan FANG of Portland OR (US) for intel corporation, Po-Kai HUANG of San Jose CA (US) for intel corporation, Qinghua LI of San Ramon CA (US) for intel corporation, Robert STACEY of Portland OR (US) for intel corporation, Shlomi VITURI of Tel Aviv (IL) for intel corporation
IPC Code(s): H04L1/00, H04L1/06, H04L27/26
Abstract: this disclosure describes systems, methods, and devices related to enhanced low-density parity-check (ldpc) coding. a device may generate a frame comprising a data field, wherein the data field comprises a number of information bits. the device may calculate a required initial number of orthogonal frequency-division multiplexing (ofdm) symbols based on the number of information bits. the device may calculate an initial number of segments in a last ofdm symbol of the number of ofdm symbols. the device may calculate a number of data bits that can be filled within an initial number of ofdm symbols. the device may determine an ldpc codeword length based on the calculated number of data bits that can be filled. the device may cause to send the frame to one or more devices based on the ldpc codeword length.
Inventor(s): Richard DORRANCE of Hillsboro OR (US) for intel corporation, Tolga ACIKALIN of San Jose CA (US) for intel corporation, Kenneth P. FOUST of Beaverton OR (US) for intel corporation, Renzhi LIU of Portland OR (US) for intel corporation
IPC Code(s): H04L1/00, H04W64/00
Abstract: the present disclosure relates to a device which includes a processor configured to: select, using sensor data, an error correction code from two or more error correction codes, the sensor data representing a physical state of the processor and/or the device; generate channel-coded data by channel-coding input data using the selected error correction code; and provide a representation of the channel-coded data to a transmitter for wireless data transmission.
Inventor(s): Bradley Smith of Vancouver WA (US) for intel corporation
IPC Code(s): H04L9/00, G06F21/72
Abstract: an apparatus comprises processing circuitry to implement an encrypted processing unit (epu) client comprising a secure enclave, an encrypted processing unit (epu) server comprising an encrypted processing unit (epu) communicatively coupled to the secure enclave and at least one pseudo-clock generator, and a memory server communicatively coupled to the encrypted processing unit (epu) client and to the encrypted processing unit (epu) server, the memory server to manage a homomorphically encrypted memory.
20240113863.EFFICIENT IMPLEMENTATION OF ZUC AUTHENTICATION_simplified_abstract_(intel corporation)
Inventor(s): Pablo De Lara Guarch of Shannon (IE) for intel corporation, Tomasz Kantecki of Ennis (IE) for intel corporation, Krystian Matusiewicz of Gdansk (PL) for intel corporation, Wajdi Feghali of Boston MA (US) for intel corporation, Vinodh Gopal of Westborough MA (US) for intel corporation, James D. Guilford of Northborough MA (US) for intel corporation
IPC Code(s): H04L9/06, H04L9/32, H04W12/037
Abstract: methods and apparatus relating to an efficient implementation of zuc authentication are described. in one embodiment, a processor computes a tag update, based at least in part on stored data, for an authentication operation. the tag update is computed by replacing a ‘for’ loop with a carry-less multiply operation. other embodiments are also claimed and disclosed.
Inventor(s): ZACHARY PEPIN of Ann Arbor MI (US) for intel corporation, SANTOSH GHOSH of Hillsboro OR (US) for intel corporation, MANOJ SASTRY of Portland OR (US) for intel corporation
IPC Code(s): H04L9/32
Abstract: in one example an apparatus comprises processing circuitry to measure a statistical distance between a marginal distribution of a coordinate of a potential signature (z) over a first interval and a uniform distribution over the first interval and use the statistical distance to determine one or more thresholds of a rejection sampling operation in a lattice-based digital signature algorithm. other examples may be described.
Inventor(s): Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Susanne M. BALLE of Hudson NH (US) for intel corporation, Rahul KHANNA of Portland OR (US) for intel corporation, Sujoy SEN of Beaverton OR (US) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation
IPC Code(s): H04L43/08, G02B6/38, G02B6/42, G02B6/44, G06F1/18, G06F1/20, G06F3/06, G06F8/65, G06F9/30, G06F9/4401, G06F9/54, G06F12/109, G06F12/14, G06F13/16, G06F13/40, G06F15/16, G06F16/901, G08C17/02, G11C5/02, G11C7/10, G11C11/56, G11C14/00, H03M7/30, H03M7/40, H04B10/25, H04L41/14, H04L43/0817, H04L43/0876, H04L43/0894, H04L49/00, H04L49/25, H04L49/356, H04L49/45, H04L67/02, H04L67/306, H04L69/04, H04L69/329, H04Q11/00, H05K7/14
Abstract: technologies for dynamically managing resources in disaggregated accelerators include an accelerator. the accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. other embodiments are also described and claimed.
Inventor(s): Christopher Son Thach of Ambler PA (US) for intel corporation, Nathan John Heldt-Sheller of Portland OR (US) for intel corporation, Radoslaw Benedykt Szulim of Kensington MD (US) for intel corporation, Ned Smith of Beaverton OR (US) for intel corporation, Matthew David Balvin of Beaverton WA (US) for intel corporation, Callum Wilson Noble of Sunnyvale CA (US) for intel corporation, Anand Basalingappa Jyoti of Bangalore (IN) for intel corporation
IPC Code(s): H04L9/40
Abstract: methods and apparatus for identity and access management on networked machines are disclosed herein. an example non-transitory machine readable storage medium includes instructions to cause programmable circuitry to at least grant first permission to form a connection between a remote compute device and a local compute device based on a first identity of a first account, the connection to enable the first account to operate the local compute device by impersonating a second user, the second user associated with a second identity, access a request to execute a command on the remote compute device from the first account, and determine, based on the first identity of the first account and the second identity of the second user, whether second permission is to be granted to execute the command.
Inventor(s): Dieter Foedlmeier of Munich (DE) for intel corporation
IPC Code(s): H04M7/00, H04L12/12, H04L12/28
Abstract: an apparatus for providing a connection to a wide area network for voice calls includes a wide area network circuit configured to transmit voice call data packets, a phone connection circuit configured to receive a voice call signal from a phone, a processor circuit configured to generate voice call data packets based on a voice call signal received by the phone connection circuit and a power management circuit configured to switch off at least a part of the apparatus to reach a power down mode of the apparatus, if a supply voltage drops below a supply voltage threshold.
Inventor(s): Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Ronen Levi of Kiryat Ata (IL) for intel corporation, Oded Liron of Givat-Ada HA (IL) for intel corporation, Nadav Szanto of Haifa (IL) for intel corporation, Nevo Idan of Zichron Ya'akov HA (IL) for intel corporation, Chen Kojokaro of Yoqneam Illit HA (IL) for intel corporation, Nir Balaban of Kfar Netter (IL) for intel corporation
IPC Code(s): H04W28/10, H04L47/62
Abstract: a multi-link device (mld) apparatus, including at least two transmission queues and first medium access control (mac) circuitry and second mac circuitry. the first mac circuitry and the second mac circuitry can transmit data of the at least two transmission queues over respective links responsive to receiving a trigger indicating that a transmission opportunity (txop) is available on the link corresponding to the respective first mac circuitry and second mac circuitry.
20240114507.MULTI-TTI SCHEDULING OF PDSCH AND PUSCH BY DCI_simplified_abstract_(intel corporation)
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Dae Won Lee of Portland OR (US) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Gang Xiong of Beaverton OR (US) for intel corporation
IPC Code(s): H04W72/1273, H04L1/1829, H04W72/232
Abstract: a user equipment (ue) configured for operation in a fifth-generation new radio (5g nr) system may be configured for multi physical downlink shared channel (pdsch) scheduling and may decode a first downlink control information (dci) and a second dci received from a gnodeb (gnb). the first dci may schedule multiple pdschs and the second dci may schedule one or more pdschs. the ue may check the timing relations of the scheduled pdschs for validity when the first dci and the second dci end at a same symbol. when the multiple pdschs scheduled by the first dci and the one or more pdschs scheduled by the second dci are determined to have overlapping time spans, the ue may identify all the pdschs scheduled by the first dci the second dci as invalid.
Inventor(s): Alexei Davydov of Santa Clara CA (US) for intel corporation, Avik Sengupta of San Jose CA (US) for intel corporation, Bishwarup Mondal of San Ramon CA (US) for intel corporation
IPC Code(s): H04W72/542, H04L5/00, H04W72/044, H04W72/51
Abstract: disclosed embodiments are related to beam management in cellular communication networks, and in particular, provide a new tranmission (tx) beamforming indication based on the flexible tx beam-forming assignment on the corresponding reference signal configured in a transmission configuration indicator (tci) state for downlink (dl) or spatial relation information in the uplink (ul). the tx beam-forming on the reference signal of the tci state configured for the dl physical channel/reference signal can be updated based on reported tx beam in the ul or using ul measurements from sounding reference signal (srs) transmission. similarly, spatial relation information configuration used to indicate tx beam-forming in the ul, may be also updated based on the reference signal measurements in dl or by suing downlink control information (dci) based beam indication in a scheduling request indicator (sri). other embodiments may be described and/or claimed.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Tarek A. Ibrahim of Mesa AZ (US) for intel corporation, Cary Kuliasha of Mesa AZ (US) for intel corporation, Siddharth K. Alur of Chandler AZ (US) for intel corporation, Jung Kyu Han of Chandler AZ (US) for intel corporation, Beomseok Choi of Chandler AZ (US) for intel corporation, Russell K. Mortensen of Chandler AZ (US) for intel corporation, Andrew Collins of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation
IPC Code(s): H05K1/18, H01L23/498, H01L23/538, H01L23/64, H01L25/065, H05K3/00, H05K3/46
Abstract: an electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.
Inventor(s): Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Sameer Paital of Chandler AZ (US) for intel corporation
IPC Code(s): H05K1/18, H01F27/02, H01F27/29, H01F41/00, H01G2/06, H01G2/10, H01L23/00, H01L23/31, H01L23/498, H01L25/16
Abstract: an electronic device includes a substrate including a glass core layer and first contact pads on a first surface of the glass core layer; one or more discrete passive electronic components disposed on the first surface of the glass core layer, the one or more discrete passive electronic components including second contact pads on a bottom surface of the one or more discrete passive electronic components; and hybrid bonds between the first contact pads of the glass core layer and the second contact pads of the one or more discrete passive electronic components.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation
IPC Code(s): H05K3/06, H01L21/48, H01L23/498, H05K1/09
Abstract: embodiments provides for a package substrate, including: a core comprising insulative material; first conductive traces in contact with a surface of the core; and buildup layers in contact with the first conductive traces and the surface of the core, the buildup layers comprising second conductive traces in an organic dielectric material. the first conductive traces comprise at least a first metal and a second metal, the first conductive traces comprise a first region proximate to and in contact with the core and a second region distant from the core, parallel and opposite to the first region, a relative concentration of the first metal to the second metal is higher in the first region than in the second region, and the relative concentration of the first metal to the second metal between the first region and the second region varies non-uniformly.
Inventor(s): Nazila Haratipour of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Vachan Kumar of Hillsboro OR (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation, Yu-Ching Liao of Portland OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation
IPC Code(s): H01L27/11502, G11C11/22, H01L27/108, H01L29/94
Abstract: inverted pillar capacitors that have a u-shaped insulating layer are oriented with the u-shaped opening of the insulating layer opening toward the surface of the substrate on which the inverted pillar capacitors are formed. the bottom electrodes of adjacent inverted pillar capacitors are isolated from each other by the insulating layers of the adjacent electrodes and the top electrode that fills the volume between the electrodes. by avoiding the need to isolate adjacent bottom electrodes by an isolation dielectric region, inverted pillar capacitors can provide for a greater capacitor density relative to non-inverted pillar capacitors. the insulating layer in inverted pillar capacitors can comprise a ferroelectric material or an antiferroelectric material. the inverted pillar capacitor can be used in memory circuits (e.g., drams) or non-memory applications.
Inventor(s): Christopher M. Neumann of Portland OR (US) for intel corporation, Brian Doyle of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Nafees Aminul Kabir of Hillsboro OR (US) for intel corporation, Gurpreet Singh of Beaverton OR (US) for intel corporation
IPC Code(s): H01L27/11514, H01L23/522, H01L23/528, H01L27/11504
Abstract: in one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.
Inventor(s): Sourav Dutta of Hillsboro OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Uygar E. Avci of Portland OR (US) for intel corporation, Vachan Kumar of Hillsboro OR (US) for intel corporation, Christopher M. Neumann of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Brian S. Doyle of Portland OR (US) for intel corporation
IPC Code(s): H01L27/11507
Abstract: backside integrated circuit capacitor structures. in an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. the first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. the transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. the second electrode can be connected to a backside interconnect feature. in some cases, the capacitor has a height that extends through at least one backside interconnect layer. in some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. the capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.
Inventor(s): Sou-Chi Chang of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Christopher Neumann of Portland OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Brian Doyle of Portland OR (US) for intel corporation, Sarah Atanasov of Beaverton OR (US) for intel corporation, Bernal Granados Alpizar of Beaverton OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation
IPC Code(s): H01L27/11507
Abstract: apparatuses, memory systems, capacitor structures, and techniques related to anti-ferroelectric capacitors having a cerium oxide doped hafnium zirconium oxide based anti-ferroelectric are described. a capacitor includes layers of hafnium oxide, cerium oxide, and zirconium oxide between metal electrodes. the cerium of the cerium oxide provides a mid gap state to protect the hafnium zirconium oxide during operation.
Inventor(s): Christopher Neumann of Portland OR (US) for intel corporation, Cory Weinstein of Portland OR (US) for intel corporation, Nazila Haratipour of Portland OR (US) for intel corporation, Brian Doyle of Portland OR (US) for intel corporation, Sou-Chi Chang of Portland OR (US) for intel corporation, Tristan Tronic of Aloha OR (US) for intel corporation, Shriram Shivaraman of Hillsboro OR (US) for intel corporation, Uygar Avci of Portland OR (US) for intel corporation
IPC Code(s): H01L27/11507, H01L27/11514
Abstract: multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. wider portions of an inner plate may be formed in lateral recesses between insulating layers. ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. an etch-stop layer may protect the inner plate when sacrificial layers are removed. an etch-stop or interface layer may remain over the inner plate adjacent insulators.
Inventor(s): Shriram SHIVARAMAN of Hillsboro OR (US) for intel corporation, Sou-Chi CHANG of Portland OR (US) for intel corporation, Sourav DUTTA of Hillsboro OR (US) for intel corporation, Uygar E. AVCI of Portland OR (US) for intel corporation
IPC Code(s): H01L27/11507
Abstract: embodiments disclosed herein include a memory device. in an embodiment, the memory device comprises a first transistor, where the first transistor is an access transistor to write data. in an embodiment, the memory device further comprises a ferroelectric capacitor for storing data. in an embodiment, the memory device further comprises a second transistor, where the second transistor is a sense transistor to read the data stored on the ferroelectric capacitor.
- Intel Corporation
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