Intel Corporation patent applications on April 25th, 2024
Patent Applications by Intel Corporation on April 25th, 2024
Intel Corporation: 60 patent applications
Intel Corporation has applied for patents in the areas of G06T1/20 (6), G06F9/48 (5), G06N5/04 (4), H01L23/00 (4), H04W72/232 (4)
With keywords such as: device, data, based, circuitry, include, graphics, network, described, memory, and embodiments in patent application abstracts.
Patent Applications by Intel Corporation
Inventor(s): David Israel Gonzalez Aguirre of Hillsboro OR (US) for intel corporation, Javier Felip Leon of Hillsboro OR (US) for intel corporation, Javier Sebastian Turek of Beaverton OR (US) for intel corporation, Javier Perez-Ramirez of North Plains OR (US) for intel corporation, Ignacio J. Alvarez of Portland OR (US) for intel corporation
IPC Code(s): B25J9/16, B25J19/02
Abstract: systems, apparatuses and methods may provide for controlling one or more end effectors by generating a semantic labelled image based on image data, wherein the semantic labelled image is to identify a shape of an object and a semantic label of the object, associating a first set of actions with the object, and generating a plan based on an intersection of the first set of actions and a second set of actions to satisfy a command from a user through actuation of one or more end effectors, wherein the second set of actions are to be associated with the command
Inventor(s): Ngoc Duy VU of Ho Chi Minh (VN) for intel corporation, Nguyen Hoang Tan LE of Ho Chi Minh (VN) for intel corporation, Minh Anh Khoa NGUYEN of Bien Hoa (VN) for intel corporation
IPC Code(s): G01D5/353, B65B11/52, B65B57/02
Abstract: the disclosure is directed to apparatus and methods for detection of out of position (oop) components in a carrier tape forming machine. an apparatus includes cross track sensors coupled to the bus interface circuitry, the cross track sensors configured to detect oop components prior to overlaying the components on the carrier tape with cover tape, optical sensors to detect the oop components on the carrier tape after overlaying with cover tape and prior to sealing and to detect reflections from oop components seated on the carrier tape, an amplifier coupled to the optical sensors to amplify signals generated by the optical sensors and set a range for determining whether the components are oop, and relays to receive indications of detected oop components, and a controller coupled to the relays to stop the carrier tape forming machine as a function of signals received by the relays.
20240133799.WAFER-LEVEL BOND STRENGTH MEASUREMENT_simplified_abstract_(intel corporation)
Inventor(s): Khaled AHMED of San Jose CA (US) for intel corporation
IPC Code(s): G01N19/04
Abstract: this disclosure describes systems, methods, and devices related to bond strength measurement. a device may comprise a first portion of a plate connected to a movement mechanism, a second portion of the plate comprising a sticky probe and a third portion of the plate comprising a mirror with a reflective side pointing outwards. the device may further comprise an optical fiber sensor assembly comprising an optical fiber bundle for sending light through a first optical fiber and receiving light reflected from the mirror through a second optical fiber.
Inventor(s): Chia How Low of Simpang Ampat (MY) for intel corporation, Roger Cheng of Campbell CA (US) for intel corporation
IPC Code(s): G01R19/10
Abstract: embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. the leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. the circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. the comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. the circuit may include a finite state machine for managing the process.
Inventor(s): Timothy C. Johnston of Sacramento CA (US) for intel corporation, Seongtae Jeong of Portland OR (US) for intel corporation, Talha Khan of HIllsboro OR (US) for intel corporation, Anjan Raghunathan of Portland OR (US) for intel corporation
IPC Code(s): G03F1/36
Abstract: this disclosure describes systems, methods, and devices related to optical proximity corrections to an integrated circuit photomask. a method may include identifying a first contour of a first adjacent polygon of a photomask predicted for a first polygon of an integrated circuit, the first contour excluding a first corner formed by a first edge and a second edge of the first polygon; identifying a second contour of a second adjacent polygon of a photomask predicted for a second polygon of the integrated circuit, the second contour excluding a second corner formed by a third edge and a fourth edge of the second polygon; generating a fast contour prediction based on corner rounding associated with the first contour and the second contour; and generating, based on the fast contour prediction, a minimum distance between the first contour and the second contour, the minimum distance associated with the optical proximity corrections.
Inventor(s): Fabian Oboril of Karlsruhe (DE) for intel corporation, Cornelius Buerkle of Karlsruhe (DE) for intel corporation, Priyanka Mudgal of Portland OR (US) for intel corporation, Frederik Pasch of Karlsruhe (DE) for intel corporation, Syed Qutub of Munich (DE) for intel corporation, Kay-Ulrich Scholl of Malsch (DE) for intel corporation
IPC Code(s): G05B19/418, G05D1/698, G05D107/70
Abstract: a system, including: a communication interface operable to receive sensor data related to a state of an object; object state estimation processor circuitry operable to estimate, based on the sensor data, a prospective probability of a degradation of the state of the object; and cobot fleet control processor circuitry operable to generate a command for either a transport cobot operable to transport the object, or another actor, to take proactive action to mitigate the prospective probability of the degradation of the state of the object.
Inventor(s): Akhilesh S. THYAGATURU of Ruskin FL (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation, Jonathan KYLE of Atlanta GA (US) for intel corporation, Marek PIOTROWSKI of Pepowo (PL) for intel corporation
IPC Code(s): G06F1/20, G06F9/455
Abstract: a method is claimed. the method includes receiving information associated with a software application's workflow. the method includes receiving information that describes a platform's current power consumption state and current thermal state. the method includes selecting platform components to support execution of the workflow. the method includes prior to execution of the workflow upon the selected platform components, estimating a thermal impact to the platform's current thermal state as a consequence of the workflow's execution upon the selected platform components. the method includes determining a change to be made to a thermal cooling system of the platform in response to the estimating and causing the change to be made to the thermal cooling system prior to execution of at least a portion of the workflow on the platform.
Inventor(s): Tamoghna Ghosh of Bangalore (IN) for intel corporation, Susanta Bhattacharjee of Bangalore (IN) for intel corporation, Mukesh Arora of Bangalore (IN) for intel corporation
IPC Code(s): G06F1/3218
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for gradient image detection to improve power savings. an example disclosed apparatus includes programmable circuitry to at least one of instantiate or execute the machine readable instructions to identify a region in an image that satisfies a brightness threshold, define a plurality of lines in the image that extend away from the region, and determine the region corresponds to a gradient based on an analysis of pixels along different ones of the plurality of lines.
Inventor(s): Yoav Babajani of Rishon Le Zion (IL) for intel corporation, Hisham Abu Salah of Santa Clara CA (US) for intel corporation, Nadav Shulman of Tel Mond (IL) for intel corporation, Nir Misgav of Ein Hahoresh (IL) for intel corporation, Arik Gihon of Rishon Le Zion (IL) for intel corporation
IPC Code(s): G06F1/324, G06F1/3206
Abstract: embodiments herein relate to a technique to be performed by a power control unit (pcu) of an electronic device. specifically, the pcu may identify, based on a metric related to an activity level of a processor core of a multi-core processor of the electronic device, first, second, and third weights that are respectively related to first, second, and third cores of the multi-core processor. based on these weights, the pcu may identify a number of active processor cores of the multi-core processor, and alter a frequency limit of the multi-core processor accordingly. other embodiments may be described and claimed.
Inventor(s): Efraim ROTEM of Santa Clara CA (US) for intel corporation, Eliezer WEISSMANN of Haifa (IL) for intel corporation, Doron RAJWAN of Rishon Lezion (IL) for intel corporation, Yoni AIZIK of Haifa (IL) for intel corporation, Esfir NATANZON of Haifa (IL) for intel corporation, Nir ROSENZWEIG of Givat Ella (IL) for intel corporation, Nadav SHULMAN of Tel Mond (IL) for intel corporation, Bart PLACKLE of Diest (BE) for intel corporation
IPC Code(s): G06F1/329, G06F9/48
Abstract: embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. the power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. other embodiments may also be described and claimed.
Inventor(s): Ravindra A. Babu of Bangalore (IN) for intel corporation, Sashank Ms of Bangalore (IN) for intel corporation, Satyanantha R. Musunuri of Bangalore (IN) for intel corporation, Sagar C. Pawar of Bangalore (IN) for intel corporation, Kalyan K. Kaipa of Bangalore (IN) for intel corporation, Vijayakumar Balakrishnan of Bangalore (IN) for intel corporation, Sameer Kp of Bangalore (IN) for intel corporation
IPC Code(s): G06F3/01, G02B27/01, G06T1/20
Abstract: when the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. as one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. in accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. in still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
Inventor(s): Joydeep Ray of Folsom CA (US) for intel corporation, Michael Apodaca of El Dorado Hills CA (US) for intel corporation, Yoav Harel of Carmichael CA (US) for intel corporation, Guei-Yuan Lueh of San Jose CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation
IPC Code(s): G06F3/06, G06T1/60
Abstract: embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. one embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. the memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. the message specifies a base address for a surface state entry or sampler state entry. the circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.
Inventor(s): Theo Drane of El Dorado Hills CA (US) for intel corporation, Christopher Louis Poole of Folsom CA (US) for intel corporation, William Zorn of Folsom CA (US) for intel corporation, Emiliano Morini of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F7/499, G06F7/556, G06N3/0464, G06N3/08
Abstract: the techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. one embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.
20240134604.CONSTANT MODULO VIA RECIRCULANT REDUCTION_simplified_abstract_(intel corporation)
Inventor(s): Theo Drane of El Dorado Hills CA (US) for intel corporation, Christopher Louis Poole of Folsom CA (US) for intel corporation, William Zorn of Folsom CA (US) for intel corporation, Emiliano Morini of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F7/501, G06F7/505, G06F7/76
Abstract: described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. the constant modulo operation calculates a result for array of bits x, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). circuitry to perform such operation can be configured to compress the array of bits x, width n into an array of bits ywidth m. the techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.
Inventor(s): Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Zeev SPERBER of Zichron Yaakov (IL) for intel corporation, Jesus CORBAL of King City OR (US) for intel corporation, Elmoustapha OULD-AHMED-VALL of Chandler AZ (US) for intel corporation, Bret L. TOLL of Hillsboro OR (US) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Barukh ZIV of Haifa (IL) for intel corporation, Alexander HEINECKE of San Jose CA (US) for intel corporation, Milind GIRKAR of Sunnyvale CA (US) for intel corporation, Simon RUBANOVICH of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F7/485, G06F7/487, G06F7/76, G06F9/38, G06F17/16
Abstract: embodiments detailed herein relate to matrix operations. in particular, support for matrix (tile) addition, subtraction, and multiplication is described. for example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. in some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.
Inventor(s): Chinh T. CAO of Beaverton OR (US) for intel corporation, Mitchell WILLIAMS of Hillsboro OR (US) for intel corporation, Yashaswini Raghuram PRATHIVADI BHAYANKARAM of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/4401
Abstract: examples described herein relate to a network interface device. in some examples, the network interface device includes a device interface; a direct memory access (dma) circuitry; a network interface; a processor; and circuitry to boot from a network source, obtain one or more boot images from said network source, and subsequently operate as a network boot server for at least one other device.
Inventor(s): Anil Kumar of Chandler AZ (US) for intel corporation, Subba Mungara of Chandler AZ (US) for intel corporation
IPC Code(s): G06F9/48, G06F9/445, H04L47/60, H04W72/121
Abstract: technologies for scheduling time-sensitive cyclical network traffic in real-time include an internet-of-things (iot) device that includes at least one sensor for collecting sensor data. the iot device is configured to store the collected sensor data in a data buffer, allocate a packet descriptor for the sensor data, and populate the allocated packet descriptor with a cyclic data port pointer indicative of a location of the data buffer. the iot device is additionally configured to queue the packet descriptor into a media access control (mac) unit transmit direct memory access (dma) of the iot device, fetch the sensor data, and packetize the fetched data to form a network packet. further, the iot device is configured to transmit the network packet to a target computing device based on a launch time, update the launch time, and requeue the packet descriptor into the mac unit transmit dma. other embodiments are described herein.
Inventor(s): Niranjan Hasabnis of San Jose CA (US) for intel corporation, Patricia Mwove of Chandler AZ (US) for intel corporation, Ellick Chan of Portland OR (US) for intel corporation, Derssie Mebratu of Hillsboro OR (US) for intel corporation, Kshitij Doshi of Tempe AZ (US) for intel corporation, Mohammad Hossain of Santa Clara CA (US) for intel corporation, Gaurav Chaudhary of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F9/50
Abstract: adjusting workload execution based on workload similarity. a processor may determine a similarity of a first workload to a second workload. the processor may adjust execution of the first workload based on execution parameters of the second workload and the similarity of the first workload to the second workload.
Inventor(s): Rajesh Poornachandran of Portland OR (US) for intel corporation, Kaushik Balasubramanian of Beaverton OR (US) for intel corporation, Karan Puttannaiah of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/38, G06F9/48
Abstract: apparatus, articles of manufacture, and methods for managing processing units are disclosed. an example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of first operations, second operations or third operations to obtain a resource request associated with a first workload; determine if a processing resource of a programmable network device is available to perform processing for the workload; determine if a second workload can be migrated from execution on the programmable network device; based on the determination that the second workload can be migrated, cause the second workload to be migrated; and cause the first workload to execute on the processing resource of the programmable network device.
20240134719.NAMED AND CLUSTER BARRIERS_simplified_abstract_(intel corporation)
Inventor(s): Fangwen Fu of Folsom CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, John A. Wiegert of Aloha OR (US) for intel corporation, Yongsheng Liu of San Diego CA (US) for intel corporation, Ben J. Ashbaugh of Folsom CA (US) for intel corporation
IPC Code(s): G06F9/52, G06F9/48
Abstract: embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. one embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. the graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
Inventor(s): Akhilesh S. THYAGATURU of Ruskin FL (US) for intel corporation, Francesc GUIM BERNAT of Barcelona (ES) for intel corporation, Karthik KUMAR of Chandler AZ (US) for intel corporation, Adrian HOBAN of Cratloe (IE) for intel corporation, Marek PIOTROWSKI of Pepowo (PL) for intel corporation
IPC Code(s): G06F9/54, G06F1/20
Abstract: a method is described. the method includes invoking one of more functions from a set of api functions that expose the current respective cooling states of different, respective cooling devices for different components of a hardware platform. the method includes orchestrating concurrent execution of multiple applications on the hardware platform in view of the current respective cooling states. the method includes, in order to prepare the hardware platform for the concurrent execution of the multiple applications, prior to the concurrent execution of the multiple applications, sending one or more commands to the hardware platform to change a cooling state of at least one of the cooling devices.
Inventor(s): Martin-Thomas Grymel of Leixlip (IE) for intel corporation, David Bernard of Kilcullen (IE) for intel corporation, Niall Hanrahan of Galway (IE) for intel corporation, Martin Power of Dublin (IE) for intel corporation, Kevin Brady of Newry (GB) for intel corporation, Gary Baugh of Bray (IE) for intel corporation, Cormac Brick of San Francisco CA (US) for intel corporation
IPC Code(s): G06F12/02, G06N3/10
Abstract: methods, apparatus, systems and articles of manufacture are disclosed for sparse tensor storage for neural network accelerators. an example apparatus includes sparsity map generating circuitry to generate a sparsity map corresponding to a tensor, the sparsity map to indicate whether a data point of the tensor is zero, static storage controlling circuitry to divide the tensor into one or more storage elements, and a compressor to perform a first compression of the one or more storage elements to generate one or more compressed storage elements, the first compression to remove zero points of the one or more storage elements based on the sparsity map and perform a second compression of the one or more compressed storage elements, the second compression to store the one or more compressed storage elements contiguously in memory.
Inventor(s): John A. Wiegert of Aloha OR (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Biju George of Folsom CA (US) for intel corporation, Fangwen Fu of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Chunhui Mei of San Diego CA (US) for intel corporation, Changwon Rhee of Rocklin CA (US) for intel corporation
IPC Code(s): G06F12/0855
Abstract: embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. one embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. the graphics core cluster includes a plurality of graphics cores. the plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.
20240134803.HARDWARE ASSISTED MEMORY ACCESS TRACKING_simplified_abstract_(intel corporation)
Inventor(s): Sanjay Kumar of Hillsboro OR (US) for intel corporation, Phillip Lantz of Cornelius OR (US) for intel corporation, Rajesh Sankaran of Portland OR (US) for intel corporation, David Hansen of Portland OR (US) for intel corporation, Evgeny V. Voevodin of Portland OR (US) for intel corporation, Andrew Anderson of Forest Grove OR (US) for intel corporation, Lizhen You of Beijing (CN) for intel corporation, Xin Zhou of Beijing (CN) for intel corporation, Nikhil Talpallikar of Portland OR (US) for intel corporation
IPC Code(s): G06F12/1009
Abstract: an embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. other embodiments are disclosed and claimed.
20240134804.DATA TRANSFER ENCRYPTION MECHANISM_simplified_abstract_(intel corporation)
Inventor(s): Marcin Andrzej Chrapek of Zurich (CH) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation
IPC Code(s): G06F12/1027, G06F12/0882, G06F12/14
Abstract: an apparatus comprising translator circuitry to receive a plurality of physical addresses of memory data, determine an offset associated with each of the physical page addresses and apply a tweak seed to each offset to generate a plurality of tweaks.
Inventor(s): Zoran Zivkovic of Hertogenbosch (NL) for intel corporation, Jian-Guo Chen of Basking Ridge NJ (US) for intel corporation, Jay ONeill of Nesquehoning PA (US) for intel corporation, Joseph Williams of Holmdel NJ (US) for intel corporation
IPC Code(s): G06F15/80, G06F1/03
Abstract: techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (lut) in accordance with a fused single instruction stream, multiple data streams (simd) instruction. the lut may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. the index values are used to map data sample values in a data array that is to be interpolated to the segment entries. by using an iterative process of mapping data samples to valid segment entries contained in each lut portion, the architecture advantageously facilitates scaling to support larger luts and thus may be expanded to enable linear interpolation on multiple dimensions.
Inventor(s): Chendi Xue of Austin TX (US) for intel corporation, Jian Zhang of Shanghai (CN) for intel corporation, Poovaiah Manavattira Palangappa of San Jose CA (US) for intel corporation, Rita Brugarolas Brufau of Hillsboro OR (US) for intel corporation, Ke Ding of Saratoga CA (US) for intel corporation, Ravi H. Motwani of Fremont CA (US) for intel corporation, Xinyao Wang of Shanghai (CN) for intel corporation, Yu Zhou of Shanghai (CN) for intel corporation, Aasavari Dhananjay Kakne of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F16/28, G06F16/23
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to preserve privacy in a user dataset including interface circuitry, machine readable instructions, and programmable circuitry to determine a data usage type for each one of a plurality of user data features in a first dataset, classify the data usage type associated with each user data feature of the plurality of user data feature into a feature category, apply at least one feature engineering mechanism to feature categories of the data usage types of the plurality of user data features, select, based on application of feature engineering, a subset of the plurality of user data features for a feature selection training model, and output a second dataset based on the subset of the plurality of user data for the feature selection training model, the second dataset to include fewer user data features than the first dataset.
Inventor(s): George VERGIS of Portland OR (US) for intel corporation, Shigeki TOMISHIMA of Portland OR (US) for intel corporation
IPC Code(s): G06F21/56, G06F21/55
Abstract: examples include techniques for a memory module per row activate counter. the techniques include detecting a row hammer or row disturb condition for a row address at a volatile memory device if an activate count to the row address matches a threshold count. the activate count is maintained by a controller for the memory module. detection of the row hammer or row disturb condition can cause refresh management actions to mitigate the row hammer or row disturb condition.
Inventor(s): Jianyi Cheng of London (GB) for intel corporation, Samuel Coward of London (GB) for intel corporation, Lorenzo Chelini of Zurich (CH) for intel corporation, Rafael Barbalho of Orangevale CA (US) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F30/327
Abstract: described herein is a technique for automatic program code optimization for high-level synthesis. one embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.
Inventor(s): Kunapareddy CHIRANJEEVI of Hyderabad (IN) for intel corporation, Sakina PITALWALA of Bangalore (IN) for intel corporation, Karthik VARADARAJAN RAJAGOPAL of Bangalore (IN) for intel corporation
IPC Code(s): G06F30/398, G06F30/27
Abstract: this disclosure describes systems, methods, and devices related to using artificial intelligence to validate performance of integrated circuit features. a device may extract, from instruction files, microinstructions source and destination registers; generate a dependency graph including macroinstructions as nodes and dependencies between macroinstructions as edges between the nodes; generate, based on the dependency graph, a frequency distribution of instructions from trace files, performance univariate autoregressive conditionally heteroscedastic (perf uarch) stat files, and register transfer language (rtl) stat files, predictors for a machine learning model; generate, based on the perf uarch stat files and the rtl stat files, ratios of perf uarch stats to rtl stats as target stat ratios; generate, using the predictors and the machine learning model, predicted ratios of perf uarch stats to rtl stats; and generate, using greedy constrained optimization, based on the target stat ratios and the predicted ratios, recommended traces for debugging.
Inventor(s): Priyanka Mudgal of Portland OR (US) for intel corporation, Rita H. Wouhaybi of Portland OR (US) for intel corporation
IPC Code(s): G06N5/04, G06N20/00
Abstract: a first computing system includes a data store with a sensitive dataset. the first computing system uses a feature extraction tool to perform a statistical analysis of the dataset to generate feature description data to describe a set of features within the dataset. a second computing system is coupled to the first computing system and does not have access to the dataset. the second computing system uses a data synthesizer to receive the feature description data and generate a synthetic dataset that models the dataset and includes the set of features. the second computing system trains a machine learning model with the synthetic data set and provides the trained machine learning model to the first computing system for use with data from the data store as an input.
Inventor(s): Shengze Wang of Santa Clara CA (US) for intel corporation, Alexey Supikov of Santa Clara CA (US) for intel corporation, Joshua Ratcliff of San Jose CA (US) for intel corporation, Ronald Azuma of San Jose CA (US) for intel corporation
IPC Code(s): G06T1/20, G06N3/08, G06N5/04, G06T7/00
Abstract: described herein is a graphics processor comprising a system interconnect and a graphics processor cluster coupled with the system interconnect. the graphics processor cluster includes circuitry configurable to generate per-frame neural representations of a multi-view video via incremental training and transferal of weights.
Inventor(s): Fan He of Shanghai (CN) for intel corporation, Yi Qian of Shanghai (CN) for intel corporation, Ning Luo of Shanghai (CN) for intel corporation, Yunbiao Lin of Shanghai (CN) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation
IPC Code(s): G06T1/20, G06N3/092, G06T15/00
Abstract: the disclosure relates to tuning configuration parameters for graphics pipeline for better user experience. a device for graphics processing, comprising: hardware engines; a graphics pipeline at least partly implemented by the hardware engines; and a tuner, coupled to the hardware engines and the graphics pipeline, the tuner to: collect statuses of the device during runtime for a previous frame; determine configuration parameters based on the collected statuses, the configuration parameters associated with three-dimensional 3d rendering, pre-processing and video encoding of the graphics pipeline; and tune the graphics pipeline with the determined configuration parameters for processing a next frame.
Inventor(s): Pawel Tomkiewicz of Zukowo (PL) for intel corporation, Pawel Zielonka of Gdansk (PL) for intel corporation, Lukasz Braszka of Gdansk (PL) for intel corporation, Monica Lucia Martinez-Canales of Los Altos CA (US) for intel corporation
IPC Code(s): G06V40/20, G06V10/82
Abstract: an initializer for circle distribution on a 2d surface using a polar coordinate system for image compression, video compression, motion detection, and posture detection. the initializer can also be used for sphere distribution in a 3d shape. the initializer uses a mixed deterministic and iterative/stochastic approach. using the polar coordinate system for initialization enables coverage of the user space, and after parameters are initialized, the method transitions to a cartesian coordinate system. methods for using the polar system in cpu units by applying an xnor/and architecture for neural network model compression are also described. the neural network includes a perceptron for supervised learning of binary classifiers. the unit responsible for multiplication in a mac architecture can be replaced with a non-linear expressive function. thus, a neural network having a non-linear expressive perceptron (quadtron) is described for solving circle distribution and other problems.
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Ilan Ronen of Hadera (IL) for intel corporation, Kavitha Nagarajan of Bangalore KA (IN) for intel corporation, Chee Kheong Yoon of Beyan Lepas (MY) for intel corporation, Chu Aun Lim of Hillsboro OR (US) for intel corporation, Eng Huat Goh of Penang (MY) for intel corporation, Jooi Wah Wong of Bukit Mertajam (MY) for intel corporation
IPC Code(s): H01L23/367, H01L23/42, H01L23/532
Abstract: described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. in this arrangement, heat can become trapped inside the device. metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.
Inventor(s): Debendra Mallik of Chandler AZ (US) for intel corporation, Je-Young Chang of Tempe AZ (US) for intel corporation, Ram Viswanath of Phoenix AZ (US) for intel corporation, Elah Bozorg-Grayeli of Chandler AZ (US) for intel corporation, Ahmad Al Mohammad of Portland OR (US) for intel corporation
IPC Code(s): H01L23/367, H01L23/373, H01L23/495
Abstract: thermal heat spreaders and/or an ic die with solderable thermal structures may be assembled together with a solder array thermal interconnects. a thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an ic die. an ic die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. metallization on the ic die and/or heat spreader may comprise a plurality of solderable structures. a multi-chip package may include multiple ic die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the ic die or heat spreader.
Inventor(s): Bok Eng CHEAH of Gelugor (MY) for intel corporation, Seok Ling LIM of Kulim Kedah (MY) for intel corporation, Jenny Shio Yin ONG of Bayan Lepas (MY) for intel corporation, Jackson Chung Peng KONG of Tanjung Tokong (MY) for intel corporation, Kooi Chi OOI of Gelugor (MY) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/64, H01L25/00, H01L25/065, H01L25/16, H01L25/18
Abstract: a device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. the first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. the second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.
Inventor(s): Gilbert Dewey of Hillsboro OR (US) for intel corporation, Ryan Keech of Portland OR (US) for intel corporation, Cory Bomberger of Portland OR (US) for intel corporation, Cheng-Ying Huang of Hillsboro OR (US) for intel corporation, Ashish Agrawal of Hillsboro OR (US) for intel corporation, Willy Rachmady of Beaverton OR (US) for intel corporation, Anand Murthy of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/762, H01L21/768, H01L27/12
Abstract: a device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. the transistor has a body including a single crystal group iii-v or group iv semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. the transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. a source contact is coupled with the source structure and a drain contact is coupled with the drain structure. the source contact is in contact with the metallization structure in the device level.
Inventor(s): Jiun Hann SIR of Gelugor (MY) for intel corporation, Poh Boon KHOO of Perai (MY) for intel corporation, Eng Huat GOH of Ayer Itam (MY) for intel corporation, Amruthavalli Pallavi ALUR of Tempe AZ (US) for intel corporation, Debendra MALLIK of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/522, H01L23/00
Abstract: an embedded multi-die interconnect bridge (emib) is fabricated on a substrate using photolithographic techniques, and the emib is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. a low z-height of the emib, allows for useful trace and via real estate below the emib, to be employed in the package substrate.
20240136279.INTEGRATED INDUCTOR OVER TRANSISTOR LAYER_simplified_abstract_(intel corporation)
Inventor(s): Min Suet Lim of Gelugor (MY) for intel corporation, Telesphor Kamgaing of Chandler AZ (US) for intel corporation, Chee Kheong Yoon of Beyan Lepas (MY) for intel corporation, Chu Aun Lim of Hillsboro OR (US) for intel corporation, Eng Huat Goh of Penang (MY) for intel corporation, Jooi Wah Wong of Bukit Mertajam (MY) for intel corporation, Kavitha Nagarajan of Bangalore KA (IN) for intel corporation
IPC Code(s): H01L23/522, H01L49/02
Abstract: described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. power delivery to the device is on the opposite side of the semiconductor devices. the integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.
20240136292.MICROELECTRONIC STRUCTURES INCLUDING BRIDGES_simplified_abstract_(intel corporation)
Inventor(s): Omkar G. Karhade of Chandler AZ (US) for intel corporation, Edvin Cetegen of Chandler AZ (US) for intel corporation, Anurag Tripathi of Gilbert AZ (US) for intel corporation, Nitin A. Deshpande of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L23/00, H01L23/31
Abstract: disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. in some embodiments, a microelectronic structure may include a substrate and a bridge.
20240136323.MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Adel A. Elsherbini of Tempe AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation, Arun Chandrasekhar of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L25/00, H01L25/18
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
Inventor(s): Wei LI of Chandler AZ (US) for intel corporation, Edvin CETEGEN of Chandler AZ (US) for intel corporation, Nicholas S. HAEHN of Scottsdale AZ (US) for intel corporation, Ram S. VISWANATH of Phoenix AZ (US) for intel corporation, Nicholas NEAL of Gilbert AZ (US) for intel corporation, Mitul MODI of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L25/065, H01L21/48, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/498
Abstract: embodiments include semiconductor packages and a method to form such semiconductor packages. a semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. the encapsulation layer surrounds the dies. the semiconductor package also includes a plurality of dummy silicon regions on the substrate. the dummy silicon regions surround the dies and encapsulation layer. the plurality of dummy silicon regions are positioned on two or more edges of the substrate. the dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. the dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. the materials have a thermal conductivity of approximately 120 w/mk or greater, or is equal to or greater than the thermal conductivity of silicon. an underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
Inventor(s): Minki Cho of Portland OR (US) for intel corporation, Balkaran Gill of Cornelius OR (US) for intel corporation, Anisur Rahman of Beaverton OR (US) for intel corporation, Ketul B. Sutaria of Beaverton OR (US) for intel corporation
IPC Code(s): H03K17/14, G06F1/08
Abstract: this disclosure describes systems, methods, and devices related to clock gating. a device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.
Inventor(s): Hao Luo of Milpitas CA (US) for intel corporation, Somnath Kundu of Hillsboro OR (US) for intel corporation, Brent R. Carlton of Portland OR (US) for intel corporation
IPC Code(s): H03L7/099, H03L7/093
Abstract: embodiments herein relate to a sampling phase-locked loop (pll) with a compensation circuit for reducing ripples due to the use of a fractional n divider. the compensation circuit includes a ripple amplifier and a ripple divider. the ripple amplifier receives an output voltage, vmain, of a main sampling circuit of the pll and amplifies its alternating current (ac) components. the amplified output voltage is provided to a ripple integrator which samples the minimum and maximum values to provide inputs to an operational amplifier (op amp). an output of the op amp is fed back to a digital-to-analog converter (dac), which provides a corresponding compensation voltage, vcomp. vcomp is added to vmain to provide a final output control voltage, vctrl, to control a voltage-controlled oscillator (vco) of the pll.
Inventor(s): Ashoke Ravi of Portland OR (US) for intel corporation, Benjamin Jann of Hillsboro OR (US) for intel corporation, Satwik Patnaik of Portland OR (US) for intel corporation
IPC Code(s): H04B1/04, G01R27/06, H01Q3/40, H03L7/081, H03L7/24
Abstract: techniques are described related to digital radio control and operation. the various techniques described herein enable high-frequency local oscillator (lo) signal generation using injection locked cock multipliers (ilcms). the techniques also include the use of lo signals for carrier aggregation applications for phased array front ends. furthermore, the disclosed techniques include the use of array element-level control using per-chain dc-dc converters. still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (adcs) to maximize dynamic range in digital beamforming systems.
Inventor(s): Sundar Krishnamurthy of Dublin CA (US) for intel corporation, Conor O'Keeffe of Cork (IE) for intel corporation, Deepak Dasalukunte of Beaverton OR (US) for intel corporation, Finbarr O'Regan of Innishannon, Cork (IE) for intel corporation, Abhinav Vinod of San Jose CA (US) for intel corporation
IPC Code(s): H04B7/185
Abstract: an apparatus can include transceiver circuitry to receive an input signal from a target apparatus. the apparatus can further include a processing circuitry to determine position information of a source object and a target object. based on the position information, the processing circuitry can calculate a relative velocity and determine a doppler shift or carrier frequency offset in the input signal based on the relative velocity. the processing circuitry can adjust a local oscillator frequency based on a doppler measured using the position information in an initial link acquisition phase. the processing circuitry can track the doppler continuously over a range of tens of gigahertz accounting for doppler phase ambiguities, and correct for a tracked doppler shift by partially adjusting a local oscillator frequency and by correcting a residual doppler shift digitally.
Inventor(s): Claudio Da Silva of Portland OR (US) for intel corporation, Cheng Chen of Portland OR (US) for intel corporation, Bahareh Sadeghi of Portland OR (US) for intel corporation, Carlos Cordeiro of Portland OR (US) for intel corporation
IPC Code(s): H04L5/00, H04W72/044
Abstract: this disclosure describes systems, methods, and devices related to wlan sensing sounding. a device may identify a sensing null data packet (ndp) request frame received from a second device, the sensing ndp request frame associated with performing a wireless local area network channel sounding procedure; identify transmit parameters included in a transmit control field of the sensing ndp request frame; generate an ndp frame using the transmit parameters; and send, in response to the sensing ndp request frame, the ndp frame to the second device.
20240137288.DATA-CENTRIC SERVICE-BASED NETWORK ARCHITECTURE_simplified_abstract_(intel corporation)
Inventor(s): Geng Wu of Portland OR (US) for intel corporation, Leifeng Ruan of Beijing (CN) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation, Dawei Ying of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L41/16, G06F18/214, H04L47/70, H04L47/762, H04L47/783
Abstract: a data-centric network and non-real-time (rt) ran intelligence controller (ric) architecture are described. the data-centric network architecture provides data plane functions (dpfs) that serve as a shared database for control functions, user functions and management functions for data plane resources in a network. the dpfs interact with control plane functions, user plane functions, management plane functions, compute plane functions, network exposure functions, and application functions of the nr network via a service interface. the non-rt ric provides functions via rapps, manages the rapps, performs conflict mitigation and security functions, monitors machine learning (ml) performance, provides a ml model catalog that contains ml model information, provides interface terminations and stores ml data and near-rt ric related information in a database. an ml training host trains and evaluates ml models in the catalog, obtains training and testing data from the database, and retrains and updates the ml models.
20240137322.LOW-LOSS SCALABLE THROUGHPUT FOR WI-FI_simplified_abstract_(intel corporation)
Inventor(s): Laurent CARIOU of Milizac (FR) for intel corporation
IPC Code(s): H04L47/2416, H04L47/26, H04L47/62
Abstract: this disclosure describes systems, methods, and devices related to enhanced access category (ac) traffic management. a device may receive one or more frames via a network interface, wherein each of the one or more frames comprises a header. the device may analyze the header of a first frame of the one or more frames to determine prioritization based on predefined criteria. the device may assign and route the first frame to appropriate access categories (ac) and traffic identifications (tid) based on the prioritization. the device may utilize established dual queuing for each ac, comprising a deep buffer queue and a shallow buffer queue. the device may direct prioritized, low latency frames to the shallow buffer queue. the device may control traffic flow via the deep buffer queue or the shallow buffer queue based on the assigned tid for each ac.
20240137347.PRIVACY-ENHANCED SENSOR DATA EXCHANGE SYSTEM_simplified_abstract_(intel corporation)
Inventor(s): Robert Vaughn of Portland OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F21/60
Abstract: a system for privacy-enhanced sensor data exchange, including: a communication interface operable to receive sensor data related to surroundings of a sensor associated with an ego device; processor circuitry operable to: evaluate the sensor data for a privacy-sensitive attribute of the sensor data, wherein the sensor data is under privacy control of the ego device; filter the sensor data by decreasing a precision of a portion of the sensor data related to the privacy-sensitive attribute; and generate data packets based on the sensor data, formatted to enable discovery by an interested entity device.
Inventor(s): Manasi DEVAL of Portland OR (US) for intel corporation, Gregory J. BOWERS of Hillsboro OR (US) for intel corporation, Joshua A. HAY of Portland OR (US) for intel corporation, Maciej MACHNIKOWSKI of Wejherowo (PL) for intel corporation, Natalia WOCHTMAN of Tomaszow Mazowiecki (PL) for intel corporation, Joanna MUNIAK of Stroza (PL) for intel corporation
IPC Code(s): H04L69/16, H04L9/40, H04L69/12, H04L69/164, H04L69/324, H04L69/326
Abstract: embodiments include a method of opening a quick user datagram protocol (udp) internet connections (quic) socket on a computing platform, initializing quic packet processing of a hardware-based offloader, opening a quic connection to the offloader, and transmitting a first quic packet to the offloader over the quic connection. the hardware-based offloader encrypts and transmits the quic packet.
20240137685.ADAPTIVE AMBIENT LISTENING FOR AUDIO SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Oren Haggai of Kefar Sava (IL) for intel corporation, Gila Kamhi of Zichron Yaakov (IL) for intel corporation, Shmuel Markovich Golan of RAMAT HASHARON (IL) for intel corporation, Shuki Perlman of Zur-Hadassa (IL) for intel corporation, Prasanna Desai of Elfin Forest CA (US) for intel corporation
IPC Code(s): H04R1/10, G06F3/16, H04R1/08
Abstract: an apparatus can include at least one audio device configured to detect sound. the apparatus can further include processing circuitry to determine presence of a relevant sound relevant to a user of the apparatus based on a user preference or an audio device parameter. the processing circuitry can further, responsive to detecting presence of the relevant sound, provide a control command to a user listening device to command the user listening device to provide the relevant sound to a microphone of the user listening device.
Inventor(s): Qian Li of Beaverton OR (US) for intel corporation, Geng Wu of Portland OR (US) for intel corporation
IPC Code(s): H04W8/22, H04L41/342, H04W8/18, H04W72/232
Abstract: an apparatus and system are described to provide functions and procedures in a data-centric infrastructure (dci). the logical architecture includes an infrastructure orchestration function and controller. interactions between the infrastructure orchestration function and controller include a function request to form or release a logical computing node, or modify the logical computing node through addition or removal of at least one of a function-dedicated computing (fdc) function, a data plane (dp) function, or a function-dedicated network (fdn) function to the logical computing node. the controller configures the fdc/dp/fdn functions and sends a response indicating completion of operations performed by the controller that are related to the function request.
Inventor(s): Alexander Min of Portland OR (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Minyoung Park of San Ramon CA (US) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation
IPC Code(s): H04W28/02, H04W72/21, H04W72/23, H04W88/10
Abstract: this disclosure describes systems, methods, and devices related to traffic indications for multi-link devices (mlds). a device may generate a first traffic indication map (tim) with a first bitmap including a first indication that traffic is to be sent by a first access point (ap) device of the mld to a first non-ap device of a second mld using a first communication link the device may generate a second tim with a second bitmap including a second indication that no traffic is to be sent by a second ap device of the mld to a second non-ap device of the second mld using a second communication link the device may send, using the first communication link, the beacon, the beacon including the first tim and the second tim. the device may send, using the first communication link, a data frame to the first non-ap device of the second mld.
20240137952.HARQ-ACK TRANSMISSION_simplified_abstract_(intel corporation)
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Daewon Lee of Portland OR (US) for intel corporation, Alexei Davydov of Nizhny Novgorod (RU) for intel corporation, Prerana Rane of Newark CA (US) for intel corporation
IPC Code(s): H04W72/232, H04L1/1812, H04W72/1273, H04W76/28
Abstract: various embodiments herein provide techniques related to hybrid automatic repeat request acknowledgement (harq-ack) transmission in cellular networks. some embodiments may relate to harq-ack transmission in networks that use a relatively high carrier frequency (e.g., a carrier frequency above approximately 52.6 gigahertz (ghz)). some embodiments may relate to harq-ack codebook size determination for multi-physical downlink shared channel (pdsch) scheduling. some embodiments may relate to downlink control and harq-ack transmission for multi-pdsch scheduling. other embodiments may be described and/or claimed.
Inventor(s): Xiaogang Chen of Hillsboro OR (US) for intel corporation, Qinghua Li of San Ramon CA (US) for intel corporation, Feng Jiang of Sunnyvale CA (US) for intel corporation, Ziv Avital of Kadima IL (US) for intel corporation, Po-Kai Huang of San Jose CA (US) for intel corporation
IPC Code(s): H04W74/00, G06F11/10, H04W72/0446, H04W72/0453, H04W72/20, H04W72/54, H04W84/12
Abstract: an extremely high throughput (eht) station (sta) configured for trigger based (tb) transmission may decode an trigger frame (tf) received from an access point (ap). the tf may include an assignment of resources comprising one or more 20 mhz channels. the eht sta may determine which of the one or more assigned channels are available for transmission and which of the allocated channels are unavailable when the eht sta is assigned more than one 20 mhz channel. the eht sta may encode a eht tb ppdu in response to the trigger frame. the eht tb ppdu may be encoded to include an eht preamble followed by a data field. the eht preamble may be encoded to indicate channel availability. the eht sta may generate signalling to cause the eht sta to transmit the encoded eht tb ppdu only on the assigned channels that have been determined to be available.
20240137984.MECHANISM TO ENABLE ALIGNED CHANNEL ACCESS_simplified_abstract_(intel corporation)
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation, Dibakar Das of Hillsboro OR (US) for intel corporation, Dmitry Akhmetov of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W74/0816, H04W74/00, H04W74/08
Abstract: this disclosure describes systems, methods, and devices related to aligned channel access. a device may perform a first backoff countdown on a first link associated with a first station device (sta) of the device, wherein the device is a multi-link device (mld). the device may detect a second backoff countdown associated with a second sta of the mld after the first backoff countdown reaches zero. the device may determine to hold the first backoff countdown at zero based on the value of the second backoff countdown. the device may transmit in synchronization on the first link and on the second link from the first sta and the second sta respectively based on holding the first backoff countdown at zero.
Inventor(s): Po-Kai Huang of San Jose CA (US) for intel corporation, Ido Ouzieli of Tel Aviv (IL) for intel corporation, Danny Alexander of Neve Efraim Monoson (IL) for intel corporation, Daniel Bravo of Portland OR (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W76/15, H04W76/30
Abstract: this disclosure describes systems, methods, and devices related to adding or removing communication access points (aps) affiliated with an associated ap multi-link device (ap-mld). a non-ap-mld may identify a communication link between the non-ap-mld and an ap-mld, the communication link previously used by the non-ap-mld; encode a request frame comprising a multi-link reconfiguration element indicative of a request to add or remove the communication link; cause the non-ap-mld to transmit the request frame to the ap-mld; and identify a response frame received from the ap-mld, the response frame comprising the multi-link reconfiguration element and indicating whether the communication link was accepted or rejected to be added or removed.
Inventor(s): Shoghi Effendi RAJAGOPAL of Kulim (MY) for intel corporation
IPC Code(s): H05K13/08, H05K13/04
Abstract: the disclosure is directed to apparatus and methods for manufacturing including a collaborative robot, a camera operatively coupled to the collaborative robot, a memory coupled to the collaborative robot, and processing circuitry coupled to the memory, the processing circuitry configured to receive image data of at least one component intended for a printed circuit board (pcb), the image data collected by the camera operatively coupled to the collaborative robot, determine, based on the image data, a coordinate location for the component, and secure the component to the pcb using an end effector of the collaborative robot based on the received image data. in one embodiment, the collaborative robot is configured to operate alongside a human, the collaborative robot in combination with the camera configured to manufacture a computer system with the pcb.
- Intel Corporation
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- Intel corporation
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