Intel Corporation patent applications on April 18th, 2024
Patent Applications by Intel Corporation on April 18th, 2024
Intel Corporation: 71 patent applications
Intel Corporation has applied for patents in the areas of H01L23/538 (8), H01L25/18 (8), H01L23/31 (6), G06N3/08 (6), G06T1/60 (6)
With keywords such as: data, memory, based, circuitry, disclosed, device, apparatus, example, die, and circuit in patent application abstracts.
Patent Applications by Intel Corporation
20240123561.MAGNET-DRIVEN CHEMICAL-MECHANICAL POLISHING_simplified_abstract_(intel corporation)
Inventor(s): Yosef KORNBLUTH of Phoenix AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Ravindranadh Tagore ELURI of Tempe AZ (US) for intel corporation
IPC Code(s): B24B1/00, B24B37/04, B24B57/02
Abstract: this disclosure describes systems, methods, and devices related to enhanced plate polishing. a device may place a liquid between a plate and a wafer. the device may utilize a controller to vary a current flowing through an array of coils. the device may apply pressure on the plate to press against the liquid and the wafer.
20240123617.ROBOT MOVEMENT APPARATUS AND RELATED METHODS_simplified_abstract_(intel corporation)
Inventor(s): Zhongxuan Liu of Beijing (CN) for intel corporation, Zhe Weng of Beijing (CN) for intel corporation
IPC Code(s): B25J9/16
Abstract: apparatus, systems, articles of manufacture, and methods for robot movement are disclosed. an example robot movement apparatus includes a sequence generator to generate a sequence of context variable vectors and policy variable vectors. the context variable vectors are related to a movement target, and the policy variable vectors are related to a movement trajectory. the example apparatus includes a calculator to calculate an upper policy and a loss function based on the sequence. the upper policy is indicative of a robot movement, and the loss function is indicative of a degree to which a movement target is met. the example apparatus also includes a comparator to determine if the loss function satisfies a threshold and an actuator to cause the robot to perform the robot movement of the upper policy when the loss function satisfies the threshold.
20240126354.POWER BUDGETING FOR COMPUTER PERIPHERALS_simplified_abstract_(intel corporation)
Inventor(s): Kunal Shah of Bangalore (IN) for intel corporation, Prabhakar Subrahmanyam of San Jose CA (US) for intel corporation, Venkataramani Gopalakrishnan of Folsom CA (US) for intel corporation, Chuen Ming Tan of Bayan Lepas (MY) for intel corporation, Venkataramana Kotakonda of Bengaluru (IN) for intel corporation, Mitsu Shah of Bangalore (IN) for intel corporation, Kannappan Rajaraman of Bangalore (IN) for intel corporation, Yi Jen Huang of Portland OR (US) for intel corporation, Dmitriy Berchanskiy of Rocklin CA (US) for intel corporation, Swathi Nukala of Portland OR (US) for intel corporation
IPC Code(s): G06F1/26, G06F1/3203
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for power budgeting for computer peripherals with electronic devices. an example apparatus to budget power in an electronic device includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: detect a type-c event associated with a computer peripheral; write a power level offset based on an assumed power contract for the computer peripheral during debounce time; obtain an actual power contract for the computer peripheral; and adjust the power level offset based on the actual power contract.
Inventor(s): Sheshaprasad KRISHNAPURA of Cupertino CA (US) for intel corporation, Vipul LAL of Santa Clara CA (US) for intel corporation, Prasad PUSULURI of Union City CA (US) for intel corporation, Harish SRINIVASAPPA of Cupertino CA (US) for intel corporation, Yunhua WU of San Jose CA (US) for intel corporation, Shaji KOOTAAL ACHUTHAN of Danville CA (US) for intel corporation, Ty TANG of San Francisco CA (US) for intel corporation
IPC Code(s): G06F1/28
Abstract: a server system can have an electrical hierarchy that includes a transformer level, a bus segment level, a power distribution unit (pdu) level, and a server device level. the different levels can have nominal safety levels of power draw that are lower than the actual maximum power draw capability. based on monitoring power draw at multiple levels of the electrical hierarchy, a power manager can determine that it is permissible for a server device, a group of server devices, or a portion of the electrical hierarchy to exceed the nominal safety level of power draw.
20240126357.POWER OPTIMIZED BLEND_simplified_abstract_(intel corporation)
Inventor(s): Theo Drane of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F1/3234, G06T1/60
Abstract: embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. when blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.
Inventor(s): Roberto DiCecco of Toronto (CA) for intel corporation, Joshua Fender of East York (CA) for intel corporation, Shane O'Connell of Toronto (CA) for intel corporation
IPC Code(s): G06F7/485, G06F7/483, G06F7/487, G06F7/499, G06F7/544, G06F17/16
Abstract: circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. the circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. the lower precision floating-point components may be processed spatially or over multiple iterations over time.
Inventor(s): Jianyi Cheng of London (GB) for intel corporation, Samuel Coward of London (GB) for intel corporation, Lorenzo Chelini of Zurich (CH) for intel corporation, Rafael Barbalho of Orangevale CA (US) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation
IPC Code(s): G06F8/41
Abstract: described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. the tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an hls-efficient representation of program code for input into high-level synthesis tools.
Inventor(s): Fabian Oboril of Karlsruhe (DE) for intel corporation, Cornelius Buerkle of Karlsruhe (DE) for intel corporation
IPC Code(s): G06F8/41
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed that compile portable code for specific hardware are disclosed herein that include an apparatus including computer readable instructions, and programmable circuitry to at least one of execute or instantiate the instructions to receive input code, the input code written for operation on a first platform, determine a target platform, the target platform different than the first platform, and translate, via an artificial intelligence (ai) model, the input code to output code, the output code written for operation on the target platform.
Inventor(s): Dipankar DAS of Pune (IN) for intel corporation, Naveen K. MELLEMPUDI of Bangalore (IN) for intel corporation, Mrinmay DUTTA of Bangalore (IN) for intel corporation, Arun KUMAR of Bangalore (IN) for intel corporation, Dheevatsa MUDIGERE of Bangalore (IN) for intel corporation, Abhisek KUNDU of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/30, G06F7/483, G06F7/544, G06F9/38, G06N3/063
Abstract: disclosed embodiments relate to instructions for fused multiply-add (fma) operations with variable-precision inputs. in one example, a processor to execute an asymmetric fma instruction includes fetch circuitry to fetch an fma instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched fma instruction, and a single instruction multiple data (simd) execution circuit to process as many elements of the second source vector as fit into an simd lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the simd lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
Inventor(s): Alexander F. HEINECKE of San Jose CA (US) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Raanan SADE of Portland OR (US) for intel corporation, Menachem ADELMAN of Modi'in (IL) for intel corporation, Zeev SPERBER of Zichron Yackov (IL) for intel corporation, Amit GRADSTEIN of Binyamina (IL) for intel corporation, Simon RUBANOVICH of Haifa (IL) for intel corporation
IPC Code(s): G06F9/30, G06F9/38
Abstract: disclosed embodiments relate to computing dot products of nibbles in tile operands. in one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a m by n destination matrix, a first source identifier to identify a m by k first source matrix, and a second source identifier to identify a k by n second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow k times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (m,k) of the specified first source matrix by a corresponding nibble of a doubleword element (k,n) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
Inventor(s): Roman S. Dubtsov of Novosibirsk (RU) for intel corporation, Robert Valentine of Kiryat Tivon (IL) for intel corporation, Jesus Corbal of King City OR (US) for intel corporation, Milind Girkar of Sunnyvale CA (US) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Gilbert AZ (US) for intel corporation
IPC Code(s): G06F9/30
Abstract: disclosed embodiments relate to executing a vector-complex fused multiply-add instruction. in one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.
Inventor(s): Bret TOLL of Hillsboro OR (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Dan BAUM of Haifa (IL) for intel corporation, Elmoustapha OULD-AHMED-VALL of Gilbert AZ (US) for intel corporation, Raanan SADE of Portland OR (US) for intel corporation, Robert VALENTINE of Kiryat Tivon (IL) for intel corporation, Mark J. CHARNEY of Lexington MA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/30
Abstract: disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. in one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2d) matrix and a one-dimensional (1d) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2d matrix, and wherein the opcode is to indicate a move of the specified group between the 2d matrix and the 1d vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1d, to move contents of the specified 1d vector to the specified group of elements.
Inventor(s): Saurabh GAYEN of Portland OR (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Utkarsh Y. KAKAIYA of Folsom CA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30, G06F9/355
Abstract: a method of an aspect includes receiving a request for a chained accelerator operation, and configuring a chain of accelerators to perform the chained accelerator operation. this may include configuring a first accelerator to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. this may also include configuring a second accelerator to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. other apparatus, methods, systems, and machine-readable medium are disclosed.
Inventor(s): Mona MINAKSHI of Hillsboro OR (US) for intel corporation, Shamima NAJNIN of Portland OR (US) for intel corporation, Rajesh POORNACHANDRAN of PORTLAND OR (US) for intel corporation
IPC Code(s): G06F9/455
Abstract: examples relate to an apparatus, a device, a method, a computer program (or computer-readable medium) and computer system for determining presence of a noisy neighbor virtual machine. some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain performance information of one or more hardware performance measurement components of the computer system, determine, based on the performance information, a deviation of a utilization of the computer system from an expected utilization of the computer system, and determine presence of a first virtual machine having a workload that impacts a performance of one or more second virtual machines based on the deviation.
Inventor(s): Leslie Xu of Palo Alto CA (US) for intel corporation, Toby Opferman of Portland OR (US) for intel corporation, David Bradley Sheffield of Portland OR (US) for intel corporation, Mukta Singh of Morgan Hill CA (US) for intel corporation
IPC Code(s): G06F9/48
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to manage workloads for an operating system wherein it causes programmable circuitry to cause a task of a workload to be executed with a first processor core configuration; cause the task to be executed with a second processor core configuration; compare a first performance metric of the execution of the task with the first processor core configuration to a second performance metric of the execution with the second processor core configuration; and cause to be used one of the first processor core configuration or the second processor core configuration based on the comparison.
20240126613.CHAINED ACCELERATOR OPERATIONS_simplified_abstract_(intel corporation)
Inventor(s): Saurabh GAYEN of Portland OR (US) for intel corporation, Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Utkarsh Y. KAKAIYA of Folsom CA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F9/355, G06F9/38
Abstract: a chip or other apparatus of an aspect includes a first accelerator and a second accelerator. the first accelerator has support for a chained accelerator operation. the first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. the second accelerator also has support for the chained accelerator operation. the second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. other apparatus, methods, systems, and machine-readable medium are disclosed.
Inventor(s): Sundar Nadathur of Cupertino CA (US) for intel corporation, Akhilesh Thyagaturu of Tampa FL (US) for intel corporation, Jonathan L. Kyle of Atlanta GA (US) for intel corporation, Scott M. Baker of Eugene TX (US) for intel corporation, Woojoong Kim of San Jose CA (US) for intel corporation
IPC Code(s): G06F9/50, G06F11/34
Abstract: embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. in one example, environment data is received for compute devices in a distributed computing infrastructure. the environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.
Inventor(s): Zhiguo WEI of Shanghai (CN) for intel corporation, Yufu LI of Shanghai (CN) for intel corporation, Tao XU of Shanghai (CN) for intel corporation
IPC Code(s): G06F12/02
Abstract: a method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. the first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. the external device and the first circuitry are configured with a specific data pattern. a data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. the data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.
20240126691.CRYPTOGRAPHIC SEPARATION OF MMIO ON DEVICE_simplified_abstract_(intel corporation)
Inventor(s): Luis S. Kida of Beaverton OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation, Soham Jayesh Desai of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F12/06, G06F9/48, G06F12/0895, G06F12/14, G06F21/76
Abstract: technologies for cryptographic separation of mmio operations with an accelerator device include a computing device having a processor and an accelerator. the processor establishes a trusted execution environment. the accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped i/o transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. an accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped i/o transaction in response to a determination that the first authentication tag matches the second authentication tag. other embodiments are described and claimed.
Inventor(s): Yao Zu DONG of Shanghai (CN) for intel corporation, Kun TIAN of Shanghai (CN) for intel corporation, Fengguang WU of TENGCHONG (CN) for intel corporation, Jingqi LIU of Shanghai (CN) for intel corporation
IPC Code(s): G06F12/0802, G06F3/06
Abstract: various embodiments are generally directed to virtualized systems. a first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (vm) on the processor, the first guest memory page corresponding to a first byte-addressable memory. the execution of the vm and the application on the processor may be paused. the first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
Inventor(s): Mark Dechene of Hillsboro OR (US) for intel corporation, Ryan Carlson of Hillsboro OR (US) for intel corporation, Sudeepto Majumdar of Hillsboro OR (US) for intel corporation, Rafael Trapani Possignolo of Hillsboro OR (US) for intel corporation, Paula Petrica of Portland OR (US) for intel corporation, Richard Klass of Hillsboro OR (US) for intel corporation, Meenakshi Marathe of Hillsboro OR (US) for intel corporation
IPC Code(s): G06F12/1027, G06F12/0882
Abstract: techniques for slicing memory of a hardware processor core by linear address are described. in certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.
Inventor(s): Samuel Coward of London (GB) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, George A. Constantinides of Santa Clara CA (US) for intel corporation
IPC Code(s): G06F30/327
Abstract: described herein is a technique for automated detection of case-splitting opportunities in rtl. the techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. one embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.
Inventor(s): Disha Puri of Bangalore (IN) for intel corporation, Sparsa Roychowdhury of West Bengal (IN) for intel corporation, Geethabai Biradar of Karnataka (IN) for intel corporation, Theo Drane of El Dorado Hills CA (US) for intel corporation, Achutha Kiran Kumar M V of Bangalore (IN) for intel corporation
IPC Code(s): G06F30/3323, G06F30/31
Abstract: described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. these techniques enable verification engineers to expand the scope of formal verification to fix both software and rtl bugs, saving significant design time and reducing the time to market of for new products.
Inventor(s): Hamza Yous of Dublin (IE) for intel corporation, Ian Hunter of Carnaross (IE) for intel corporation, Alessandro Palla of Pisa (IT) for intel corporation
IPC Code(s): G06N3/042, G06N3/08
Abstract: a graph neural network (gnn) model is used in a scheduling process for compiling a deep neural network (dnn). the dnn, and parameter options for scheduling the dnn, are represented as a graph, and the gnn predicts a set of parameters that is expected to have a low cost. using the gnn-based model, a compiler can produce a schedule for compiling the dnn in a relatively short and predictable amount of time, even for dnns with many layers and/or many parameter options. for example, the gnn-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.
20240127061.VIDEO SUMMARIZATION USING SEMANTIC INFORMATION_simplified_abstract_(intel corporation)
Inventor(s): Myung Hwangbo of Lake Oswego OR (US) for intel corporation, Krishna Kumar Singh of Davis CA (US) for intel corporation, Teahyung Lee of Chandler AZ (US) for intel corporation, Omesh Tickoo of Portland OR (US) for intel corporation
IPC Code(s): G06N3/08, G06F18/2431, G06N3/045, G06V10/40, G06V10/764, G06V10/82, G06V20/40
Abstract: example apparatus disclosed herein are to process a first image of a first video segment from the image capture sensor with a machine learning algorithm to determine a first score for the first image, the machine learning algorithm to detect actions associated with images, the actions associated with labels. disclosed example apparatus are also to determine a second score for the first video segment based on respective first scores for corresponding images in the first video segment. disclosed example apparatus are further to determine, based on the second score, whether to retain the first video segment in the memory.
Inventor(s): Michael McCourt of San Francisco CA (US) for intel corporation, Ben Hsu of San Francisco CA (US) for intel corporation, Patrick Hayes of San Francisco CA (US) for intel corporation, Scott Clark of San Francisco CA (US) for intel corporation
IPC Code(s): G06N20/20, G06F18/21, G06F18/211, G06F18/22, G06F18/23
Abstract: disclosed examples including generating a joint model based on first and second subject models, the first and second subject models selected based on a relationship between the first and second subject models; selecting the joint model from a plurality of joint models after a determination that entropy data points of the joint model satisfy a threshold, the entropy data points based on multiple tuning trials of the joint model; and providing tuning data associated with the joint model to a tuning session of a target model.
Inventor(s): Rita H. WOUHAYBI of Portland OR (US) for intel corporation, Frederik PASCH of Karlsruhe (DE) for intel corporation, Priyanka MUDGAL of Portland OR (US) for intel corporation, Fabian OBORIL of Karlsruhe (DE) for intel corporation, Cornelius BUERKLE of Karlsruhe (DE) for intel corporation, Greeshma PISHARODY of Portland OR (US) for intel corporation
IPC Code(s): G06Q10/087, G08B21/24, H04W4/38
Abstract: an apparatus including a memory and a processor configured to: identify an item located within the environment based on sensor data, wherein the sensor data represents one or more sensor detections of the environment; determine a metric representative of a likelihood of the item becoming lost the within the environment based on information about the item; and select, based on the metric, at least one monitoring method to monitor the item within the environment from a plurality of monitoring methods.
20240127391.IMAGE PROCESSING TECHNOLOGIES_simplified_abstract_(intel corporation)
Inventor(s): Narifumi IWAMOTO of Chandler AZ (US) for intel corporation
IPC Code(s): G06T1/60, G06T1/20, G06T5/00, G06T5/20
Abstract: a system that includes at least one memory device and at least one graphics processing unit (gpu) comprising at least one processor and at least one register accessible to the at least one processor. in some examples, the at least one processor is configured to: retrieve, from the at least one memory device, pixel data of a kernel grid into the at least one register to load pixel data neighboring a target pixel region once into the one or more registers and process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the at least one register.
Inventor(s): Christopher J. HUGHES of Santa Clara CA (US) for intel corporation, Saurabh GAYEN of Portland OR (US) for intel corporation, Utkarsh Y. KAKAIYA of Folsom CA (US) for intel corporation, Alexander F. HEINECKE of San Jose CA (US) for intel corporation
IPC Code(s): G06T1/60, G06T1/20
Abstract: a chip or other apparatus of an aspect includes a first accelerator and a second accelerator. the first accelerator has support for a chained accelerator operation. the first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. the second accelerator also has support for the chained accelerator operation. the second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. other apparatus, methods, systems, and machine-readable medium are disclosed.
Inventor(s): Petrus Van Beek of Vancouver WA (US) for intel corporation, Chyuan-Tyng Wu of San Jose CA (US) for intel corporation
IPC Code(s): G06T3/4053, G06T3/4046
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to generate super-resolution upscaling. an example apparatus to process an image disclosed herein includes interface circuitry to accept input image data with a first resolution, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to upscale the input image data based on an upscale factor to generate intermediate image data with a second resolution higher than the first resolution, process the input image data with a neural network to produce neural network output data with a number of channels per pixel that is based on the upscale factor, combine the intermediate image and the neural network output data to generate output image data with the second resolution.
Inventor(s): Anbang Yao of Beijing 11 (CN) for intel corporation, Ming Lu of Beijing 11 (CN) for intel corporation, Yikai Wang of Beijing (CN) for intel corporation, Xiaoming Chen of Shanghai 31 (CN) for intel corporation, Junjie Huang of Shenzhen (CN) for intel corporation, Tao Lv of Shanghai (CN) for intel corporation, Yuanke Luo of Shanghai (CN) for intel corporation, Yi Yang of Shanghai 31 (CN) for intel corporation, Feng Chen of Shanghai 31 (CN) for intel corporation, Zhiming Wang of Shanghai 31 (CN) for intel corporation, Zhiqiao Zheng of Shenzhen (CN) for intel corporation, Shandong Wang of Beijing 11 (CN) for intel corporation
IPC Code(s): G06T5/00, G06N3/04
Abstract: embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. an embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.
Inventor(s): Attila Tamas Afra of Satu Mare (RO) for intel corporation
IPC Code(s): G06T5/92, G06F9/38, G06F17/11, G06N3/04, G06N3/08, G06T5/70
Abstract: systems and methods for tone mapping of high dynamic range (hdr) images for high-quality deep learning based processing are disclosed. in one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. the execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.
Inventor(s): Soila Kavulya of Hillsboro OR (US) for intel corporation, Rita Chattopadhyay of Chandler AZ (US) for intel corporation, Monica Lucia Martinez-Canales of Los Altos CA (US) for intel corporation
IPC Code(s): G06T7/73
Abstract: technologies for performing sensor fusion include a compute device. the compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. the detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. the circuitry is also configured to merge the detection data from the multiple sensors to define final bounding shapes for the objects.
Inventor(s): Jessica M. Christian of Redwood City CA (US) for intel corporation, Peter Graff of San Jose CA (US) for intel corporation, Crystal A. Nakatsu of San Jose CA (US) for intel corporation, Beth Ann Hockey of Sunnyvale CA (US) for intel corporation
IPC Code(s): G10L13/027, G06F40/30, G06F40/40, G10L13/08
Abstract: systems and methods are disclosed for providing non-lexical cues in synthesized speech. an example system includes processor circuitry to generate a breathing cue to enhance speech to be synthesized from text; determine a first insertion point of the breathing cue in the text, wherein the breathing cue is identified by a first tag of a markup language; generate a prosody cue to enhance speech to be synthesized from the text; determine a second insertion point of the prosody cue in the text, wherein the prosody cue is identified by a second tag of the markup language; insert the breathing cue at the first insertion point based on the first tag and the prosody cue at the second insertion point based on the second tag; and trigger a synthesis of the speech from the text, the breathing cue, and the prosody cue.
Inventor(s): Changyok Park of Portland OR (US) for intel corporation
IPC Code(s): H01G4/35, H01L23/522, H01L27/08
Abstract: disclosed herein are ic structures with one or more decoupling capacitors based on dummy tsvs provided in a support structure. an example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. the first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. the capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. the second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.
20240128138.EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING_simplified_abstract_(intel corporation)
Inventor(s): Robert L. Sankman of Phoenix AZ (US) for intel corporation, Rahul N. Manepalli of Chandler AZ (US) for intel corporation, Robert Alan May of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Bharat P. Penmecha of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L21/48, H01L23/31, H01L23/538, H01L25/065
Abstract: semiconductor packages and methods for forming semiconductor packages are disclosed. an example semiconductor package includes a substrate and a core. an insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. a via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. a bridge die is in a recess in the substrate. the bridge die is coupled with the via. an electronic component is coupled to an end of the via at a second surface of the substrate.
Inventor(s): Elizabeth NOFEN of Phoenix AZ (US) for intel corporation, Shripad GOKHALE of Gilbert AZ (US) for intel corporation, Nick ROSS of Chandler AZ (US) for intel corporation, Amram EITAN of Scottsdale AZ (US) for intel corporation, Nisha ANANTHAKRISHNAN of Chandler AZ (US) for intel corporation, Robert M. NICKERSON of Chandler AZ (US) for intel corporation, Purushotham Kaushik MUTHUR SRINATH of Chandler AZ (US) for intel corporation, Yang GUO of Chandler AZ (US) for intel corporation, John C. DECKER of Tempe AZ (US) for intel corporation, Hsin-Yu LI of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/373, H01L21/02, H01L21/56, H01L21/768, H01L23/48
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (tmis) through the first mold layer. the electronic package may further comprise a second package electrically coupled the first package by the tmis, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. in an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
Inventor(s): Ravindranath MAHAJAN of Chandler AZ (US) for intel corporation, Debendra MALLIK of Chandler AZ (US) for intel corporation, Sujit SHARAN of Chandler AZ (US) for intel corporation, Digvijay RAORANE of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/48, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/34, H01L23/538, H01L25/18
Abstract: embodiments disclosed herein include electronic packages and methods of forming such electronic packages. in an embodiment, the electronic package comprises a base substrate. the base substrate may have a plurality of through substrate vias. in an embodiment, a first die is over the base substrate. in an embodiment a first cavity is disposed into the base substrate. in an embodiment, the first cavity is at least partially within a footprint of the first die. in an embodiment, a first component is in the first cavity.
Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon C. Marin of Gilbert AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/14, H01L23/538, H01L25/065
Abstract: embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
Inventor(s): Gianni SIGNORINI of Garching bei Muenchen (DE) for intel corporation, Georg SEIDEMANN of Landshut (DE) for intel corporation, Bernd WAIDHAS of Pettendorf (DE) for intel corporation
IPC Code(s): H01L23/552, H01L21/48, H01L21/78, H01L23/31, H01L23/498
Abstract: embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. in an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. a redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. in an embodiment, an under ball metallization (ubm) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. in an embodiment, the conductive shield is electrically coupled to the ubm layer.
Inventor(s): Debendra MALLIK of Chandler AZ (US) for intel corporation, Ravindranath MAHAJAN of Chandler AZ (US) for intel corporation, Robert SANKMAN of Phoenix AZ (US) for intel corporation, Shawna LIFF of Scottsdale AZ (US) for intel corporation, Srinivas PIETAMBARAM of Chandler AZ (US) for intel corporation, Bharat PENMECHA of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/31, H01L23/538
Abstract: embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. in an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. in an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. in an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
Inventor(s): Bernd WAIDHAS of Pettendorf (DE) for intel corporation, Andreas WOLTER of Regensburg (DE) for intel corporation, Georg SEIDEMANN of Landshut (DE) for intel corporation, Thomas WAGNER of Regelsbach (DE) for intel corporation
IPC Code(s): H01L23/00, H01L23/31, H01L23/538
Abstract: embodiments disclosed herein include electronic package and methods of forming such packages. in an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. in an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. in an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. in an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.
Inventor(s): Brandon C. Marin of Gilbert AZ (US) for intel corporation, Kristof Kuwawi Darmawikarta of Chandler AZ (US) for intel corporation, Srinivas V. Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Jeremy Ecton of Gilbert AZ (US) for intel corporation, Suddhasattwa Nad of Chandler AZ (US) for intel corporation, Hiroki Tanaka of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L25/16, H01F27/02, H01F27/28, H01F27/29, H01F41/00, H01F41/04, H01L21/48, H01L23/00, H01L23/538
Abstract: embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (ic) dies. a first subset of the plurality of ic dies is directly coupled to the second side of the first substrate, a second subset of the plurality of ic dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of ic dies is embedded in the second substrate between the first substrate and the second subset of the plurality of ic dies.
Inventor(s): Denis MYASISHCHEV of Chandler AZ (US) for intel corporation, Andrew V. MAZUR of Tempe AZ (US) for intel corporation, Purushotham Kaushik MUTHUR SRINATH of Chandler AZ (US) for intel corporation, Robert M. NICKERSON of Chandler AZ (US) for intel corporation, Shripad GOKHALE of Gilbert AZ (US) for intel corporation
IPC Code(s): H01L25/18, H01L23/31, H01L25/065
Abstract: embodiments disclosed herein include electronic packages. in an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. in an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. in an embodiment, the second surface comprises a first cavity into the solder resist.
20240128255.MICROELECTRONIC ASSEMBLIES_simplified_abstract_(intel corporation)
Inventor(s): Adel A. Elsherbini of Tempe AZ (US) for intel corporation, Shawna M. Liff of Scottsdale AZ (US) for intel corporation, Johanna M. Swan of Scottsdale AZ (US) for intel corporation, Arun Chandrasekhar of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/00, H01L23/00, H01L23/498, H01L23/538, H01L25/065, H01L25/18
Abstract: microelectronic assemblies, and related devices and methods, are disclosed herein. for example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
20240128256.MULTI-CHIP PACKAGING_simplified_abstract_(intel corporation)
Inventor(s): Robert L. SANKMAN of Phoenix AZ (US) for intel corporation, Sairam AGRAHARAM of Chandler AZ (US) for intel corporation, Shengquan OU of Chandler AZ (US) for intel corporation, Thomas J. DE BONIS of Tempe AZ (US) for intel corporation, Todd SPENCER of Chandler AZ (US) for intel corporation, Yang SUN of Chandler AZ (US) for intel corporation, Guotao WANG of Chandler AZ (US) for intel corporation
IPC Code(s): H01L25/00, H01L21/56, H01L23/00, H01L23/538, H01L25/18
Abstract: an electronic device may include a first die that may include a first set of die contacts. the electronic device may include a second die that may include a second set of die contacts. the electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. the first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). the second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). the bridge interconnect may help facilitate electrical communication between the first die and the second die.
Inventor(s): Abhishek A. SHARMA of Hillsboro OR (US) for intel corporation, Van H. LE of Portland OR (US) for intel corporation, Seung Hoon SUNG of Portland OR (US) for intel corporation, Ravi PILLARISETTY of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation
IPC Code(s): H01L27/12, G05F1/56, G06F1/26, H01L21/02, H01L21/383, H01L29/24, H01L29/423, H01L29/49, H01L29/66, H01L29/786
Abstract: described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (tfts). the tfts may be formed in the back-end of an integrated circuit. additionally, the tfts may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior tfts. the one or more tfts of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. other embodiments may be described and claimed.
20240128340.INTEGRATED CIRCUIT CONTACT STRUCTURES_simplified_abstract_(intel corporation)
Inventor(s): Patrick Morrow of Portland OR (US) for intel corporation, Glenn A. Glass of Portland OR (US) for intel corporation, Anand S. Murthy of Portland OR (US) for intel corporation, Rishabh Mehandru of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L21/285, H01L29/66, H01L29/78
Abstract: disclosed herein are integrated circuit (ic) contact structures, and related devices and methods. for example, in some embodiments, an ic contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. the metal may conductively couple the semiconductor material and the electrical element.
Inventor(s): Smita Kumar of Chandler AZ (US) for intel corporation, Patrick Fleming of Laois (IE) for intel corporation
IPC Code(s): H03M7/30, H03M7/32
Abstract: a hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. the hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
Inventor(s): Alexander W. Min of Portland OR (US) for intel corporation, Thomas J. Kenney of Portland OR (US) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation, Shahrnaz Azizi of Cupertino CA (US) for intel corporation, Xiaogang Chen of Portland OR (US) for intel corporation, Robert J. Stacey of Portland OR (US) for intel corporation, Qinghua Li of San Ramon CA (US) for intel corporation
IPC Code(s): H04L1/00, H04L5/00
Abstract: for example, an apparatus may include a segment parser to parse scrambled data bits of a ppdu into a first plurality of data bits and a second plurality of data bits, the ppdu to be transmitted in an ofdm transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first ofdm mcs for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second ofdm mcs for transmission over the second channel in the second frequency band.
Inventor(s): Jason M. Fung of Portland OR (US) for intel corporation, Debayan Das of Hillsboro OR (US) for intel corporation, Sayak Ray of San Jose CA (US) for intel corporation, Rana Elnaggar of San Jose CA (US) for intel corporation, Majid Sabbagh of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L9/00
Abstract: an apparatus, system, and method for protecting a component from an observation attack are provided. a power balancing circuit configured to protect a cryptography component can include a ring oscillator electrically connected to a power supply, a time-to-digital converter (tdc) electrically connected to monitor an electrical parameter of the electrical power drawn by the cryptography component and provide data indicative of the electrical parameter, and a controller circuit configured to adjust a number of inverters of the ring oscillator drawing power from the power supply based on the data.
Inventor(s): Aiswarya M. Pious of Bangalore (IN) for intel corporation, Tao Tao of Portland OR (US) for intel corporation, Stanley Jacob Baran of Chandler AZ (US) for intel corporation, Michael Daniel Rosenzweig of Queen Creek AZ (US) for intel corporation, Chia-Hung Sophia Kuo of Folsom CA (US) for intel corporation, Rahul R of Aluva (IN) for intel corporation, Nagalakshmi S of Bengaluru (IN) for intel corporation, Praveen Kashyap Ananta Bhat of Bangalore (IN) for intel corporation, Balvinder Pal Singh of Bhilai (IN) for intel corporation, Navya P of Bangalore (IN) for intel corporation, Jason Tanner of Folsom CA (US) for intel corporation, Passant V. Karunaratne of Chandler AZ (US) for intel corporation, Venkateshan Udhayan of Portland OR (US) for intel corporation, Srikanth Potluri of Folsom CA (US) for intel corporation
IPC Code(s): H04L12/18, G06F3/04817, H04L51/04, H04L65/1069, H04L65/80
Abstract: an example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. the disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. the disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. the disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.
Inventor(s): Markus Dominik MUECK of Unterhaching (DE) for intel corporation
IPC Code(s): H04L41/0895, G06F8/71, H04L41/0806, H04L67/60
Abstract: the present disclosure is generally related to reconfigurable radio equipment (rres), and in particular to information models and protocols for the multiradio interface for rres and radio application packages (raps) used for reconfiguring rres. various extensions to the information models of the multiradio interface for rres are provided such that internal state information is included in the information models and protocols of the multiradio interface. various aspects of rap container formats and structure are also provided.
Inventor(s): Mario Jose Divan Koller of Hillsboro OR (US) for intel corporation, Francesc Guim Bernat of Barcelona (ES) for intel corporation, Manish Dhananjay Dave of Folsom CA (US) for intel corporation, Marcos Emanuel Carranza of Portland OR (US) for intel corporation, Xiangyang Zhuang of Lake Zurich IL (US) for intel corporation, Adrian Christopher Hoban of Cratloe (IE) for intel corporation
IPC Code(s): H04L43/0864, H04L43/04, H04N7/18
Abstract: an example first device disclosed includes interface circuitry, machine readable instructions, and programmable circuitry to operate based on the machine readable instructions to update configuration data based on a telemetry pattern from a second device, the second device to satisfy a neighbor condition, generate telemetry data based on the configuration data, and update the first set of data based on feedback from a recipient of the telemetry data.
20240129234.MANAGEMENT OF PACKET TRANSMISSION AND RESPONSES_simplified_abstract_(intel corporation)
Inventor(s): Hossein FARROKHBAKHT of Toronto (CA) for intel corporation, Fabrizio PETRINI of Menlo Park CA (US) for intel corporation
IPC Code(s): H04L47/11, H04L45/24, H04L47/129
Abstract: examples described herein relate to a router interface device. in some examples, the router includes an interface and circuitry. in some examples, the circuitry is to: proactively drop a packet and send a negative acknowledgement (nack) message to a sender based on lack of buffer space for a response associated with the packet and sent from a downstream network interface device that received the packet and also based on one or more of: congestion at a downstream switch or congestion at an endpoint receiver.
20240129235.MANAGEMENT OF PACKET TRANSMISSION AND RESPONSES_simplified_abstract_(intel corporation)
Inventor(s): Hossein FARROKHBAKHT of Toronto (CA) for intel corporation, Fabrizio PETRINI of Menlo Park CA (US) for intel corporation
IPC Code(s): H04L47/11, H04L45/28, H04L47/129
Abstract: examples described herein relate to a router. in some examples, the router includes an interface and circuitry coupled to the interface. in some examples, the circuitry is to determine whether an incoming packet is to reach a faulty link based on a fault location received in a received negative acknowledgment (nack) message and based on a determination that the incoming packet is to reach the faulty link, drop the packet one or multiple hops before reaching the faulty link.
20240129260.MANAGEMENT OF PACKET TRANSMISSION AND RESPONSES_simplified_abstract_(intel corporation)
Inventor(s): Hossein FARROKHBAKHT of Toronto (CA) for intel corporation, Fabrizio PETRINI of Menlo Park CA (US) for intel corporation
IPC Code(s): H04L49/90, G06F12/0802
Abstract: examples described herein relate to a router. in some examples, the router includes an interface and circuitry coupled to the interface. in some examples, the circuitry is to reserve a memory region in a buffer for a response sent by a receiver of a forwarded packet.
Inventor(s): Hong C. Li of El Dorado Hills CA (US) for intel corporation, John B. Vicente of Roseville CA (US) for intel corporation, Prashant Dewan of Hillsboro OR (US) for intel corporation
IPC Code(s): H04L9/40, G06F21/51, G06F21/53
Abstract: systems and methods may provide for receiving web content and determining a trust level associated with the web content. additionally, the web content may be mapped to an execution environment based at least in part on the trust level. in one example, the web content is stored to a trust level specific data container.
Inventor(s): Amruta Misra of Bangalore (IN) for intel corporation, Niall McDonnell of Limerick (IE) for intel corporation, Mrittika Ganguli of Tempe AZ (US) for intel corporation, Edwin Verplanke of Chandler AZ (US) for intel corporation, Stephen Palermo of Chandler AZ (US) for intel corporation, Rahul Shah of Chandler AZ (US) for intel corporation, Pushpendra Kumar of Agra (IN) for intel corporation, Vrinda Khirwadkar of Bengaluru (IN) for intel corporation, Valerie Parker of Portland OR (US) for intel corporation
IPC Code(s): H04L65/612, H04L67/02, H04L67/60
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. an example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. the example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. the example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. the example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.
Inventor(s): Tsung-Han Yang of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/176, H04N19/119, H04N19/186, H04N19/59, H04N19/70
Abstract: methods, systems, and articles are described herein related to video coding. the method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. the method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. this method comprises detecting whether or not the block has an illegal block partition. also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. further, the method includes decoding the block at least according to the second partition data.
Inventor(s): Prasoonkumar Surti of Folsom CA (US) for intel corporation, Abhishek R. Appu of El Dorado Hills CA (US) for intel corporation, Michael J. Norris of Folsom CA (US) for intel corporation, Eric G. Liskay of Folsom CA (US) for intel corporation
IPC Code(s): H04N19/436, G06T1/20, G06T5/20, G06T7/13, G06T9/00, G06T15/50, H04N19/85
Abstract: described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. in one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W12/0433, H04W12/0431, H04W12/106, H04W12/76
Abstract: an apparatus of an access point multi-link device (ap mld) is configured as a transmitted basic service set identifier (txbssid) in a wireless network including a multiple bssid (mbssid) set. the apparatus includes memory and processing circuitry coupled to the memory and configured to encode beacon frames for transmission to non-ap mlds in the wireless network. the transmission is on behalf of the txbssid and non-transmitted bssids (nontxbssids) within the mbssid set. a link recommendation frame is encoded for transmission to the non-ap mlds. the link recommendation frame includes link recommendations for the non-ap mlds associated with any aps in the mbssid set. a group management cipher suite of the txbssid is used to protect the link recommendation frame encoded for the transmission.
Inventor(s): Roya Doostnejad of Los Altos CA (US) for intel corporation, Ehud Reshef of Kiryat Tivon (IL) for intel corporation, Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W28/24, H04W28/02, H04W48/18
Abstract: for example, an access point (ap) may be configured to process network slicing information including slice identification information and service level agreement (sla) information, wherein the slice identification information is to identify one or more quality of service (qos) network slices. for example, the ap may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more qos network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more qos network slices.
Inventor(s): Markus Dominik Mueck of Unterhaching (DE) for intel corporation
IPC Code(s): H04W52/34
Abstract: techniques are disclosed for dynamically selecting out of band emission protection mechanisms to protect the usage of other frequency bands, as well as techniques for managing the scheduling and transmission of safety related messages having different communication latency requirements.
Inventor(s): Toufiqul Islam of Santa Clara CA (US) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/23, H04L5/00, H04W72/1268
Abstract: various embodiments herein provide techniques for cancelation of one or more uplink (ul) transmissions from a user equipment (ue). the ue may receive an indication of a parameter d to use for determining a start of a reference ul resource (rur). the parameter d may be ue-specific. the ue may further receive a physical downlink control channel (pdcch) that includes a downlink control information (dci) to indicate that a ul transmission is to be canceled in a rur. the ue may determine a starting symbol of the rur based on the parameter d. in embodiments, the ue may scale the parameter d based on a first subcarrier spacing (scs) associated with the parameter d and a second scs associated with the uplink transmission to obtain a scaled parameter d′ that is used to determine the starting symbol of the rur. other embodiments may be described and claimed.
Inventor(s): Gang Xiong of Portland OR (US) for intel corporation, Sergey Sosnin of Santa Clara CA (US) for intel corporation
IPC Code(s): H04W72/53, H04L1/00, H04L1/1812, H04L1/1867, H04L5/00, H04L5/10, H04L5/14, H04W56/00, H04W72/0453, H04W72/21, H04W76/27
Abstract: the present disclosure provides techniques for physical uplink shared channel (pusch) only based small data transmission, including: configuration of pre-allocated ul resource (pur) set; association of synchronization signal block (ssb) and pusch transmission; scrambling sequence generation of the pusch transmission; and a procedure for pusch only transmission carrying small data. other embodiments may be described and claimed.
Inventor(s): Alexander W. Min of Portland OR (US) for intel corporation, Arik Klein of Givaat Shmuel (IL) for intel corporation, Rath Vannithamby of Portland OR (US) for intel corporation, Ziv Avital of Kadima (IL) for intel corporation
IPC Code(s): H04W72/54, H04W72/1268
Abstract: for example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an uplink (ul) transmission from a wireless communication station (sta) in a trigger-based (tb) multi-user (mu) ul transmission to be communicated from a plurality of stas to the wireless communication device; to determine one or more transmit (tx) configuration parameters for the sta based on the expected interference-based value corresponding to the ul transmission from the sta; and to transmit a trigger frame to trigger the tb mu ul transmission, the trigger frame including the one or more tx configuration parameters to configure the ul transmission from the sta.
Inventor(s): Laurent Cariou of Milizac (FR) for intel corporation
IPC Code(s): H04W74/0816, H04W74/08
Abstract: an apparatus of an access point (ap) includes memory and processing circuitry configured to encode a trigger frame for transmission to a plurality of station devices (stas) in a wireless network. a first request frame received from a sta of the plurality of stas is decoded. the first request frame requests the ap to create a protected period for the sta when the sta is in an exposed node situation. a second request frame is encoded for transition to at least a second ap. the second request frame requests the at least second ap to establish a restricted target wake time (rtwt) for the sta. a first response frame from the at least second ap is decoded. the first response frame includes an indication of whether the rtwt is established. a second response frame is encoded for transmission to the sta. the second response frame includes the indication.
20240129977.SINGLE-RADIO MULTI-CHANNEL MEDIUM ACCESS_simplified_abstract_(intel corporation)
Inventor(s): Minyoung PARK of San Ramon CA (US) for intel corporation
IPC Code(s): H04W76/15, H04W74/0808
Abstract: this disclosure describes systems, methods, and devices related to single-radio multi-channel medium access. a device may detect that a primary channel is occupied by a transmission of a first packet by a neighboring station device in an overlapping basic service set (obss). the device may detect that a secondary channel is idle. the device may select the secondary channel for packet transmission while the primary channel is occupied by the first packet. the device may cause to send a second packet to a first station device using the secondary channel.
20240130002.TECHNOLOGIES FOR WIRELESS SENSOR NETWORKS_simplified_abstract_(intel corporation)
Inventor(s): Rahul Khanna of Portland OR (US) for intel corporation, Yi Qian of Shanghai (CN) for intel corporation, Greeshma Pisharody of Portland OR (US) for intel corporation, Raju Arvind of Bangalore (IN) for intel corporation, Jiejie Wang of Shanghai (CN) for intel corporation, Laura M. Rumbel of Portland OR (US) for intel corporation, Christopher R. Carlson of Beaverton OR (US) for intel corporation, Jennifer M. Williams of Hillsboro OR (US) for intel corporation, Prince Adu Agyeman of Hillsboro OR (US) for intel corporation
IPC Code(s): H04W76/40, H04W12/00, H04W74/00
Abstract: various technologies relating to wireless sensor networks (wsns) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.
Inventor(s): Nan Wang of Shanghai (CN) for intel corporation, Zhichao Z. Zhang of Shanghai (CN) for intel corporation, Lihui Wu of Shanghai (CN) for intel corporation, Jialiang Xu of Shanghai (CN) for intel corporation, Xiaoguo Liang of Shanghai (CN) for intel corporation, Bo Chen of Shanghai (CN) for intel corporation, Haifeng Gong of Shanghai (CN) for intel corporation
IPC Code(s): H05K7/14, H01R12/79, H05K1/02
Abstract: technologies for a flexible three-dimensional power plane in a chassis are disclosed. in one embodiment, a flexible ribbon cable is laid along a circuit board tray. the flexible ribbon cable is secured to the tray using power bosses. the power bosses connect to one or more conductors on the ribbon cable. when the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. the ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.
- Intel Corporation
- B24B1/00
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- Intel corporation
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