INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on July 4th, 2024
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION on July 4th, 2024
INTERNATIONAL BUSINESS MACHINES CORPORATION: 56 patent applications
INTERNATIONAL BUSINESS MACHINES CORPORATION has applied for patents in the areas of H01L29/06 (5), H01L29/786 (5), H01L21/8234 (4), G06F30/20 (3), H01L29/423 (3) H01L23/481 (2), G06N20/00 (2), G06F30/392 (2), G06F30/20 (2), H01P5/16 (1)
With keywords such as: data, device, semiconductor, computing, contact, user, structure, source, processor, and based in patent application abstracts.
Patent Applications by INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor(s): MATTHEW DOYLE of CHATFIELD MN (US) for international business machines corporation, JEFFREY N. JUDD of ORONOCO MN (US) for international business machines corporation, MARK J. JEANSON of ROCHESTER MN (US) for international business machines corporation, TIMOTHY J. TOFIL of ROCHESTER MN (US) for international business machines corporation, MATTHEW S. KELLY of OAKVILLE (CA) for international business machines corporation, HENRY MICHAEL NEWSHUTZ of ROCHESTER MN (US) for international business machines corporation
IPC Code(s): G01R31/28, G01R1/18, G01R33/07
CPC Code(s): G01R31/2813
Abstract: an apparatus for tin whisker isolation and detection includes a substrate having a plurality of pads for connecting to an electronic component placed on the substrate, and a shield placed on a surface of the substrate. the shield includes a plurality of cavities aligned over the plurality of pads. a plurality of sensing components each associated with one of the plurality of cavities are configured for sensing an electrically conductive growth from a corresponding pad of the plurality of pads. a plurality of circuit connections are each configured to connect one of the sensing components to detection circuitry. the detection circuitry is configured to receive one or more sensing signals from one or more of the sensing components and detect an electrically conductive growth from the corresponding pad based on the one or more sensing signals.
Inventor(s): Padmanabha Venkatagiri Seshadri of Mysore (IN) for international business machines corporation, Krishnasuri Narayanam of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: a method of replicating the volume of stateful-sets by receiving input request types for each container of a number of containers, extracting control flow paths and mapping the input request types to the extracted control flow paths. the method learns control flow path—to—volume mappings by computing, for each control flow path of the number of control flow paths, (i) one or more associations between the control flow path and one or more volumes and (ii) a nature of access of the one or more volumes. for each pod replica a dominant control flow path is computed by computing a most common control flow path and a most common volume corresponding to the most common control flow path. a request for volume management of an identified most common volume is received and the identified most common volume is replicated or a its view is created.
Inventor(s): Chao Yuan HUANG of Taipei (TW) for international business machines corporation, Yuan Jie ZHANG of Ningbo (CN) for international business machines corporation, Yu Jie GU of Beijing (CN) for international business machines corporation, Yan Xiu WU of Beijing (CN) for international business machines corporation
IPC Code(s): G06F8/34
CPC Code(s): G06F8/34
Abstract: aspects of the present disclosure relate generally to ui automation in rpa and, more particularly, to automation of contextual ui element identification by rpa robots. for example, a computer-implemented method includes: receiving, by a processor set, user interface context identification information of attributes of user interface elements in user interface code of an application; constructing, by the processor set, a model of the attributes of the user interface elements including an attribute indicating functionality of at least one user interface element; obtaining from the model of the attributes of the user interface elements an identification of the at least one user interface element referenced in an action command for performing the functionality of the at least one user interface element in robotic process automation code; and storing, by the processor set, the model of the attributes of the user interface elements in persistent storage.
Inventor(s): Lukasz G. CMIELOWSKI of Krakow (PL) for international business machines corporation, Szymon KUCHARCZYK of Krakow (PL) for international business machines corporation, Daniel Jakub RYSZKA of Krakow (PL) for international business machines corporation, Wojciech SOBALA of Krakow (PL) for international business machines corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3867
Abstract: processing within a computing environment is facilitated by determining a correlation quantity indicative of similarity between respective nodes of processing pipelines of the computing environment. consolidating of respective nodes of the process pipelines is initiated where the correlation quantity has a predefined relationship with a correlation threshold for consolidating nodes of the process pipelines within the computing environment.
Inventor(s): Wei Jun Zheng of Shanghai (CN) for international business machines corporation, Hua Hong Wang of Shanghai (CN) for international business machines corporation, Yuan Jie Song of Shanghai (CN) for international business machines corporation, Min Huang of Shanghai (CN) for international business machines corporation, Qing Lu of Shanghai (CN) for international business machines corporation, Yang Qiu of Shanghai (CN) for international business machines corporation
IPC Code(s): G06F9/451
CPC Code(s): G06F9/453
Abstract: a method for facilitating user input into a form of a graphical user interface is disclosed. in one embodiment, such a method includes receiving a form implemented on a graphical user interface. the form has multiple fields. the method automatically scans the form to determine relationships such as dependencies between the fields and automatically generates a knowledge graph that describes the fields and their relationships. the fields may be represented as nodes in the knowledge graph. the method enables a user to select a designated field in the form and display the knowledge graph to show relationships between the designated field and other fields in the form. a corresponding system and computer program product are also disclosed.
Inventor(s): Abhishek Malvankar of White Plains NY (US) for international business machines corporation, Alaa S. Youssef of Valhalla NY (US) for international business machines corporation, Chen Wang of Chappaqua NY (US) for international business machines corporation, Diana Jeanne Arroyo of Austin TX (US) for international business machines corporation, Marquita May Ellis of White Plains NY (US) for international business machines corporation
IPC Code(s): G06F9/50, G06N3/092
CPC Code(s): G06F9/505
Abstract: a method and system allocating computing resources according to a trained machine learning model that includes receiving a request to accommodate a particular workload that involves a first threshold amount of computing resources implemented by at least one computing cluster. an identified a set of computing clusters, that have computing resources available for allocating from the identified set of computing clusters to the at least one computing cluster to satisfy the first threshold amount of computing resources, is received from a database. a trained deep-reinforcement learning model is applied to generate a policy for allocating the available computing resources from the identified set of computing clusters to the at least one computing cluster. it is verified that the generated policy satisfies a threshold according to one or more predetermined criteria. the computing resources are allocated from the set of computing clusters to the at least one computing cluster.
Inventor(s): Sarbajit K. Rakshit of KOLKATA (IN) for international business machines corporation, Akash U. Dhoot of Pune (IN) for international business machines corporation, Shailendra Moyal of Pune (IN) for international business machines corporation
IPC Code(s): G06F11/07, G05B15/02, G06F30/20
CPC Code(s): G06F11/0703
Abstract: a processor may receive object data associated with an object in an environment. the processor may generate one or more simulations associated with the object using the object data. the processor may analyze the one or more simulations to identify one or more potential issues associated with the object. the processor may deploy the one or more smart devices to the object to capture issue data associated the one or more potential issues.
Inventor(s): Derek E. WILLIAMS of Round Rock TX (US) for international business machines corporation, Florian Auernhammer of Rueschlikon (CH) for international business machines corporation
IPC Code(s): G06F12/1045, G06F12/0831, G06F13/16
CPC Code(s): G06F12/1045
Abstract: a data processing system includes a master and multiple snoopers communicatively coupled to a system fabric for communicating requests, where the master and snoopers are distributed among a plurality of nodes. the data processing system maintains logical partition (lpar) information for each of a plurality of lpars, wherein the lpar information indicates, for each of the plurality of lpars, which of the plurality of nodes includes at least one snooper among the plurality of snoopers that holds an address translation entry for that lpar. based on the lpar information, the master selects a broadcast scope of a multicast request on the system fabric, where the broadcast scope includes fewer than all of the plurality of nodes. the master repetitively issues, on the system fabric, the multicast request utilizing the selected broadcast scope until the multicast request is successfully received by all of the plurality of snoopers within the broadcast scope.
Inventor(s): Sasikanth Eda of Vijayawada (IN) for international business machines corporation, Karthik Iyer of Bangalore (IN) for international business machines corporation, Sandeep Ramesh Patil of Pune (IN) for international business machines corporation, Muthu Annamalai Muthiah of Chennai (IN) for international business machines corporation
IPC Code(s): G06F16/182, G06F9/50
CPC Code(s): G06F16/1827
Abstract: a computer-implemented method for provisioning cloud computing clusters includes receiving a request to create a cloud computing cluster, the cloud computing cluster comprising a clustered filesystem and a requested number of processing nodes and attached storage devices associated with the cloud computing cluster and initiating an initialization process for a single processing node and a corresponding attached storage device responsive to receiving the request to create the cloud computing cluster. the method may also include, previous to completion of the initialization process, requesting and receiving an ip address for the single processing node and a device id for the corresponding attached storage device from one or more cloud infrastructure controllers and configuring the clustered filesystem and a corresponding wan cache using the received ip address and the received device id. a system and computer program product corresponding to the above method are also disclosed herein.
Inventor(s): Sheng Yan Sun of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Xiao Xiao Chen of Beijing (CN) for international business machines corporation, Ying Zhang of Beijing (CN) for international business machines corporation
IPC Code(s): G06F16/22, G06F16/242, G06F16/2457, G06F18/2323
CPC Code(s): G06F16/22
Abstract: a computer-implemented method, including receiving, by a processor set, a query including a query string for a system catalog; identifying, by the processor set, a default index structure of the system catalog; executing, by the processor set, the query based on the default index structure of each index in the system catalog; ranking, by the processor set, a performance of each execution of the query by each index; mapping, by the processor set, a query pattern to a corresponding index of the system catalog; selecting, by the processor set, the index to perform the query using a machine learning (ml) model trained with a knowledge base that includes the ranking and the mapping; executing, by the processor set, the query on the selected index; and in response to executing the query on the selected index, returning, by the processor set, a result of the query.
Inventor(s): Felix Beier of Haigerloch (DE) for international business machines corporation, Knut Stolze of Hummelshain (DE) for international business machines corporation, Reinhold Geiselhart of Rottenburg-Ergenzingen (DE) for international business machines corporation, Luis Eduardo Oliveira Lizardo of Böblingen (DE) for international business machines corporation
IPC Code(s): G06F16/22
CPC Code(s): G06F16/2282
Abstract: the present disclosure relates to a method for storing a table in a database system. the table comprises a first set of one or more columns of first data type and a second set of one or more columns of second data type. the method comprises: storing the first set of columns and a set of locator columns in a first regular table space. the second set of columns may be stored in a second large object table space. in case a first recorded data volume is higher than or equal to a second recorded data volume, data of the second large object table space may be assigned to a first large object table space. in case the first recorded data volume is smaller than the second recorded data volume, data of the first regular table space may be assigned to a second regular table space.
Inventor(s): Rajesh Bordawekar of Westchester NY (US) for international business machines corporation, Jose Luis Pontes Correia Neves of Poughkeepsie NY (US) for international business machines corporation, Apoorva Nitsure of Pittsburgh PA (US) for international business machines corporation
IPC Code(s): G06F16/242, G06F16/22, G06F16/2453
CPC Code(s): G06F16/243
Abstract: a count of unique values in a column of a database table is determined. a query on the database table is performed, wherein a technique for performing the query is selected based on the count of unique values.
Inventor(s): Sarika Sinha of BANGALORE (IN) for international business machines corporation, Siddharth Saraya of NEW DELHI (IN) for international business machines corporation, Pradeep Kumar Rathi of Bangalore (IN) for international business machines corporation
IPC Code(s): G06F16/2457, G06F9/54, G06F16/248
CPC Code(s): G06F16/24578
Abstract: an example operation may include one or more of receiving, via a user interface, a feature set, querying a repository of application programming interfaces (apis) to identify an api in the repository that corresponds to the received feature set based on a comparison of features in the feature set to features of the api stored in the repository, identifying criteria of the identified api that is published in the repository, and displaying a recommendation with the identified api including the identified criteria of the identified api via the user interface.
Inventor(s): Shubham Jain of Elmsford NY (US) for international business machines corporation, Geoffrey Burr of Cupertino CA (US) for international business machines corporation, HsinYu Tsai of Cupertino CA (US) for international business machines corporation, Yasuteru Kohda of Yamato-shi (JP) for international business machines corporation, Milos Stanisavljevic of Langnau am Albis (CH) for international business machines corporation
IPC Code(s): G06F17/16, G06F7/50, G06F7/523, G06F7/535, G06F7/556
CPC Code(s): G06F17/16
Abstract: a compute engine is configured to perform self-attention computations by delaying performance of a division operation of a softmax computation, the performance including iteratively computing a first matrix multiplication of a given row vector of a first matrix and each column vector of a second matrix while determining a first scalar element representing a maximum value of the iterative first matrix multiplications; iteratively subtracting a corresponding determined first scaler element from a result of each computed first matrix multiplication and computing an elementwise exponential function based on a result of the subtraction operation to generate a plurality of elements of a given row vector of a fourth matrix; iteratively computing a second matrix multiplication of a given row vector of the fourth matrix and each column vector of a third matrix while summing the given row vectors of the fourth matrix; and computing a row vector of an output matrix.
Inventor(s): Li Juan Gao of Xi'an (CN) for international business machines corporation, Yong Wang of Xi'an (CN) for international business machines corporation, Zhong Fang Yuan of Xi'an (CN) for international business machines corporation, Liu Yao He of Beijing (CN) for international business machines corporation, Yuan Yuan Ding of Shanghai (CN) for international business machines corporation, Yu Pan of Shanghai (CN) for international business machines corporation, Jing Zhang of Shanghai (CN) for international business machines corporation
IPC Code(s): G06F18/214, G06F18/22, G06N3/094
CPC Code(s): G06F18/214
Abstract: prompt learning is performed, using a prompt encoder, on an input data set to generate a revised text pattern. the revised text pattern is processed, using a text generative adversarial network, based on an existing data set to generate a fused data set and a machine learning system is updated with the fused data set.
Inventor(s): Holly Wright of Studio Village (AU) for international business machines corporation, Jared Ryan Hayward of Southport (AU) for international business machines corporation, Wayne Francis Tackabury of West Tisbury MA (US) for international business machines corporation, Melanie Hanson of Ashmore (AU) for international business machines corporation, Yair Allouche of Dvira (IL) for international business machines corporation
IPC Code(s): G06F18/231
CPC Code(s): G06F18/231
Abstract: an example method includes initiating training of an hierarchical clustering algorithm using training data. the method further includes determining a first factor, the first factor being a number of analyzed nodes compared to a number of discovered nodes. the method further includes determining a second factor, the second factor being a first time elapsed compared to a first typical training duration for environments with a data set size substantially similar to a data set size of the training data. the method further includes determining a third factor, the third factor being a second time elapsed compared to a second typical training duration for environments with a data having a uniformity substantially similar to a uniformity of the training data. the method further includes estimating a progress of the training of the hierarchical clustering algorithm based at least in part on the first factor, the second factor, and the third factor.
Inventor(s): Su Liu of Austin TX (US) for international business machines corporation, Luis Osvaldo Pizana of Austin TX (US) for international business machines corporation, Boyi Tzen of Taipei City (TW) for international business machines corporation, Saritha Arunkumar of Woodley (GB) for international business machines corporation
IPC Code(s): G06F21/56, G06F8/41
CPC Code(s): G06F21/563
Abstract: a computer implemented method compiles a source code. a computer system loads the source code into a first memory. the computer system loads a rendered source code into a second memory, wherein the rendered source code is a rendered version of the source code. the computer system determines whether a difference is present between the source code in the first memory and the rendered source code in the second memory. the computer system performs a set of actions in compiling the source code in response to determining that the difference between the source code and the rendered source code is present.
Inventor(s): Nikki Elyse Robinson of Davidsonville MD (US) for international business machines corporation, Leigh Chase of Andover (GB) for international business machines corporation, Efran Himel of Cambridge MA (US) for international business machines corporation, Carter Hottovy of Austin TX (US) for international business machines corporation
IPC Code(s): G06F21/57, G06F16/23, G06F21/62
CPC Code(s): G06F21/577
Abstract: an embodiment includes invoking a search of vulnerability chain data of a local database using a database query to obtain a search result, where the database query is based on a description string associated with a new vulnerability, and where the search result comprises a plurality of linked vulnerabilities that collectively form a vulnerability chain. the embodiment also includes identifying a vulnerability characteristic of a linked vulnerability of the plurality of linked vulnerabilities in the vulnerability chain. the embodiment also includes generating, as a new vulnerability chain, a modified version of the vulnerability chain by appending the new vulnerability to the vulnerability chain. the embodiment also includes assigning an updated vulnerability score to the new vulnerability based at least in part on the identified vulnerability characteristic of the linked vulnerability. the embodiment also includes updating the local database to include the new vulnerability chain and the updated vulnerability score.
Inventor(s): Melba Lopez Broz of Cedar Park TX (US) for international business machines corporation, Dimple Gajra of Austin TX (US) for international business machines corporation, Nikki Elyse Robinson of Davidsonville MD (US) for international business machines corporation, Raul Infantes of Miami FL (US) for international business machines corporation
IPC Code(s): G06F30/20, G06F21/57
CPC Code(s): G06F30/20
Abstract: using a system risk evaluation model, system data is evaluated, the evaluating identifying a system risk, the system risk comprising a risk associated with a system of an organization being audited, the system risk evaluation model computing a system risk score using a first plurality of weights assigned to data attributes of the system data. using a role risk evaluation model, role data is evaluated, the evaluating identifying a role risk, the role risk comprising a risk associated with a role in the organization being audited, the role risk evaluation model comprising computing a role risk score using a second plurality of weights assigned to data attributes of the role data. using an audit repository, an audit customized to the system risk and the role risk is generated. using a result of the audit, a configuration of the system is caused to be adjusted.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06F30/20
CPC Code(s): G06F30/20
Abstract: a processor may receive an entity data having one or more data components associated with an entity. the processor may analyze the entity data. the processor may identify, responsive to analyzing the entity data, one or more restricted data components and one or more unrestricted data components from the one or more data components. the processor may generate at least one federated digital twin model of the entity using the one or more restricted data components. the processor may generate a non-federated digital twin of the entity using the one or more unrestricted data components. the processor may aggregate the at least one federated digital twin and the non-federated digital twin to form a hybrid digital twin.
Inventor(s): David Wolpert of Poughkeepsie NY (US) for international business machines corporation, Leon Sigal of Monsey NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Biswanath Senapati of Mechanicville NY (US) for international business machines corporation, Lawrence A. Clevenger of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): G06F30/392, G06F30/33, G06F30/394
CPC Code(s): G06F30/392
Abstract: a semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. the first and second backside metal rails bound a first circuit row. the structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. the second and third backside metal rails bound a second circuit row. the structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. the structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.
Inventor(s): DONGBING SHAO of Briarcliff Manor NY (US) for international business machines corporation, April Carniol of Ossining NY (US) for international business machines corporation, Jyotica Patel of Yonkers NY (US) for international business machines corporation, Michael Justin Beckley of New York NY (US) for international business machines corporation, James R. Brancaccio of Florida NY (US) for international business machines corporation
IPC Code(s): G06F30/392, G06F30/398
CPC Code(s): G06F30/392
Abstract: an integrated circuit design is partitioned into a plurality of cells and a plurality of images of a stitched chip design are generated based on the plurality of cells. at least one of the images is wrapped with a chrome border and a blading outline to generate a mask design. design information is extracted from the mask design and the stitched chip design. a scanner job file for fabricating the integrated circuit design is generated based on the extracted design information and the fabrication of an integrated circuit using the scanner job file is facilitated.
Inventor(s): TAKUMA UDAGAWA of Yamatoshi (JP) for international business machines corporation, HIROSHI KANAYAMA of Yokohama-shi (JP) for international business machines corporation, Issei Yoshida of Tokyo (JP) for international business machines corporation
IPC Code(s): G06F40/284, G06F40/30
CPC Code(s): G06F40/284
Abstract: a probability of a given token of a given text being a beginning of sentence is computed and a probability of the given token of the given text being an end of sentence is computed. the probability of the token being the beginning of sentence and the probability of the token being the end of sentence are combined to determine a probability of a given span of text being a sentential unit. the given span of text is identified as most probably being the sentential unit.
Inventor(s): Zhong Fang Yuan of Xi'an (CN) for international business machines corporation, Tong Liu of Xi'an (CN) for international business machines corporation, Si Tong Zhao of Beijing (CN) for international business machines corporation, Xiang Yu Yang of Xi'an (CN) for international business machines corporation, Ziqiumin Wang of Shanghai (CN) for international business machines corporation
IPC Code(s): G06F40/30, G06F18/214, G06F18/2413, G06V30/19
CPC Code(s): G06F40/30
Abstract: information extraction and image restructuring includes generating semantic vectors to encode portions of text extracted from a document. for each semantic vector a semantic similarity between a schema key and other text encoded therein is determined based on their respective positions within the document. an enhanced nlp model is created using the semantic vectors, each labeled according to the semantic similarity. the text, including schema key, are re-encoded as a key and candidate vectors. key-value pairs are generated by matching the key vector with a predetermined number of candidate vectors. the enhanced nlp model, using prompt learning, is repurposed to perform a next-sentence prediction that predicts which of the candidate vectors is logically related to the schema key. based on the next-sentence prediction, the discrete portion of text identified as the schema key and portion of text determined to be logically related thereto are output.
Inventor(s): Zhengliang Xue of Yorktown Heights NY (US) for international business machines corporation, Mo Liu of Albany CA (US) for international business machines corporation, Shivaram Subramanian of Frisco TX (US) for international business machines corporation, Markus Ettl of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: a total demand model can be trained, by machine learning and using historical data. the total demand model can be configured to process current data and output first data indicating a predicted future total demand for a product. a target demand model can be trained. the target demand model can be configured to process the current data and, based on processing the current data, output a plurality of class demand models. each class demand model can be configured to predict demand, for each of a plurality of future time periods, for a plurality of classes of the product. the class demand models configured to optimize, for each of the plurality of future time periods, a respective set of optimal prices for the respective classes of the product that maximizes total expected revenue for the product over the plurality of classes of the product.
Inventor(s): Xuan-Hong DANG of Chappaqua NY (US) for international business machines corporation, Petros ZERFOS of New York NY (US) for international business machines corporation, Syed Yousaf SHAH of Yorktown Heights NY (US) for international business machines corporation, Anil R. SHANKAR of New York NY (US) for international business machines corporation
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: a prediction system may obtain data, via a network, from devices and process the data, using a first machine learning, to identify a plurality of signals. the prediction system may train a second machine learning model to analyze the plurality of signals to forecast a first forecasted time series and evaluate a first performance of the first forecasted time series. the prediction system may determine that the first performance does not satisfy a performance threshold and may refine the plurality of signals to obtain a refined plurality of signals. the prediction system may train a third machine learning model to analyze the refined plurality of signals to forecast a second forecasted time series and evaluate a second performance of the second forecasted time series. the prediction system may use the refined plurality of signals and the third machine learning model to predict a performance of a third forecasted time series.
Inventor(s): Ismael Faro Sertage of Chappaqua NY (US) for international business machines corporation, Juan Cruz Benito of Salamanca (ES) for international business machines corporation, Francisco Jose Martin Fernandez of Ridgefield CT (US) for international business machines corporation
IPC Code(s): G06N20/20, G06N3/045
CPC Code(s): G06N20/20
Abstract: methods and systems use one or more machine learning models to automatically generate three-dimensional sound. a multimodal content item is accessed by a computing device. three-dimensional sound is automatically generated by the computing device using the one or more machine learning models based on the multimodal content item.
Inventor(s): Madhusmita Patil of Hyderabad (IN) for international business machines corporation, Vivek Warrier of Bengaluru (IN) for international business machines corporation, Renjith Koorumullamkattil Mathew of Bangalore (IN) for international business machines corporation, Parag Sanjay Mhatre of Pen (IN) for international business machines corporation, Karanam Rakesh of Eluru (IN) for international business machines corporation, Ayushi Jain of Indore (IN) for international business machines corporation, Swati Anand of Noida (IN) for international business machines corporation
IPC Code(s): G06Q10/063, G06F40/40
CPC Code(s): G06Q10/063
Abstract: a computer hardware system includes a machine learning engine and a hardware processor configured to perform the following executable operations. text of a role description of a role having a role title is preprocessed. competencies are inferred from the role description; using the machine learning engine. competencies are identified from titles in a talent framework being similar to the title using the machine learning engine. the competencies are aggregated into an aggregation of competencies. the competencies in the aggregation are ordered based upon aggregated similarity scores. a proficiency level associated with each of the competencies in the aggregation is adjusted based upon band level and competency type. a plurality of competencies are selected. the role is augmented with metadata that includes the selected plurality of competencies and proficiency levels associated therewith.
Inventor(s): Pranshu Tiwari of Delhi (IN) for international business machines corporation, Swarnalata Patel of Morrisville NC (US) for international business machines corporation, Saurabh Trehan of Gurgaon (IN) for international business machines corporation, Harish Bharti of Pune (IN) for international business machines corporation
IPC Code(s): G06Q10/0631, G06F18/23213
CPC Code(s): G06Q10/06313
Abstract: an end-to-end framework that provides for pair programming can determine a project intent. programming requirements needed to fulfill the project intent can be identified. the programming requirements can be reduced into lower dimensions. the reduced programming requirements can be clustered into clusters. a common theme can be identified in each of the clusters. from at least one of the clusters having a common theme corresponding to the programming requirements, feasible pairs of developers can be selected. at least one optimal pair of developers can be determined among the feasible pairs using an optimization algorithm that optimizes the project intent.
Inventor(s): Sarath Sreedharan of Tempe AZ (US) for international business machines corporation, Tathagata Chakraborti of Cambridge MA (US) for international business machines corporation, Vinod Muthusamy of Austin TX (US) for international business machines corporation, Yara Rizk of Cambridge MA (US) for international business machines corporation, Yasaman Khazaeni of Needham MA (US) for international business machines corporation
IPC Code(s): G06Q10/0633, G06F9/48
CPC Code(s): G06Q10/0633
Abstract: embodiments of the invention are directed to a programmable computer system that includes a processor system operable to perform processor system operations. the processor system operations include using a workflow composer to perform an automated workflow composition process that generates a composed workflow that is operable to, when executed by a host device, satisfy a target logical goal. performing the automated workflow composition process includes using a workflow-metric model to control the automated workflow composition process such that the composed workflow is operable to, when executed by the host device, satisfy the target logical goal in a manner that optimizes a target metric goal. the target metric goal quantifies a performance feature of the composed workflow.
Inventor(s): Tushar Agrawal of West Fargo ND (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation
IPC Code(s): G06Q30/0601, G06T19/00
CPC Code(s): G06Q30/0643
Abstract: an approached is disclosed that selectively replaces physical objects with virtual objects viewable in augmented reality. selective replacement is based on user location and corresponding preferences mapped to location clusters. ai systems learn user preferences for location clusters and derive object preferences for users depending on location. preferences and priorities for objects within each location cluster are derived using location data, purchase histories, iot data, social media, communication data and other data sources. ai systems implement algorithms to predict levels of engagement between users and objects of a particular location cluster and as objects around the user are predicted to be uninteresting to the user, uninteresting objects may be replaced within ar environments using ar image overlay techniques with new objects having an interest rating above a threshold level. replacement objects are purchasable through the ar interface, whereby users select objects to purchase and initiate delivery.
Inventor(s): Timothy J. Chainer of Putnam Valley NY (US) for international business machines corporation, Todd Edward Takken of Brewster NY (US) for international business machines corporation, Joshua M. Rubin of Albany NY (US) for international business machines corporation, Arvind Kumar of Chappaqua NY (US) for international business machines corporation
IPC Code(s): H01L23/46, H01L23/367, H01L23/433, H01L25/065
CPC Code(s): H01L23/46
Abstract: an exemplary apparatus includes a substrate; a plurality of chips mounted onto the substrate; a plurality of cold plates corresponding to the plurality of chips; means for pressing each of the cold plates toward a corresponding one of the chips; means for delivering coolant flow to the cold plates; and means for adjusting the cooling power of the plurality of cold plates, responsive to at least one sensed parameter of the plurality of chips.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L29/06, H01L29/417, H01L29/786
CPC Code(s): H01L23/481
Abstract: embodiments are disclosed for a semiconductor device and a method for fabrication. the device includes a first gate, having a top fet that is disposed above a bottom fet, and in electrical contact with a top source/drain epitaxial (s/d epi) and a back end of line (beol) interconnect. additionally, the device includes the bottom fet. the bottom fet is in electrical contact with a bottom s/d epi. further, a shallow backside contact is in electrical contact with the bottom s/d epi. additionally, the device includes a deep via that is in electrical contact with the beol interconnect and the shallow backside contact. the deep via and the shallow backside contact provide a conductive path between the beol interconnect and the bottom s/d epi.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Julien Frougier of ALBANY NY (US) for international business machines corporation, Nicolas Jean Loubet of GUILDERLAND NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L29/06, H01L29/417, H01L29/66, H01L29/786
CPC Code(s): H01L23/481
Abstract: back side and front side contact structures adjoin source/drain regions and facilitate contact spacing in a semiconductor structure. a bottom dielectric isolation layer structure including horizontal and vertical portions is located between the gate regions and a back side interlevel dielectric layer. the vertical portions of the bottom dielectric layer further adjoin the back side contact structure. source/drain regions of transistors within the semiconductor structure are grown uniformly over semiconductor surfaces. the source/drain regions and the gate regions are protected during back side processing.
Inventor(s): Takeshi Nogami of Schenectady NY (US) for international business machines corporation, SON NGUYEN of Schenectady NY (US) for international business machines corporation, Cornelius Brown Peethala of Slingerlands NY (US) for international business machines corporation
IPC Code(s): H01L23/532, H01L21/768
CPC Code(s): H01L23/53266
Abstract: an integrated circuit configuration with graphene coated metal interconnect structures and airgap structures between the graphene coated metal interconnect structures and method for fabrication of the integrated circuit configuration may be provided. the structure may include a metal interconnect structure in contact with an electrode upon a substrate fabricated through subtractive metal reactive ion etching. the metal interconnect structure may have a thin coating of hydrophobic graphene surrounding the exterior of the metal interconnect structure to prevent oxidation of the metal interconnect and to prevent parasitic capacitance. the structure may further include one or more air gap structures formed upon the substrate and in between the graphene coated metal interconnect structures and capped with a dielectric layer.
Inventor(s): Roy R. Yu of Poughkeepsie NY (US) for international business machines corporation, Katsuyuki Sakuma of Fishkill NY (US) for international business machines corporation
IPC Code(s): H01L23/00, H01L21/683, H01L21/78
CPC Code(s): H01L24/80
Abstract: an apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on an upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bond head configured to accommodate a second semiconductor substrate on a downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bond head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. the heatable bond head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substrate and the second stack of semiconductor materials against the collet. the heatable bond head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Daniel Schmidt of Niskayuna NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/423, H01L29/786
CPC Code(s): H01L27/0922
Abstract: a hybrid semiconductor structure, a system, and a method of forming a hybrid semiconductor structure. the hybrid semiconductor structure may include a pfet region, where the pfet region includes a first channel in a fin shape; an nfet region, where the nfet region includes a second channel, the second channel including a nanosheet; and an isolation bar separating the pfet region from the nfet region. the system may include a hybrid semiconductor structure including a pfet region; an nfet region; an isolation bar separating the pfet and nfet region; and a gate surrounding a plurality of sidewalls of the first channel and the second channel. the method may include forming an isolation bar between a first channel material in an nfet region and a second channel material in a pfet region; forming the second channel material into a fin shape; and forming the first channel material into stacked nanosheets.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Oleg Gluschenkov of Tannersville NY (US) for international business machines corporation
IPC Code(s): H01L27/12, H01L21/822
CPC Code(s): H01L27/12
Abstract: a semiconductor device includes a first field effect transistor (fet) and a second fet arranged under the first fet to form a stack on the frontside of a wafer. a middle of line (mol) contact has a first end connected to a source or drain of the first fet, and a second end connected to a first voltage node. a direct backside contact is connected to a backside power delivery network, the direct backside contact has a first end connected to a source or drain of the second fet, and a second end connected to a second voltage node. a back end of line (beol) layer has an input signal line and an output signal line. a gate region connects the mol contact to the input signal line at the beol. the first fet and the second fet are connected through the mol contact to the output signal line.
Inventor(s): Oscar van der Straten of Guilderland Center NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Koichi Motoyama of Clifton Park NY (US) for international business machines corporation
IPC Code(s): H01L27/12
CPC Code(s): H01L27/1248
Abstract: embodiments are disclosed for a semiconductor device array and a method for fabricating the semiconductor device array. the semiconductor device array includes a backside power distribution network (bspdn), a buried power rail (bpr) in electrical contact with the bspdn, a device layer, and a backside-connecting via. the device layer includes a first transistor, a second transistor, a first spacer, and a second spacer. further, the first transistor is in electrical contact with the first spacer. additionally, the second transistor is in electrical contact with the second spacer. also, the first transistor neighbors the second transistor. further, the backside-connecting via is in electrical contact with the first transistor, the bpr, the first spacer, and the second spacer.
Inventor(s): Joshua M. Rubin of Albany NY (US) for international business machines corporation, Christopher J. Penny of Saratoga Springs NY (US) for international business machines corporation
IPC Code(s): H01L21/02
CPC Code(s): H01L28/92
Abstract: a multi-stack metal-insulator-metal (mim) structure includes a plurality of conductive plates including a first group comprising odd-numbered ones of the plates and a second group comprising even-numbered ones of the plates. all of the conductive plates are of an identical material. a plurality of insulators are between the plurality of conductive plates; and a first plate via contact extends vertically through the plurality of conductive plates and the plurality of insulators. the first plate via contact is electrically coupled to the first group of conductive plates and electrically isolated from the second group of conductive plates. the second plate via contact extends vertically through the plurality of conductive plates and the plurality of insulators. the second plate via contact is electrically coupled to the second group of conductive plates and electrically isolated from the first group of conductive plates.
Inventor(s): Sagarika Mukesh of Albany NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation, Tsung-Sheng Kang of Ballston Lake NY (US) for international business machines corporation
IPC Code(s): H01L29/06, H01L21/8234, H01L29/20, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0649
Abstract: one or more embodiments includes a semiconductor device. the semiconductor device includes: a first gate-all-around (gaa) field-effect transistor (fet) disposed on a silicon layer; and a second gaa fet disposed on the silicon layer adjacent to the first gaa fet. the semiconductor device also includes: an isolation layer disposed within the silicon layer between a first bottom dielectric isolation (bdi) layer of the first gaa fet and a second bdi layer of the second gaa fet; and a gate structure disposed proximate the first gaa fet and the second gaa fet, wherein at least one of a cap or a sidewall spacer isolates the gate structure from the silicon layer.
Inventor(s): Eric Miller of Albany NY (US) for international business machines corporation, Nelson Felix of Slingerlands NY (US) for international business machines corporation, Andrew Herbert Simon of FISHKILL NY (US) for international business machines corporation
IPC Code(s): H01L29/417, H01L21/768, H01L21/8234, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device includes first and second nanosheet stacks above an upper surface of a semiconductor substrate, a first source/drain on an end of the first nanosheet stack, and a second source/drain on an end of the second nanosheet stack. a first gate stack wraps around individual channels of the first nanosheet stack and a second gate stack wraps around individual channels the second nanosheet stack. an interlayer dielectric covers the first and second nanosheet stacks, the first and second source/drains, and the first and second gate stacks. the semiconductor device further includes a first source/drain contact that contacts the first source/drain and a second source/drain contact that contacts the second source/drain. the first and second source/drain contacts extend continuously from the first and second source/drains, respectively, to an upper surface of the interlayer dielectric.
Inventor(s): Asaf Tzadok of New Castle NY (US) for international business machines corporation, Alberto Valdes Garcia of Chappaqua NY (US) for international business machines corporation, John Francis Bulzacchelli of Somers NY (US) for international business machines corporation
IPC Code(s): H03L7/191, G06F17/15, H03L7/107
CPC Code(s): H03L7/191
Abstract: a first 1:n frequency divider has an input configured to be coupled to one of two signals and a second 1:n frequency divider has an input configured to be coupled to another of the two signals. a mixer includes two inputs, where each input is coupled to an output of one of the first and second 1:n frequency dividers. a low-pass filter has an input coupled to an output of the mixer and an analog-to-digital converter (adc) has an input coupled to an output of the low-pass filter. a data collection and analysis block repeatedly changes a phase of an output of the first 1:n divider, collects a set of digitized data generated by the adc, and estimates the phase difference between the two signals based on the set of digitized data.
Inventor(s): Martin Cochet of South Salem NY (US) for international business machines corporation, John Francis Bulzacchelli of Somers NY (US) for international business machines corporation
IPC Code(s): H03M1/10
CPC Code(s): H03M1/1014
Abstract: a system and method for compensating segmented dac intrinsic inl by adjusting the relative strength of dac thermometer segments. in the method, the strength of each thermometer segment is adjusted sequentially to reduce inl to 0 at one point on each thermometer code range. the strength of the binary section is also adjusted to further reduce inl while conserving output amplitude. the system includes a calibration circuit that senses the dac differential output and compares it to an ideal output generated from the same dac via dithering between 0 and a maximum code. the compensation scheme only performs a specific type of dac compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. the method can also be applied to calibrate a full thermometer dac.
Inventor(s): Martin Cochet of South Salem NY (US) for international business machines corporation, John Francis Bulzacchelli of Somers NY (US) for international business machines corporation, Timothy O. Dickson of Ridgefield CT (US) for international business machines corporation
IPC Code(s): H03M1/82, H03M1/10
CPC Code(s): H03M1/825
Abstract: a system and method for calibrating a digital-to-analog converter (dac) device. the method includes tuning a second subset of one or more dac segments to match a strength of a first subset of dac segments wherein the first subset of dac segments is of a strength nominally equal to that of the second subset of dac segments. the process is iterative, and the second subset of dac segments is associated with lesser significant bits than the bits associated with the first subset of dac segments. the process is repeated to tune each of successive second subsets of dac segments to corresponding successive first subsets of dac segments in top-down order from a segment associated with a msb input to a segment associated with a lsb input. in each case the first subset of dac segments is of a strength nominally equal to that of the second subset of dac segments.
Inventor(s): Akram Bitar of Haifa (IL) for international business machines corporation, Dov Murik of Haifa (IL) for international business machines corporation, Ehud Aharoni of Kfar Saba (IL) for international business machines corporation, Nir Drucker of Zichron Yaakov (IL) for international business machines corporation, OMRI SOCEANU of Haifa (IL) for international business machines corporation, Ronen Levy of Haifa (IL) for international business machines corporation
IPC Code(s): H04L9/00, H04L9/08, H04L9/14
CPC Code(s): H04L9/008
Abstract: a computer-implemented method comprising: generating, from a key-seed associated with a user, a set of homomorphic encryption (he) keys associated with an he scheme; receiving, from a key management system (kms) associated with said he scheme, an encrypted version of said key-seed; storing said encrypted version of said key-seed, and said set of he keys, in an untrusted storage location; and at a decryption stage, decrypting an encrypted computation result generated using said he scheme, by: (i) recalling, from said untrusted storage location, said encrypted version of said key-seed, (ii) providing said encrypted version of said key-seed to said kms, to obtain a decrypted version of said key-seed s associated with said user, (iii) generating, from said received decrypted version of said key-seed, a secret he key associated with said he scheme, and (iv) using said secret he key to decrypt said encrypted computation result.
Inventor(s): RAJAT RAO of BANGALORE (IN) for international business machines corporation
IPC Code(s): H04L9/06, H04L1/00
CPC Code(s): H04L9/0618
Abstract: a method for encrypting frames transmitted from a transmitter to a receiver includes transmitting unencrypted training frames of a set from the transmitter to the receiver, with each training frame scrambled prior to transmission on an output of a counter of the transmitter and a training frame, where each scrambled training frame is unencrypted. a control signal from the transmitter is transmitted from the transmitter to the receiver after the training frames. after transmitting the control signal to the receiver, a frame modified to include error detection information is encrypted using an encrypted counter block that is generated from the output of the counter. the encrypted modified frame is transmitted from the transmitter to the receiver.
Inventor(s): Gandhi Sivakumar of Bentleigh (AU) for international business machines corporation, Kushal S. Patel of Pune (IN) for international business machines corporation, Sarvesh S. Patel of Pune (IN) for international business machines corporation
IPC Code(s): H04L67/5682
CPC Code(s): H04L67/5682
Abstract: embodiments relate improved traffic management in edge caching. responsive to an emergency trigger, an edge device receives a map from a target system, the edge device including a cache having a plurality of blocks, where the map is representative of content in a data volume of the target system. the edge device determines at least one block of the plurality of blocks in the cache different from the content in the data volume based on the map. the edge device sends the at least one block in the cache to the target system, responsive to the emergency trigger.
Inventor(s): Steve RIDGILL of Raleigh NC (US) for international business machines corporation, Randy A. RENDAHL of Raleigh NC (US) for international business machines corporation, Aditya MANDHARE of Durham NC (US) for international business machines corporation, Zach TAYLOR of Fuquay Varina NC (US) for international business machines corporation
IPC Code(s): H04N21/4545, G06F3/14
CPC Code(s): H04N21/45455
Abstract: masking sensitive information in a shared display is described herein. for example, system level detection of a shared display condition and application specific privacy settings are used to identify sensitive information and obscures a visual presentation of the contents on a shared system display.
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Raghuveer Prasad Nagar of Kota (IN) for international business machines corporation, Sidharth Ullal of Chennai (IN) for international business machines corporation, Reji Jose of Bangalore (IN) for international business machines corporation
IPC Code(s): H04N21/4627, H04N7/01, H04N21/2543
CPC Code(s): H04N21/4627
Abstract: a computer-implemented method dynamically transforming digital content includes receiving a request for digital content from a digital device, receiving configuration information associated with the digital device, account constraints associated with a user of the digital device, and information on resources available on the digital device, identifying an alternative output event based on the configuration information, the account constraints, and the information on resources available on the digital device, and executing the alternative output event. a system and computer program product corresponding to the above method are also disclosed herein.
Inventor(s): Yang LIU of Zhong Xin City (CN) for international business machines corporation, Yuan Yuan DING of Shanghai (CN) for international business machines corporation, Yi Chen ZHONG of Shanghai (CN) for international business machines corporation, Hong Bing ZHANG of Beijing (CN) for international business machines corporation
IPC Code(s): H04N21/81, G06Q30/0251, G06T7/70, G06T17/00
CPC Code(s): H04N21/812
Abstract: embodiments of the present disclosure provide enhanced systems and methods for generating enhanced dynamic video placement advertisements with scene recognition and user portrait analysis. one disclosed method comprises analyzing a video to identify a scene from video content based on a scene model pool providing scene recognition for the video. user portrait analysis for users enables generating customized advertising content for a given user based on user interests or preference. video content can be customized for specific users with scene recognition enabling effective video advertising and improved user enjoyment.
Inventor(s): John S. Werner of Fishkill NY (US) for international business machines corporation, Piyush Kashyap of Highland NY (US) for international business machines corporation, Samuel R. Connor of Apex NC (US) for international business machines corporation, Yuanchen Hu of Wappingers Falls NY (US) for international business machines corporation, Kevin O'Connell of Rochester MN (US) for international business machines corporation
IPC Code(s): H05K1/02
CPC Code(s): H05K1/023
Abstract: an apparatus for providing a safety and emc compliant heat sink. the apparatus includes a heat sink configured to be attached to an internal power plane of a printed circuit board (pcb). the heat sink includes a plurality of fins extending outward from the heat sink. the apparatus further includes a compliance cage configured to be connected to a ground portion of the pcb, the compliance cage surrounding at least a portion of the heat sink. at least one capacitor plate contacting at least a portion of the compliance cage and extending inwards towards the heat sink and interleaving with the plurality of fins is present. dielectric spacers are provided to fill a portion of the space between the capacitor plates and the heat sink fins.
Inventor(s): Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation, Alexander Reznicek of Troy NY (US) for international business machines corporation
IPC Code(s): H10B53/30, G11C11/22, H01L21/28
CPC Code(s): H10B53/30
Abstract: a ferroelectric random access memory cell comprises a ferroelectric active layer comprising a first ferroelectric material and at least one second ferroelectric material in contact with the first ferroelectric material; a first electrode in contact with the first ferroelectric material and the second ferroelectric material, the first electrode being positioned at a first side of the ferroelectric active layer; and a second electrode in contact with the first ferroelectric material and the second ferroelectric material, the second ferroelectric material being positioned at a second opposing side of the ferroelectric active layer. the first ferroelectric material has a threshold electric field for an intrinsic electric polarization reversal that is higher than the threshold electric field for an intrinsic electric polarization reversal of the second ferroelectric material. the first ferroelectric material at least partially surrounds the second ferroelectric material.
Inventor(s): Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Michael Rizzolo of Delmar NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H10N50/01, G11C11/16, H10B61/00, H10N50/10, H10N50/80
CPC Code(s): H10N50/01
Abstract: a semiconductor device includes a magneto-resistive random access memory (mram) formed at a backside of a wafer. a self-aligning micro stud and silicide layer can directly electrically connect the mram to a source/drain (s/d) of a transistor in the mram region of the semiconductor device.
Inventor(s): Chanro Park of Clifton Park NY (US) for international business machines corporation, Kangguo Cheng of Schenectady NY (US) for international business machines corporation, Youngseok Kim of Upper Saddle River NJ (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Takashi Ando of Eastchester NY (US) for international business machines corporation
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/023
Abstract: a method of manufacturing a resistive random access memory (rram) cell includes forming an electrode, and forming an insulator on the electrode, the insulator having a pore and an insulator surface. the method also includes forming a dielectric material on the insulator and the electrode using an atomic layer deposition (ald) process such that a seam exists in the dielectric material, and forming another electrode on the dielectric material.
INTERNATIONAL BUSINESS MACHINES CORPORATION patent applications on July 4th, 2024
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- G01R31/28
- G01R1/18
- G01R33/07
- CPC G01R31/2813
- International business machines corporation
- G06F3/06
- CPC G06F3/0611
- G06F8/34
- CPC G06F8/34
- G06F9/38
- G06F9/30
- CPC G06F9/3867
- G06F9/451
- CPC G06F9/453
- G06F9/50
- G06N3/092
- CPC G06F9/505
- G06F11/07
- G05B15/02
- G06F30/20
- CPC G06F11/0703
- G06F12/1045
- G06F12/0831
- G06F13/16
- CPC G06F12/1045
- G06F16/182
- CPC G06F16/1827
- G06F16/22
- G06F16/242
- G06F16/2457
- G06F18/2323
- CPC G06F16/22
- CPC G06F16/2282
- G06F16/2453
- CPC G06F16/243
- G06F9/54
- G06F16/248
- CPC G06F16/24578
- G06F17/16
- G06F7/50
- G06F7/523
- G06F7/535
- G06F7/556
- CPC G06F17/16
- G06F18/214
- G06F18/22
- G06N3/094
- CPC G06F18/214
- G06F18/231
- CPC G06F18/231
- G06F21/56
- G06F8/41
- CPC G06F21/563
- G06F21/57
- G06F16/23
- G06F21/62
- CPC G06F21/577
- CPC G06F30/20
- G06F30/392
- G06F30/33
- G06F30/394
- CPC G06F30/392
- G06F30/398
- G06F40/284
- G06F40/30
- CPC G06F40/284
- G06F18/2413
- G06V30/19
- CPC G06F40/30
- G06N20/00
- CPC G06N20/00
- G06N20/20
- G06N3/045
- CPC G06N20/20
- G06Q10/063
- G06F40/40
- CPC G06Q10/063
- G06Q10/0631
- G06F18/23213
- CPC G06Q10/06313
- G06Q10/0633
- G06F9/48
- CPC G06Q10/0633
- G06Q30/0601
- G06T19/00
- CPC G06Q30/0643
- H01L23/46
- H01L23/367
- H01L23/433
- H01L25/065
- CPC H01L23/46
- H01L23/48
- H01L21/8234
- H01L29/06
- H01L29/417
- H01L29/786
- CPC H01L23/481
- H01L29/66
- H01L23/532
- H01L21/768
- CPC H01L23/53266
- H01L23/00
- H01L21/683
- H01L21/78
- CPC H01L24/80
- H01L27/092
- H01L21/8238
- H01L29/423
- CPC H01L27/0922
- H01L27/12
- H01L21/822
- CPC H01L27/12
- CPC H01L27/1248
- H01L21/02
- CPC H01L28/92
- H01L29/20
- H01L29/775
- CPC H01L29/0649
- CPC H01L29/41733
- H03L7/191
- G06F17/15
- H03L7/107
- CPC H03L7/191
- H03M1/10
- CPC H03M1/1014
- H03M1/82
- CPC H03M1/825
- H04L9/00
- H04L9/08
- H04L9/14
- CPC H04L9/008
- H04L9/06
- H04L1/00
- CPC H04L9/0618
- H04L67/5682
- CPC H04L67/5682
- H04N21/4545
- G06F3/14
- CPC H04N21/45455
- H04N21/4627
- H04N7/01
- H04N21/2543
- CPC H04N21/4627
- H04N21/81
- G06Q30/0251
- G06T7/70
- G06T17/00
- CPC H04N21/812
- H05K1/02
- CPC H05K1/023
- H10B53/30
- G11C11/22
- H01L21/28
- CPC H10B53/30
- H10N50/01
- G11C11/16
- H10B61/00
- H10N50/10
- H10N50/80
- CPC H10N50/01
- H10N70/00
- H10B63/00
- CPC H10N70/023
