INTEL CORPORATION patent applications on June 20th, 2024
Patent Applications by INTEL CORPORATION on June 20th, 2024
INTEL CORPORATION: 56 patent applications
INTEL CORPORATION has applied for patents in the areas of H01L29/66 (8), H01L29/778 (5), H01L29/423 (5), H01L29/20 (5), H01L29/40 (5) G06F30/392 (3), H01L27/0266 (2), H01L23/5226 (2), H01L23/15 (2), G02B6/3636 (1)
With keywords such as: device, layer, memory, material, data, substrate, region, based, include, and gate in patent application abstracts.
Patent Applications by INTEL CORPORATION
Inventor(s): Richard Laming of Livingston (GB) for intel corporation, Nicholas D. Psaila of Lanark (GB) for intel corporation
IPC Code(s): G02B6/36, G02B6/38, G02B6/42
CPC Code(s): G02B6/3636
Abstract: an apparatus for positioning one or more optical fibers relative to the apparatus, comprises a body comprising a monolithic block of material, one or more fiber alignment structures formed in the material of the monolithic block, each fiber alignment structure comprising a groove configured to accommodate a corresponding optical fiber, and one or more apparatus alignment features formed in the material of the monolithic block, wherein the one or more apparatus alignment features are additional to the one or more fiber alignment structures and wherein the one or more apparatus alignment features have a known spatial relationship relative to the one or more fiber alignment structures. the one or more apparatus alignment features may enable passive alignment of the apparatus relative to a member which is separate from the apparatus such as an optical component and/or a photonic chip. when one or more optical fibers are located and/or secured in one or more corresponding fiber alignment structures of the apparatus, the one or more apparatus alignment features may also enable passive alignment of the one or more optical fibers relative to the member.
Inventor(s): James Blackwell of Portland OR (US) for intel corporation, Charles Cameron Mokhtarzadeh of Portland OR (US) for intel corporation, Lauren Elizabeth Doyle of () for intel corporation, Eric Mattson of Portland OR (US) for intel corporation, Patrick Theofanis of Portland OR (US) for intel corporation, John J. Plombon of Portland OR (US) for intel corporation, Michael Robinson of Beaverton OR (US) for intel corporation, Marie Krysak of Portland OR (US) for intel corporation, Paul Meza-Morales of Hillsboro OR (US) for intel corporation, Scott Semproni of Portland OR (US) for intel corporation, Scott B. Clendenning of Portland OR (US) for intel corporation
IPC Code(s): G03F7/004, G03F7/038, G03F7/16, G03F7/20, G03F7/38
CPC Code(s): G03F7/0042
Abstract: precursors and methods related to a tin-based photoresist are disclosed herein. in some embodiments, a method for forming a tin-based photoresist may include exposing a tin-containing precursor and a co-reagent to a substrate to form a photoresist having tin clusters; selectively exposing the photoresist to extreme ultraviolet radiation (euv); and exposing the photoresist to heat to form, in the region, crosslinking between the tin clusters. in some embodiments, the precursor has a formula rrsn(n(ch)), and rand rare selected from the group consisting of neo-silyl, neo-pentyl, phenyl, benzyl, methyl-bis(trimethylsilyl), methyl, ethyl, isopropyl, tert-butyl, n-butyl, n,n-dimethylpropylamine, and n, n-dimethlybutylamine. in other embodiments, the precursor includes a chelating alkyl-amine or alkyl-amide ligand featuring a 5 membered or 6 membered tin-based heterocycle bound �-c,n with an alkyl group on the ligand backbone, wherein the alkyl group includes methyl, ethyl, vinyl, hydrogen, or tert-butyl.
20240201834.Concept for Image Data Processing_simplified_abstract_(intel corporation)
Inventor(s): Alex NAYSHTUT of Gan Yavne D (IL) for intel corporation, Dan HOROVITZ of Rishon Lezion (IL) for intel corporation, Miriam ENGEL of Jerusalem (IL) for intel corporation, Victoria ALMOG-AYZENBERG of Haifa (IL) for intel corporation, Ilil BLUM SHEM-TOV of Kiryat Tivon (IL) for intel corporation
IPC Code(s): G06F3/04845, G06T7/20, G06T7/70
CPC Code(s): G06F3/04845
Abstract: examples relate to an apparatus, device, method, and computer program for an image data processing system, to an image date processing system and image data processing method, and to corresponding computer systems and computer programs. an apparatus for an image data processing system is to obtain information on a user selection from a user, the user selection relating to at least one modality of computer-based processing of a depiction of the user the user is comfortable or uncomfortable with, determine a presence of a depiction of the user in image data of a camera, and determine one or more modalities of computer-based processing to be applied to the depiction of the user in the image data based on the user selection, provide control information regarding the one or more modalities of computer-based processing to be applied to the depiction of the user in the image data for the image data processing system.
Inventor(s): Reshma Lal of Portland OR (US) for intel corporation, Sarbartha Banerjee of Austin TX (US) for intel corporation
IPC Code(s): G06F3/06, G06F12/1009, G06F12/14
CPC Code(s): G06F3/0611
Abstract: an apparatus to facilitate in-place memory copy during remote data transfer in a heterogeneous compute environment is disclosed. the apparatus includes a processor to receive data via a network interface card (nic) of a hardware accelerator device; identify a destination address of memory of the hardware accelerator device to write the data; determine that access control bits of the destination address in page tables maintained by a memory management unit (mmu) indicate that memory pages of the destination address are both registered and free; write the data to the memory pages of the destination address; and update the access control bits for memory pages of the destination address to indicate that the memory pages are restricted, wherein setting the access control bits to restricted prevents the nic and a compute kernel of the hardware accelerator device from accessing the memory pages.
Inventor(s): Sagar Varma Sayyaparaju of Telangana (IN) for intel corporation, Om Ji Omer of Bangalore (IN) for intel corporation, Sreenivas Subramoney of Bangalore (IN) for intel corporation
IPC Code(s): G06F7/523, G06F7/50
CPC Code(s): G06F7/523
Abstract: systems, apparatuses and methods may provide for technology that includes a compute-in-memory (cim) enabled memory array to conduct digital bit-serial multiply and accumulate (mac) operations on multi-bit input data and weight data stored in the cim enabled memory array, an adder tree coupled to the cim enabled memory array, an accumulator coupled to the adder tree, and an input bit selection stage coupled to the cim enabled memory array, wherein the input bit selection stage restricts serial bit selection on the multi-bit input data to non-zero values during the digital mac operations.
Inventor(s): Niranjan Soundararajan of Bengaluru (IN) for intel corporation, Sreenivas Subramoney of Bangalore (IN) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3806
Abstract: techniques and mechanisms for efficiently saving and recovering state of a processor core. in an embodiment, a processor core fetches and decodes a first instruction to generate a first decoded instruction, wherein the first instruction comprises a first opcode which corresponds to one or more components of the processor core. execution of the first instruction comprises saving microarchitectural state of the one or more components to a memory of the core. in another embodiment, a processor core fetches and decodes a second instruction to generate a second decoded instruction, wherein the second instruction comprises a second opcode which corresponds to the same one or more components. execution of the second instruction comprises restoring the microarchitectural state from the memory to the one or more components.
Inventor(s): Hideki Ido of Campbell CA (US) for intel corporation
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3842
Abstract: techniques for implementing a branch instruction having a misprediction handling hint to prevent instructions on a mispredicted path from getting cancelled are described. in certain examples, a hardware processor core includes a retirement circuit; a branch predictor circuit to predict a predicted path for a branch, and cause a speculative processing of the predicted path; a decode circuit to decode a single instruction into a decoded instruction, the single instruction having a field to indicate the retirement circuit is to allow retirement of the predicted path for the branch that is a misprediction; and an execution circuit to execute the decoded instruction to cause: the retirement circuit to allow the retirement of the predicted path that is the misprediction for the branch when the field is set to a first value, and the retirement circuit to disallow the retirement of the predicted path that is the misprediction for the branch when the field is otherwise.
20240202025.HYBRID VIRTUAL GPU CO-SCHEDULING_simplified_abstract_(intel corporation)
Inventor(s): Yan Zhao of Shanghai (CN) for intel corporation, Zhi Wang of Tampere (FN) for intel corporation, Weinan Li of Shanghai (CN) for intel corporation
IPC Code(s): G06F9/48, G06F9/30, G06F9/50
CPC Code(s): G06F9/4881
Abstract: an embodiment of a semiconductor package apparatus may include technology to manage one or more virtual graphic processor units, and co-schedule the one or more virtual graphic processor units based on both general processor instructions and graphics processor instructions. other embodiments are disclosed and claimed.
20240202106.A Concept for Generating Code of Test Cases_simplified_abstract_(intel corporation)
Inventor(s): Junjun SHAN of Shanghai (CN) for intel corporation, Minggui CAO of Shanghai (CN) for intel corporation, Jian Jun CHEN of Shanghai (CN) for intel corporation, Qian OUYANG of Shanghai (CN) for intel corporation, Yi QIAN of Shanghai (CN) for intel corporation, Xiangyang WU of Shanghai (CN) for intel corporation
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3684
Abstract: examples relate to an apparatus, a device, a method and a computer program for generating code for test cases for testing a function under test. the apparatus comprises circuitry configured to obtain a diagram representation of the function under test, select a plurality of symbols of interest from the diagram representation of the function under test, the symbols of interest being based on a pre-defined set of symbols of interest, and generate, for the symbols of interest, code of a plurality of test cases based on a pre-defined set of checks related to the pre-defined symbols of interest.
Inventor(s): Israel Diamand of Aderet (IL) for intel corporation, Julius Mandelblat of Haifa (IL) for intel corporation
IPC Code(s): G06F12/0806
CPC Code(s): G06F12/0806
Abstract: techniques and mechanisms for selectively configuring an integrated circuit (ic) chip to provide tag array functionality and/or cache array functionality. in an embodiment, an ic chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. based on whether the ic chip is coupled to another ic chip, selector circuitry of the ic chip configures one of multiple possible modes of the cache controller. a first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. a second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. in another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.
Inventor(s): Israel Diamand of Aderet (IL) for intel corporation, Randy Osborne of Beaverton OR (US) for intel corporation, Nadav Bonen of Ofer (IL) for intel corporation
IPC Code(s): G06F12/0831, G06F12/0864
CPC Code(s): G06F12/0831
Abstract: embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems implementing a very large cache for one or more processing engines in a shared memory system. according to various embodiments, a snoop filter tracks a hash value of the cached addresses instead of tracking the addresses themselves. tracking hash values introduces inaccuracy and an inability to easily clean or refresh the snoop filter. a refresh algorithm maintains cache coherency without significant performance degradation. the cache refresh algorithm keeps the accuracy of the snoop filter, hence reducing the latency and power effects of false snoops. further, the use of hash values reduces the hardware cost over traditional snoop filters.
20240202125.COHERENCY BYPASS TAGGING FOR READ-SHARED DATA_simplified_abstract_(intel corporation)
Inventor(s): Neha Gholkar of Sunnyvale CA (US) for intel corporation, Akhilesh Kumar of Saratoga CA (US) for intel corporation
IPC Code(s): G06F12/084, G06F12/0817, G06F12/0891
CPC Code(s): G06F12/084
Abstract: an example of an apparatus may include memory, two or more caches, and circuitry coupled to the memory and the two or more caches to selectively maintain coherency of data shared among the memory and the two or more caches based on coherency bypass information associated with the data. other examples are disclosed and claimed.
Inventor(s): Karthik V. Narayanan of Chandler AZ (US) for intel corporation, Raghunathan Srinivasan of Chandler AZ (US) for intel corporation
IPC Code(s): G06F12/1009, G06F12/084
CPC Code(s): G06F12/1009
Abstract: an example of an apparatus may include memory and an input/output (io) bus, where an address space of the memory and the io bus is at least partially organized as a plurality of large pages, and where a large page is organized as two or more sub-pages. in some examples, the apparatus further includes circuitry coupled to the memory and the io bus to map an io address to a physical address, and track a modification to a large page at a granularity that corresponds to a size of a subset of the large page. other embodiments are disclosed and claimed.
Inventor(s): Marko Bartscherer of Cornelius OR (US) for intel corporation, Israel A. Cepeda Lopez of Orangevale CA (US) for intel corporation, Antonio S. Cheng of Portland OR (US) for intel corporation, Ke Han of Shanghai (CN) for intel corporation, Manjunatha Kondappa of Folsom CA (US) for intel corporation, Hongjun Li of Shanghai (CN) for intel corporation, Xinpeng Sun of Shanghai (CN) for intel corporation, Feng Xu of Shanghai (CN) for intel corporation, Xiang Ye of Shanghai (CN) for intel corporation, Qipeng Zha of Shanghai (CN) for intel corporation
IPC Code(s): G06F13/20, G06F13/42
CPC Code(s): G06F13/20
Abstract: a system includes a processor in a lid portion of a computing device. the processor is communicatively coupled to a plurality of input/output (i/o) devices according to a plurality of i/o communication protocols via a first number of wires. the system includes a first memory coupled to the processor to store instructions that can be executed by the processor and cause the processor to receive, from a first i/o device of the plurality of i/o devices, a first message according to a first i/o communication protocol of the plurality of i/o communication protocols, convert the first message to a second message according to a host communication protocol, and send the second message over a bus containing a second number of wires traversing a hinge movably coupling the lid portion to a base portion of the computing device. the second number of wires is less than the first number of wires.
Inventor(s): Mona Vij of Hillsboro OR (US) for intel corporation, Dmitrii Kuvaiskii of Taufkirchen (DE) for intel corporation, Bin Xing of Hillsboro OR (US) for intel corporation, Krystof Zmudzinski of Forest Grove OR (US) for intel corporation, Scott Constable of Portland OR (US) for intel corporation
IPC Code(s): G06F21/53
CPC Code(s): G06F21/53
Abstract: techniques and mechanisms for a processor core to execute an instruction for a hardware (hw) thread to have access to a trusted execution environment (tee). in an embodiment, execution of the instruction includes determining whether any sibling hw thread, which is currently active, is also currently approved to access the tee. tee access by the hw thread is conditioned upon a requirement that any sibling hw thread is either currently inactive, is currently in the same tee, or is currently approved to enter the tee. in another embodiment, execution of another instruction, for the hw thread to exit the tee, includes or otherwise results in system software being conditionally notified of an opportunity to wake up one or more sibling hw threads.
Inventor(s): Quan Shi of Portland OR (US) for intel corporation, Patrick Morrow of Portland OR (US) for intel corporation, Charles Henry Wallace of Portland OR (US) for intel corporation, Lars Liebmann of Mechanicville NY (US) for intel corporation, Thi Nguyen of Beaverton OR (US) for intel corporation, Sivakumar Venkataraman of Hillsboro OR (US) for intel corporation, Nikolay Ryzhenko Vladimirovich of Beaverton OR (US) for intel corporation, Xinning Wang of Hillsboro OR (US) for intel corporation, Douglas Stout of Aurora CO (US) for intel corporation
IPC Code(s): G06F30/392, G06F30/394
CPC Code(s): G06F30/392
Abstract: transistor cell architectures have three mo routing tracks within a single cell height. the cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. each diffusion region extends primarily in a particular direction, and the mo routing tracks extending in the same direction as the diffusion regions. one mo routing track may be formed over each of the diffusion regions, and a third mo routing track formed between the diffusion regions.
Inventor(s): Wei-Yi Hu of Sunnyvale CA (US) for intel corporation
IPC Code(s): G06F30/392
CPC Code(s): G06F30/392
Abstract: an integrated circuit structure includes a plurality of first and second cells, each first and second cell including corresponding two or more transistor devices. each first cell has a first height. each second cell has a second height, the second height at least 3 nanometers (nm) different from the first height. the cells are arranged in a plurality of rows, where a row includes a first cell and a second cell. an imaginary line passes through the first cell, and divides the first cell into a first upper portion having a first upper height and a first lower portion having a first lower height that are within 1 nm of each other. the imaginary line also divides the second cell into a second upper portion having a second upper height and a second lower portion having a second lower height that are within 1 nm of each other.
Inventor(s): Miaomiao Ma of Sunnyvale CA (US) for intel corporation, Adam Norman of Forest Grove OR (US) for intel corporation, Jianfang Olena Zhu of Portland OR (US) for intel corporation, Mackenzie Norman of Portland OR (US) for intel corporation, Mark Gallina of Hillsboro OR (US) for intel corporation, Pei Chun Ch'ng of Penang (MY) for intel corporation, Xia Zhu of Portland OR (US) for intel corporation, Jagadeesh Radhakrishnan of Folsom CA (US) for intel corporation, Soon Khiang Toh of PENANG (MY) for intel corporation, Omer Vikinski of Haifa (IS) for intel corporation, Slade Morgan of Forest Grove OR (US) for intel corporation
IPC Code(s): G06F30/392, G06F30/27, G06F115/02, G06F119/08
CPC Code(s): G06F30/392
Abstract: systems, apparatuses and methods may provide for technology that determines a plurality of transient thermal responses for a corresponding plurality of power source locations on a semiconductor die, obtains corner block list (cbl) representations associated with a plurality of candidate floorplans, and conducts an artificial intelligence (ai) based search of the cbl representations, wherein an output of the ai based search is one or more suggested floorplans having a transient thermal response that is below a thermal threshold.
Inventor(s): Linlin Zhang of Shanghai (CN) for intel corporation, Ning Luo of Shanghai (CN) for intel corporation, Changliang Wang of Bellevue WA (US) for intel corporation, Yi Qian of Shanghai (CN) for intel corporation, Zhisheng Zhou of Shenzhen (CN) for intel corporation
IPC Code(s): G06T15/00, H04N13/366
CPC Code(s): G06T15/005
Abstract: the disclosure relates to content aware foveated asw for low latency rendering. a device for graphics processing comprises processing resources and a pipeline at least partly implemented by the processing resources. the pipeline is to: render input data to generate a first frame; perform asw on the first frame on a block basis based on content and focusing related information associated with the first frame to generate a second frame; and output the first frame and the second frame.
20240203664.IN CORE LARGE AREA CAPACITORS_simplified_abstract_(intel corporation)
Inventor(s): Yosef KORNBLUTH of Phoenix AZ (US) for intel corporation, Bainye Francoise ANGOUA of Phoenix AZ (US) for intel corporation, Whitney BRYKS of Tempe AZ (US) for intel corporation, Daniel ROSALES-YEOMANS of Gilbert AZ (US) for intel corporation, Aaditya Anand CANDADAI of Chandler AZ (US) for intel corporation, Holly CLINGAN of Chandler AZ (US) for intel corporation, Jade Sharee LEWIS of Phoenix AZ (US) for intel corporation, Patrick QUACH of Chandler AZ (US) for intel corporation, Srinivas V. PIETAMBARAM of Chandler AZ (US) for intel corporation
IPC Code(s): H01G4/33, H01G4/10
CPC Code(s): H01G4/33
Abstract: embodiments disclosed herein include a core for a package substrate. in an embodiment, the core comprises a first substrate with a first surface and a second surface, a first recess into the first surface of the first substrate, a first layer in the first recess, where the first layer is electrically conductive, a second layer over the first layer, where the second layer is a dielectric layer, and a third layer over the second layer, where the third layer is electrically conductive. in an embodiment, the core further comprises a second substrate with a third surface and a fourth surface, where the third surface of the second substrate faces the first surface of the first substrate, a second recess in the third surface of the second substrate, and a fourth layer in the second recess, where the fourth layer is electrically conductive, and the fourth layer contacts the third layer.
Inventor(s): Swapnadip Ghosh of Hillsboro OR (US) for intel corporation, Yulia Gotlib of Hillsboro OR (US) for intel corporation, Matthew J. Prince of Portland OR (US) for intel corporation, Alison V. Davis of Portland OR (US) for intel corporation, Chun Chen Kuo of Portland OR (US) for intel corporation, Andrew Arnold of Hillsboro OR (US) for intel corporation, Cun Wen of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L21/28, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/775
CPC Code(s): H01L21/28123
Abstract: techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. a semiconductor device includes a gate structure around or otherwise on a semiconductor region. the gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. some of the gate cuts may be at least 2� wider than others. such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.
20240203805.EMBEDDED MEMORY FOR GLASS CORE PACKAGES_simplified_abstract_(intel corporation)
Inventor(s): Mohammad Mamunur RAHMAN of Gilbert AZ (US) for intel corporation, Brandon C. MARIN of Gilbert AZ (US) for intel corporation, Gang DUAN of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/15, H01L23/00, H01L23/498, H01L23/538, H01L25/065
CPC Code(s): H01L23/15
Abstract: embodiments disclosed herein include electronic package packages. in an embodiment, the electronic package comprises a package substrate. in an embodiment, a first die is embedded in the package substrate, and a second die is over the package substrate. in an embodiment, the first die is entirely within a footprint of the second die.
20240203806.GLASS LAYER WITH LITHO DEFINED THROUGH-GLASS VIA_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Leonel R. Arana of Phoenix AZ (US) for intel corporation, Dingying XU of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Jeremy D. Ecton of Gilbert AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Bin Mu of Tempe AZ (US) for intel corporation
IPC Code(s): H01L23/15, C03C17/00, C03C17/06, H01L21/48, H01L23/498
CPC Code(s): H01L23/15
Abstract: an electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. the layer can be preformed with through glass vias that support at least one electrically conductive interconnect. the through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.
Inventor(s): Samuel James BADER of Hillsboro OR (US) for intel corporation, Nachiket Venkappayya DESAI of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation
IPC Code(s): H01L23/34, H01L29/20, H01L29/40, H01L29/66, H01L29/778
CPC Code(s): H01L23/34
Abstract: layer transfer for gallium nitride (gan) integrated circuit technology is described. in an example, an integrated circuit structure includes a gan device on or above a substrate, the gan device including a source, a gate and a drain. a silicon-based diode structure or a silicon-based thin-film resistor is above the substrate, the silicon-based diode structure or the silicon-based thin-film resistor over the gan device in a region between the gate and the drain of the gan device.
20240203853.DRY FILM PHOTORESIST WET LAMINATION AND METHOD_simplified_abstract_(intel corporation)
Inventor(s): Bohan Shan of Chandler AZ (US) for intel corporation, Haobo Chen of Chandler AZ (US) for intel corporation, Hongxia Feng of Chandler AZ (US) for intel corporation, Julianne Troiano of Scottsdale AZ (US) for intel corporation, Dingying Xu of Chandler AZ (US) for intel corporation, Matthew Tingey of Mesa AZ (US) for intel corporation, Xiaoying Guo of Chandler AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Bai Nie of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Bin Mu of Tempe AZ (US) for intel corporation, Kyle Mcelhinny of Tempe AZ (US) for intel corporation, Ashay A. Dani of Chandler AZ (US) for intel corporation, Leonel R. Arana of Phoenix AZ (US) for intel corporation
IPC Code(s): H01L23/498, H01L21/48, H01L23/538
CPC Code(s): H01L23/49827
Abstract: an electronic device and associated methods are disclosed. in one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. the substrate can include a conductor coating. the via can be connected to the conductor coating. the build-up layer can be on the substrate. the build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. the top layer can be interproximal to the substrate and the via. the one or more dies can be connected to the via.
Inventor(s): Gurpreet Singh of Portland OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, David Nathan Shykind of Buxton OR (US) for intel corporation, Richard E. Schenker of Portland OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Nafees Aminul Kabir of Hillsboro OR (US) for intel corporation, Sean Michael Pursel of Hillsboro OR (US) for intel corporation, Nityan Labros Nair of Portland OR (US) for intel corporation, Robert Seidel of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768
CPC Code(s): H01L23/5226
Abstract: metal lines are formed through serial dsa processes. a first dsa process may define a pattern of first hard masks. first metal lines are fabricated based on the first hard masks. a metal cut crossing one or more first metal lines may be formed. a width of the metal cut is no greater than a pitch of the first metal lines. after the metal cut is formed, a second dsa process is performed to define a pattern of second hard masks. edges of a second hard mask may align with edges of a first metal line. an insulator may be formed around a second hard mask to form an insulative structure. an axis of the insulative structure may be aligned with an axis of a first metal line. second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.
Inventor(s): Sukru Yemenicioglu of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation, Nikhil Jasvant Mehta of Portland OR (US) for intel corporation, Charles Henry Wallace of Portland OR (US) for intel corporation
IPC Code(s): H01L23/522, H01L21/768, H01L23/532
CPC Code(s): H01L23/5226
Abstract: methods for fabricating an integrated circuit (ic) device with one or more hybrid metal lines are provided. an example ic device includes a substrate; and a metal line extending, along an axis, over the substrate. the metal line has a first end and a second end along the axis. a portion of the metal line at the first end includes a first electrically conductive material. another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. in some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.
Inventor(s): Feras Eid of Chandler AZ (US) for intel corporation, Joe Walczyk of Tigard OR (US) for intel corporation, Weihua Tang of Chandler AZ (US) for intel corporation, Akhilesh Rallabandi of Chandler AZ (US) for intel corporation, Marco Aurelio Cartas Ayala of Chandler AZ (US) for intel corporation
IPC Code(s): H01L23/00
CPC Code(s): H01L24/29
Abstract: an integrated circuit (ic) die structure comprises a substrate material comprising silicon. integrated circuitry is over a first side of the substrate material. a composite layer is in direct contact with a second side of the substrate material. the second side is opposite the first side. the composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (cte), and a first thermal conductivity exceeding that of the substrate. the composite layer also comprises a second constituent material associated with a second cte that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
Inventor(s): Samuel James BADER of Hillsboro OR (US) for intel corporation, Nachiket Venkappayya DESAI of Portland OR (US) for intel corporation, Harish KRISHNAMURTHY of Beaverton OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation, William J. LAMBERT of Tempe AZ (US) for intel corporation, Jingshu YU of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L29/16, H01L29/20, H01L29/40, H01L29/66, H01L29/778
CPC Code(s): H01L27/0266
Abstract: layer transfer for gallium nitride (gan) integrated circuit technology is described. in an example, an integrated circuit structure includes a gan device on or above a substrate, the gan device including a source, a gate and a drain. a silicon-based clamp structure is above substrate, the silicon-based clamp structure over the gan device in a region that overlaps the source and the gate of the gan device.
Inventor(s): Samuel James BADER of Hillsboro OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation
IPC Code(s): H01L27/02, H01L29/20, H01L29/66, H01L29/778
CPC Code(s): H01L27/0266
Abstract: layer transfer for gallium nitride (gan) integrated circuit technology is described. in an example, an integrated circuit structure includes a gan device on or above a substrate, the gan device including a source, a gate and a drain. a silicon-based transistor structure is above substrate, the silicon-based transistor structure at a level above the gate of the gan device in a region outside of the gan device.
Inventor(s): Hwichan Jun of Portland OR (US) for intel corporation
IPC Code(s): H01L29/08, H01L23/00, H01L27/085, H01L29/06, H01L29/16, H01L29/423
CPC Code(s): H01L29/0843
Abstract: techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. a first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. the first and second semiconductor devices include a subfin region adjacent to a dielectric layer. a conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. a dielectric layer is also present between the conductive contact and the subfin region.
Inventor(s): Pratik KOIRALA of Portland OR (US) for intel corporation, Michael S. BEUMER of Portland OR (US) for intel corporation, Marko RADOSAVLJEVIC of Portland OR (US) for intel corporation, Han Wui THEN of Portland OR (US) for intel corporation
IPC Code(s): H01L29/32, H01L29/20, H01L29/205, H01L29/40, H01L29/778
CPC Code(s): H01L29/32
Abstract: gallium nitride (gan) with interlayers for integrated circuit technology is described. in an example, an integrated circuit structure includes a substrate including silicon. a layer including gallium and nitrogen is above the substrate. the layer including gallium and nitrogen has an interlayer therein. the interlayer confines a plurality of defects to a lower portion of the layer including gallium and nitrogen.
Inventor(s): Rohit Galatage of Hillsboro OR (US) for intel corporation, Cheng-Ying Huang of Portland OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation, Jami Wiedemer of Scappoose OR (US) for intel corporation, Munzarin Qayyum of Hillsboro OR (US) for intel corporation, Evan Clinton of Carrollton GA (US) for intel corporation
IPC Code(s): H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/401
Abstract: ic structures with nanoribbon stacks without dielectric protection caps for top nanoribbons, and associated methods and devices, are disclosed. an example ic structure includes a stack of nanoribbons, an opening over the top nanoribbon of the stack of nanoribbons, and a gate electrode material in the opening, where the opening has a first portion, a second portion, and a third portion, the second portion is between the first portion and the third portion, and where a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion. in such an ic structure, a gate insulator on the sidewalls of the first portion of the opening is materially discontinuous from a gate insulator on the sidewalls of the third portion of the opening.
Inventor(s): Guillaume Bouche of Portland OR (US) for intel corporation, Bilal Chehab of Portland OR (US) for intel corporation, Lars Liebmann of Mechanicville NY (US) for intel corporation, Quan Shi of Portland OR (US) for intel corporation
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/40, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L29/41733
Abstract: techniques are provided herein to form semiconductor devices having a dielectric wall or spine between two devices that extends between source or drain regions of the two devices and separates backside contacts to the source or drain regions. a first semiconductor device includes a first semiconductor region extending from a first source or drain region and a second adjacent semiconductor device includes a second semiconductor region extending from a second source or drain region adjacent to the first source or drain region. a dielectric wall extends between the first source or drain region and the second source or drain region. a first backside contact touches the underside of the first source or drain region and a second backside contact touches the underside of the second source or drain region. the dielectric wall further extends down between the first conductive contact and the second conductive contact.
Inventor(s): Gurpreet Singh of Portland OR (US) for intel corporation, Manish Chandhok of Beaverton OR (US) for intel corporation, Florian Gstrein of Portland OR (US) for intel corporation, Charles Henry Wallace of Portland OR (US) for intel corporation, Eungnak Han of Portland OR (US) for intel corporation, Leonard P. Guler of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/66, H01L21/768, H01L21/8234, H01L23/00, H01L23/498, H01L25/065
CPC Code(s): H01L29/6656
Abstract: dsa-based spacers and liners can provide shorting margins for vias connected to conductive structures. self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. spacers may be formed based on the self-assembly of the diblock copolymer. each spacer includes an electrical insulator and is over an insulative structure. each liner may wrap around one or more side surfaces of a spacer. each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. the insulative spacing structures may include a different electrical insulator from the insulative structures. the conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.
Inventor(s): Heli Vora of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Pratik Koirala of Portland OR (US) for intel corporation, Han Wui Then of Portland OR (US) for intel corporation, Michael Beumer of Portland OR (US) for intel corporation, Ahmad Zubair of Hillsboro OR (US) for intel corporation, Samuel Bader of Hillsboro OR (US) for intel corporation
IPC Code(s): H01L29/778, H01L21/285, H01L21/306, H01L29/20, H01L29/47, H01L29/66
CPC Code(s): H01L29/7786
Abstract: devices, transistor structures, systems, and techniques are described herein related to low aluminum concentration aluminum gallium nitride interlayers for group iii-nitride enhancement mode transistors. the low aluminum concentration aluminum gallium nitride interlayer includes a lower aluminum concentration than a polarization layer of the transistor, such that the polarization layer induces a two-dimensional electron gas in a semiconductor layer of the transistor. the low aluminum concentration aluminum gallium nitride interlayer may be implemented as an etch stop layer, as a gate liner, or both.
Inventor(s): Rohit Galatage of Hillsboro OR (US) for intel corporation, Cheng-Ying Huang of Portland OR (US) for intel corporation, Dan S. Lavric of Portland OR (US) for intel corporation, Sarah Atanasov of Beaverton OR (US) for intel corporation, Shao Ming Koh of Tigard OR (US) for intel corporation, Jack T. Kavalieros of Portland OR (US) for intel corporation, Marko Radosavljevic of Portland OR (US) for intel corporation, Mauro J. Kobrinsky of Portland OR (US) for intel corporation, Jami Wiedemer of Scappoose OR (US) for intel corporation, Munzarin Qayyum of Hillsboro OR (US) for intel corporation, Evan Clinton of Carrollton GA (US) for intel corporation
IPC Code(s): H01L29/78, H01L29/06, H01L29/423, H01L29/49
CPC Code(s): H01L29/785
Abstract: disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include multiple dipole materials, and related methods and devices. for example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. the transistor gate stack may include a gate electrode material and a gate dielectric material between the gate electrode material and the channel material, where the gate dielectric material includes a first dipole material and a second dipole material where one of the first and second dipole materials is a p-shifter dipole material and the other one is an n-shifter dipole material.
Inventor(s): Amit Agarwal of Hillsboro OR (US) for intel corporation, Steven K. Hsu of Lake Oswego OR (US) for intel corporation, Ram Kumar Krishnamurthy of Portland OR (US) for intel corporation
IPC Code(s): H03K19/094, H03K19/017, H03K19/1776
CPC Code(s): H03K19/09425
Abstract: some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.
20240204879.PHOTONIC SYSTEM WITH MARKER TONE_simplified_abstract_(intel corporation)
Inventor(s): Duanni Huang of San Jose CA (US) for intel corporation, Xinru Wu of San Jose CA (US) for intel corporation, Taehwan Kim of Portland OR (US) for intel corporation, Ganesh Balamurugan of Hillsboro OR (US) for intel corporation, Haisheng Rong of Pleasanton CA (US) for intel corporation
IPC Code(s): H04B10/50, H04B10/69
CPC Code(s): H04B10/503
Abstract: embodiments herein relate to an optical system coupled with or including a control logic. the control logic may be configured to identify, based on feedback provided by a photodiode (pd) of an optical receiver, that an amplitude of an optical marker signal output by an interferometer of the optical receiver is above a threshold value. the control logic may further be configured to adjust, based on the identification, a thermo-optic phase tuner of the interferometer, wherein adjustment of the thermo-optic phase tuner results in a change to the amplitude of the optical marker signal. other embodiments may be described and/or claimed.
20240204899.PHASE SYNCHRONIZATION BETWEEN TIMERS_simplified_abstract_(intel corporation)
Inventor(s): Mark BORDOGNA of Andover MA (US) for intel corporation, Zoltan FODOR of Swindon (GB) for intel corporation
IPC Code(s): H04J3/06
CPC Code(s): H04J3/0667
Abstract: examples described herein relate to a first network interface controller comprising a first network interface, first timer, and a first signal transceiver and circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller. the circuitry to reduce offset between the first timer of the first network interface controller and a second timer of a second network interface controller based on a first signal transmitted over a communication line from the first signal transceiver to the second network interface controller and also based on the first signal transmitted from the second network interface controller back to the first network interface controller over the communication line.
Inventor(s): Gang XIONG of Portland OR (US) for intel corporation, Yingyang LI of Santa Clara CA (US) for intel corporation, Daewon LEE of Portland OR (US) for intel corporation, Alexei DAVYDOV of Santa Clara CA (US) for intel corporation
IPC Code(s): H04L5/00
CPC Code(s): H04L5/001
Abstract: various embodiments herein provide techniques related to a physical downlink control channel (pdcch) that includes a single downlink control information (dci). the single dci may be related to a first set of one or more physical shared channels on a first component carrier (cc) and a second set of two or more physical shared channels on a second component carrier (cc). other embodiments may be described and/or claimed.
Inventor(s): Ned M. Smith of Beaverton OR (US) for intel corporation, Keith Nolan of Mullingar (IE) for intel corporation, Mark Kelly of Leixlip (IE) for intel corporation
IPC Code(s): H04L41/0806, G06F16/182, H04L9/00, H04L9/08, H04L9/32, H04L41/12, H04L45/00, H04L61/4505, H04L61/5069, H04L67/10, H04L67/104, H04L67/1087, H04L67/12, H04L67/562, H04L69/18, H04L69/22, H04W4/08, H04W4/70, H04W12/69, H04W84/18, H04W84/22
CPC Code(s): H04L41/0806
Abstract: an internet of things (iot) network includes an iot device with a communicator to send a communication including egress frame, protocol library builder to determine available protocols, frame analyzer to analyze an ingress frame, and frame builder to build the egress frame from the ingress frame. an iot network includes an iot device with network discoverer to identify available parallel communication channels between the iot device and target device, payload, payload fragmenter/packager to fragment the payload into sub-objects for transmission, and packet communicator to send sub-objects to the target device over parallel communication channels. an iot network includes a plurality of iot devices, which each include a communication channel to an upstream device, a network link to another one of the plurality of iot devices, a hash calculator to identify a neighbor iot device, and a communicator to send out a message to the neighbor iot device.
20240205113.ENHANCING PERFORMANCE IN NETWORK-BASED SYSTEMS_simplified_abstract_(intel corporation)
Inventor(s): Asaf Ezra of Tel Aviv (IL) for intel corporation, Tal Saiag of Tel Aviv (IL) for intel corporation, Ron Gruner of Tel Aviv (IL) for intel corporation
IPC Code(s): H04L41/5054, G06F9/52, H04L41/14, H04L67/10
CPC Code(s): H04L41/5054
Abstract: a method, system, and computer program product, the method comprising: obtaining a data path representing flow of data in processing a service request within a network computing environment having system resources; analyzing the data path to identify usage of the system resources required by the service request processing; determining, based on the usage of the system resources, an optimization action expected to improve the usage of the system resources; and implementing the optimization action in accordance with the data path, thereby modifying operation of the cloud computing environment in handling future service requests.
20240205143.MANAGEMENT OF PACKET TRANSMISSION AND RESPONSES_simplified_abstract_(intel corporation)
Inventor(s): Hossein FARROKHBAKHT of Toronto (CA) for intel corporation, Fabrizio PETRINI of Menlo Park CA (US) for intel corporation
IPC Code(s): H04L45/00, H04L45/28
CPC Code(s): H04L45/38
Abstract: examples described herein relate to a router. in some examples, the router includes an interface and circuitry coupled to the interface. in some examples, the circuitry is to: based on receipt of a negative acknowledgement (nack) message: record an endpoint destination of a packet corresponding to the nack message in a data allocated per-link and drop a second packet transmitted to the endpoint destination corresponding to the nack message to drop the second packet one or more hops before reaching a congested device.
20240205167.SYSTEM-IN-PACKAGE NETWORK PROCESSORS_simplified_abstract_(intel corporation)
Inventor(s): Kevin Clark of San Jose CA (US) for intel corporation, Scott J. Weber of Piedmont CA (US) for intel corporation, Ravi Prakash Gutala of San Jose CA (US) for intel corporation, Aravind Raghavendra Dasu of Milpitas CA (US) for intel corporation
IPC Code(s): H04L49/109, H01L23/538, H01L25/065, H04L49/15
CPC Code(s): H04L49/109
Abstract: this disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. the data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. the data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
Inventor(s): Kapil Sood of Portland OR (US) for intel corporation, Srinivasa Addepalli of San Jose CA (US) for intel corporation, Dong Guo of Kunshan City (CN) for intel corporation, Sakari Poussa of Espoo (ES) for intel corporation, Kailun Qin of Shanghai (CN) for intel corporation, Ismo Puustinen of Helsinki (ES) for intel corporation, Veronika Karperko of New Ross (IE) for intel corporation
IPC Code(s): H04L9/40
CPC Code(s): H04L63/0428
Abstract: various methods, systems, and use cases for securely managing, generating, and controlling access to keys in a service mesh are discussed herein. in various examples, key protection operations include service mesh signing key protection and service mesh communication key protection, for a secure transport session between services such as conducted with mutual transport layer security (mtls). for instance, such key protection operations may be used to establish communications between the service host and another entity within the service mesh, in a secure transport session, based on use of a private key (secured using a confidential computing technology) in a secure enclave or other secure compute environment to sign one or more keys for the secure transport session.
Inventor(s): Arvind Kumar of Beaverton OR (US) for intel corporation, Duncan Glendinning of Chandler AZ (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation, Anand Rangarajan of Portland OR (US) for intel corporation, Gautam Singh of Morrisville NC (US) for intel corporation
IPC Code(s): H04L65/1069, H04L67/02
CPC Code(s): H04L65/1069
Abstract: methods, apparatus, systems, and articles of manufacture are disclosed to improve device connectivity. an example system includes an electronic device to broadcast a message including a uniform resource indicator (uri), the uri corresponding to the electronic device, and an endpoint device to, after obtaining the message, launch a user interface to display a request for authorization to connect to the electronic device, after obtaining the authorization, retrieve an instance of a container based on the uri, and execute a service with the container based on data obtained from the electronic device.
Inventor(s): Kent C. LUSTED of Aloha OR (US) for intel corporation
IPC Code(s): H04L69/24, H04L1/00
CPC Code(s): H04L69/24
Abstract: examples described herein relate to ethernet physical layer transceiver (phy) circuitry for use in frame communication with a remote link partner and that is to perform capabilities auto-negotiation with a link partner.
Inventor(s): Praveen Kashyap Ananta Bhat of Bangalore (IN) for intel corporation, Rahul R. of Aluva (IN) for intel corporation, Passant V. Karunaratne of Chandler AZ (US) for intel corporation, Navya P. of Bangalore (IN) for intel corporation, Nagalakshmi Shashidhara Guptha of Bengaluru (IN) for intel corporation, Venkateshan Udhayan of Portland OR (US) for intel corporation, Tao Tao of Portland OR (US) for intel corporation, Chia-Hung S. Kuo of Folsom CA (US) for intel corporation, Balvinder Pal Singh of Bhilai (IN) for intel corporation, Stanley Baran of Chandler AZ (US) for intel corporation, Aiswarya Pious of Bangalore (IN) for intel corporation, Michael Rosenzweig of Queen Creek AZ (US) for intel corporation
IPC Code(s): H04N7/15, H04W24/08
CPC Code(s): H04N7/157
Abstract: systems, apparatus, articles of manufacture, and methods are disclosed to manage video conferencing call data. an example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to access input data associated with a first video conferencing device, the first video conferencing device communicatively coupled to a second video conferencing device via a network, generate a representation of the input data when a performance metric corresponding to the network satisfies a threshold value, and transmit the representation to the second video conferencing device via the network.
Inventor(s): Nader Mahdi of Maple Ridge (CA) for intel corporation
IPC Code(s): H04N19/50, H04N19/105, H04N19/139, H04N19/176
CPC Code(s): H04N19/50
Abstract: in the process of block-prediction in block-based video compression, a vector for translating a reference block to produce a predicted block is not encoded directly in an encoded bitstream. rather, a residual vector, which is the difference between the vector and a selected vector predictor candidate, is encoded to achieve higher compression efficiency. a selected vector predictor candidate can have the smallest euclidean distance to the vector to ensure the residual vector is small. for compressing video that has complex spatial and/or temporal characteristics, the selected vector predictor candidate may not result in the smallest residual vector. to address this concern, vector predictor candidates are selected separately for the horizontal component and the vertical component of the vector to obtain smaller residual vectors. an effective and efficient signaling scheme can be implemented to indicate whether the predictor is based on components from two different predictor candidates.
Inventor(s): Mikhail Shilov of Santa Clara CA (US) for intel corporation, Alexey Khoryaev of Santa Clara CA (US) for intel corporation, Sergey Panteleev of Kildare (IE) for intel corporation, Sergey Sosnin of Santa Clara CA (US) for intel corporation, Kilian Roth of Munich (DE) for intel corporation
IPC Code(s): H04W28/02, H04W4/40, H04W28/16, H04W72/20, H04W72/56
CPC Code(s): H04W28/0289
Abstract: embodiments herein relate to sidelink communication between nodes, aspects of the sidelink communication, in accordance with embodiments herein, may include one or more of resource selection, congestion control, and resource signaling. specific embodiments may relate to use of at least one priority level during the sidelink communication. other embodiments may be described and/or claimed.
20240205781.USER EQUIPMENT TRAJECTORY-ASSISTED HANDOVER_simplified_abstract_(intel corporation)
Inventor(s): Ziyi Li of Beijing (CN) for intel corporation, Dawei Ying of Portland OR (US) for intel corporation, Qian Li of Portland OR (US) for intel corporation, Youn Hyoung Heo of Santa Clara CA (US) for intel corporation, Jaemin Han of Santa Clara CA (US) for intel corporation, Zongrui Ding of Portland OR (US) for intel corporation, Maruti Gupta Hyde of Santa Clara CA (US) for intel corporation, Yi Zhang of San Jose CA (US) for intel corporation, Sudeep Palat of Cheltenham (GB) for intel corporation, Yi Guo of Shanghai (CN) for intel corporation
IPC Code(s): H04W36/32, H04W36/00, H04W36/36
CPC Code(s): H04W36/322
Abstract: systems, apparatuses, methods, and computer-readable media are provided for user equipment (ue) trajectory-assisted handovers. in particular, some embodiments may include artificial intelligence (ai) or machine learning (ml) to predict ue location information. other embodiments may be described and/or claimed.
Inventor(s): Venkateshan Udhayan of Portland OR (US) for intel corporation, Nevo Idan of Zichron Ya'akov (IL) for intel corporation, Leor Rom of Haifa (IL) for intel corporation
IPC Code(s): H04W52/02, H04W76/20
CPC Code(s): H04W52/0235
Abstract: for example, an apparatus may include circuitry and logic configured to cause a wireless communication device to identify an end-to-end network latency of a data stream communicated between the wireless communication device and an endpoint via a wireless communication link between the wireless communication device and an access point (ap); and to set an idle timeout period for the wireless communication link based on the end-to-end network latency of the data stream. for example, the idle timeout period includes a time period after which the wireless communication device is to be allowed to switch the wireless communication link from an active mode to a power save mode when the wireless communication link is idle.
Inventor(s): Walid EL HAJJ of Antibes (FR) for intel corporation, Nawfal ASRIH of Mandelieu-la-Napoule (FR) for intel corporation, Manuel BLAZQUEZ DE PINEDA of Antibes (FR) for intel corporation, Wilfrid DANGELO of Mougins (FR) for intel corporation, Mythili HEGDE of Bangalore (IN) for intel corporation, Noam KOGOS of Ramat Hasharon (IL) for intel corporation, Ronen KRONFELD of Shoham (IL) for intel corporation, Gil MEYUHAS of Tel-Aviv (IL) for intel corporation, Robert PAXMAN of Hillsboro OR (US) for intel corporation, Ehud RESHEF of Qiryat Tivon (IL) for intel corporation, John ROMAN of Hillsboro OR (US) for intel corporation, Rony ROSS of Haifa (IL) for intel corporation, Amir RUBIN of Kiryat Ono (IL) for intel corporation
IPC Code(s): H04W52/36
CPC Code(s): H04W52/367
Abstract: disclosed herein are devices, methods, and systems for adjusting transmit properties based on compliance metrics for human exposure to radiation. as one example, the system determines a first transmission power limit associated with transmissions on a first radio resource, wherein the first transmission power limit is based on a first compliance level threshold of human exposure to emitted radiation when using the first radio resource. the system determines a second transmission power limit associated with transmissions on a second radio resource, wherein the second transmission power limit is based on a second compliance level threshold of human exposure to emitted radiation when transmitting using the second radio resource. the system also controls a wireless device to select either the first radio resource or the second radio resource for a transmission from the wireless device based on the first transmission power limit and the second transmission power limit.
Inventor(s): Yingyang Li of Beijing (CN) for intel corporation, Yi Wang of Beijing (CN) for intel corporation, Debdeep Chatterjee of San Jose CA (US) for intel corporation, Gang Xiong of Portland OR (US) for intel corporation, Seunghee Han of San Jose CA (US) for intel corporation
IPC Code(s): H04W72/12, H04W72/23
CPC Code(s): H04W72/12
Abstract: various embodiments may relate to physical downlink control channel (pdcch) monitoring in association with cross-carrier scheduling. in particular, some embodiments are directed to scheduling a transmission on a primary cell (pcell) or primary secondary cell (pscell) considering secondary cell (scell) dormancy switching or scell activation states. other embodiments may be disclosed or claimed.
Inventor(s): Punyashloka Debashis of Hillsboro OR (US) for intel corporation, Ian Alexander Young of Olympia WA (US) for intel corporation, Dmitri Evgenievich Nikonov of Beaverton OR (US) for intel corporation, Chia-Ching Lin of Portland OR (US) for intel corporation, Hai Li of Portland OR (US) for intel corporation
IPC Code(s): H10N52/85, G11C11/16, H03K19/20, H10B61/00, H10N50/10, H10N50/85
CPC Code(s): H10N52/85
Abstract: in embodiments herein, probabilistic and deterministic logic devices include reduced symmetry materials, such as two-dimensional (2d) transition metal dichalcogenide (tmd) materials (e.g., nbseor mote).
- INTEL CORPORATION
- G02B6/36
- G02B6/38
- G02B6/42
- CPC G02B6/3636
- Intel corporation
- G03F7/004
- G03F7/038
- G03F7/16
- G03F7/20
- G03F7/38
- CPC G03F7/0042
- G06F3/04845
- G06T7/20
- G06T7/70
- CPC G06F3/04845
- G06F3/06
- G06F12/1009
- G06F12/14
- CPC G06F3/0611
- G06F7/523
- G06F7/50
- CPC G06F7/523
- G06F9/38
- G06F9/30
- CPC G06F9/3806
- CPC G06F9/3842
- G06F9/48
- G06F9/50
- CPC G06F9/4881
- G06F11/36
- CPC G06F11/3684
- G06F12/0806
- CPC G06F12/0806
- G06F12/0831
- G06F12/0864
- CPC G06F12/0831
- G06F12/084
- G06F12/0817
- G06F12/0891
- CPC G06F12/084
- CPC G06F12/1009
- G06F13/20
- G06F13/42
- CPC G06F13/20
- G06F21/53
- CPC G06F21/53
- G06F30/392
- G06F30/394
- CPC G06F30/392
- G06F30/27
- G06F115/02
- G06F119/08
- G06T15/00
- H04N13/366
- CPC G06T15/005
- H01G4/33
- H01G4/10
- CPC H01G4/33
- H01L21/28
- H01L29/06
- H01L29/423
- H01L29/49
- H01L29/66
- H01L29/775
- CPC H01L21/28123
- H01L23/15
- H01L23/00
- H01L23/498
- H01L23/538
- H01L25/065
- CPC H01L23/15
- C03C17/00
- C03C17/06
- H01L21/48
- H01L23/34
- H01L29/20
- H01L29/40
- H01L29/778
- CPC H01L23/34
- CPC H01L23/49827
- H01L23/522
- H01L21/768
- CPC H01L23/5226
- H01L23/532
- CPC H01L24/29
- H01L27/02
- H01L29/16
- CPC H01L27/0266
- H01L29/08
- H01L27/085
- CPC H01L29/0843
- H01L29/32
- H01L29/205
- CPC H01L29/32
- CPC H01L29/401
- H01L29/417
- H01L21/8238
- H01L27/092
- CPC H01L29/41733
- H01L21/8234
- CPC H01L29/6656
- H01L21/285
- H01L21/306
- H01L29/47
- CPC H01L29/7786
- H01L29/78
- CPC H01L29/785
- H03K19/094
- H03K19/017
- H03K19/1776
- CPC H03K19/09425
- H04B10/50
- H04B10/69
- CPC H04B10/503
- H04J3/06
- CPC H04J3/0667
- H04L5/00
- CPC H04L5/001
- H04L41/0806
- G06F16/182
- H04L9/00
- H04L9/08
- H04L9/32
- H04L41/12
- H04L45/00
- H04L61/4505
- H04L61/5069
- H04L67/10
- H04L67/104
- H04L67/1087
- H04L67/12
- H04L67/562
- H04L69/18
- H04L69/22
- H04W4/08
- H04W4/70
- H04W12/69
- H04W84/18
- H04W84/22
- CPC H04L41/0806
- H04L41/5054
- G06F9/52
- H04L41/14
- CPC H04L41/5054
- H04L45/28
- CPC H04L45/38
- H04L49/109
- H04L49/15
- CPC H04L49/109
- H04L9/40
- CPC H04L63/0428
- H04L65/1069
- H04L67/02
- CPC H04L65/1069
- H04L69/24
- H04L1/00
- CPC H04L69/24
- H04N7/15
- H04W24/08
- CPC H04N7/157
- H04N19/50
- H04N19/105
- H04N19/139
- H04N19/176
- CPC H04N19/50
- H04W28/02
- H04W4/40
- H04W28/16
- H04W72/20
- H04W72/56
- CPC H04W28/0289
- H04W36/32
- H04W36/00
- H04W36/36
- CPC H04W36/322
- H04W52/02
- H04W76/20
- CPC H04W52/0235
- H04W52/36
- CPC H04W52/367
- H04W72/12
- H04W72/23
- CPC H04W72/12
- H10N52/85
- G11C11/16
- H03K19/20
- H10B61/00
- H10N50/10
- H10N50/85
- CPC H10N52/85
