Huawei technologies co., ltd. (20240178187). CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE simplified abstract
Contents
- 1 CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
Organization Name
Inventor(s)
Shanghsuan Chiang of Shenzhen (CN)
CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178187 titled 'CHIP PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF, AND ELECTRONIC DEVICE
Simplified Explanation
The chip package structure described in the patent application includes a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is placed on the substrate, while the conductive columns are located on the periphery of the first connection chip. The first packaging layer wraps around the first connection chip and the conductive columns, exposing their active surface and top surfaces. The first chip is positioned on the first packaging layer and connected to both the conductive columns and the first connection chip. The second chip is also placed on the first packaging layer, away from the substrate, and connected to both the conductive columns and the first connection chip.
- The chip package structure includes a substrate, first connection chip, conductive columns, first packaging layer, first chip, and second chip.
- The first connection chip is on the substrate, while conductive columns are on its periphery.
- The first packaging layer wraps around the first connection chip and conductive columns, exposing their active surface and top surfaces.
- The first chip is on the first packaging layer, connected to both conductive columns and the first connection chip.
- The second chip is on the first packaging layer, away from the substrate, and connected to both conductive columns and the first connection chip.
Potential Applications
The technology described in this patent application could be applied in various electronic devices such as smartphones, tablets, laptops, and other portable electronics where space-saving and efficient chip packaging is crucial.
Problems Solved
This technology solves the problem of efficiently packaging multiple chips in a compact space while ensuring proper connectivity and functionality.
Benefits
The benefits of this technology include space-saving design, improved connectivity, enhanced functionality, and potentially lower production costs due to efficient packaging.
Potential Commercial Applications
- "Innovative Chip Package Structure for Electronic Devices: Enhancing Connectivity and Space Efficiency"
Possible Prior Art
There may be prior art related to chip packaging structures and methods in the semiconductor industry, but specific examples are not provided in this patent application.
Unanswered Questions
How does this technology compare to existing chip packaging methods in terms of cost-effectiveness?
The cost-effectiveness of this technology compared to existing methods is not explicitly addressed in the patent application. Further research or analysis would be needed to determine the cost implications of implementing this chip package structure.
What are the potential challenges or limitations of implementing this chip package structure in mass production?
The patent application does not discuss potential challenges or limitations of mass-producing this chip package structure. Additional studies or testing may be required to identify and address any issues that could arise during large-scale production.
Original Abstract Submitted
a chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. the first connection chip is disposed on the substrate. the conductive columns is disposed on the substrate and located on a periphery of the first connection chip. the first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. the first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. the second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip.
