Huawei technologies co., ltd. (20240178103). Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device simplified abstract
Contents
- 1 Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device
Organization Name
Inventor(s)
Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178103 titled 'Chip Stacked Structure and Manufacturing Method Thereof, Chip Package Structure, and Electronic Device
Simplified Explanation
The patent application describes a chip stacked structure consisting of a first chip and a second chip, with various layers and through silicon vias connecting them.
- The first chip includes a first substrate, a first functional layer, and first through silicon vias. The diameter of the through silicon vias close to the functional layer is greater than those close to the substrate.
- The second chip includes a second substrate and a second functional layer.
- The structure also includes a first redistribution layer, a first dielectric layer, and a plurality of first bonding metal blocks.
Potential Applications
This technology could be applied in:
- Advanced semiconductor devices
- High-performance computing systems
- Data storage solutions
Problems Solved
This technology helps in:
- Improving interconnectivity between chips
- Enhancing overall performance and reliability of stacked structures
Benefits
The benefits of this technology include:
- Increased data transfer speeds
- Enhanced thermal management
- Compact and efficient chip designs
Potential Commercial Applications
The potential commercial applications of this technology could be in:
- Consumer electronics
- Telecommunications equipment
- Automotive systems
Possible Prior Art
One possible prior art for this technology could be the use of through silicon vias in stacked chip structures for improved connectivity and performance.
Unanswered Questions
How does this technology compare to traditional chip stacking methods?
This technology offers improved connectivity and performance compared to traditional methods by utilizing through silicon vias and bonding metal blocks for enhanced interconnectivity.
What are the manufacturing challenges associated with implementing this technology?
Manufacturing challenges may include precise alignment of the layers, controlling the diameter of through silicon vias, and ensuring proper bonding of metal blocks within the structure.
Original Abstract Submitted
a chip stacked structure includes a first chip and a second chip. the first chip includes a first substrate, a first functional layer, and first through silicon vias. a diameter of the first through silicon via close to the first functional layer is greater than a diameter of the first through silicon via close to the first substrate. the second chip includes a second substrate and a second functional layer. the chip stacked structure further includes a first redistribution layer disposed on a side that is of the second functional layer and that is away from the second substrate, a first dielectric layer disposed between the first substrate and the first redistribution layer, and a plurality of first bonding metal blocks disposed in the first dielectric layer.
