Google llc (20240249058). GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKS simplified abstract

GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKS

Organization Name

google llc

Inventor(s)

Anna Darling Goldie of San Francisco CA (US)

Azalia Mirhoseini of Mountain View CA (US)

Ebrahim Songhori of San Jose CA (US)

Wenjie Jiang of Mountain View CA (US)

Shen Wang of Sunnyvale CA (US)

Roger David Carpenter of San Francisco CA (US)

Young-Joon Lee of San Jose CA (US)

Mustafa Nazim Yazgan of Cupertino CA (US)

Chian-min Richard Ho of Palo Alto CA (US)

Quoc V. Le of Sunnyvale CA (US)

James Laudon of Madison WI (US)

Jeffrey Adgate Dean of Palo Alto CA (US)

Kavya Srinivasa Setty of Sunnyvale CA (US)

Omkar Pathak of Mountain View CA (US)

GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240249058 titled 'GENERATING INTEGRATED CIRCUIT PLACEMENTS USING NEURAL NETWORKS

The abstract describes methods, systems, and apparatus for generating a computer chip placement using neural networks.

• Obtaining netlist data for a computer chip.
• Generating a computer chip placement by placing macro nodes in a sequence of time steps.
• Using a node placement neural network to process input representations and generate a score distribution over positions on the chip surface.
• Assigning the macro node to a position based on the score distribution.

Potential Applications: - Semiconductor industry for chip design and manufacturing. - Electronic device manufacturing for optimizing chip layouts.

Problems Solved: - Efficient and automated computer chip placement. - Optimization of chip layout for better performance.

Benefits: - Faster chip design process. - Improved chip performance and functionality.

Commercial Applications: - Semiconductor companies for chip design. - Electronic device manufacturers for optimizing chip layouts.

Questions about the technology: 1. How does the neural network improve the efficiency of computer chip placement? 2. What are the key factors influencing the placement of macro nodes on the chip surface?

Frequently Updated Research: - Stay updated on advancements in neural network algorithms for chip placement optimization.

Original Abstract Submitted

methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. one of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.