FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING: abstract simplified (18331241)

• This abstract for appeared for patent application number 18331241 Titled 'FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING'

Simplified Explanation

The abstract describes a new type of MOSFET (metal-oxide-semiconductor field-effect transistor) called MFMIS-FET. This MOSFET has a three-dimensional structure that allows it to have a larger effective area than the MFM (metal-ferroelectric-metal) or the MOSFET itself. In some cases, the gate electrode of the MOSFET and the bottom electrode of the MFM are combined, and they have equal areas. In other cases, the MFM and the MOSFET have nearly equal footprints. The main advantage of this structure is that it reduces the capacitance ratio between the MFM structure and the MOSFET without decreasing the area of the MFM structure, which would negatively impact the drain current.

Original Abstract Submitted

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.