Decoding Status Flag Techniques for Memory Circuits: abstract simplified (18323178)

• This abstract for appeared for patent application number 18323178 Titled 'Decoding Status Flag Techniques for Memory Circuits'

Simplified Explanation

This abstract describes techniques for improving memory reliability. The memory circuitry includes memory cells, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry checks the read data from the memory cells for errors and corrects any detected correctable errors to generate corrected data. The memory circuitry provides the read data to a requesting circuit through the interface circuitry, including sets of corrected data from the on-die ECC circuitry. Additionally, the memory circuitry provides a decoding status flag (DSF) through the interface circuitry. The DSF is set to a first value when no error is detected, a second value when a correctable error is detected and corrected, and a third value when an uncorrectable error is detected by the on-die ECC circuitry.

Original Abstract Submitted

Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.