Category:Kunal R. Parekh of Boise ID (US)
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Kunal R. Parekh of Boise ID (US)
Executive Summary
Kunal R. Parekh of Boise ID (US) is an inventor who has filed 18 patents. Their primary areas of innovation include the devices being of types provided for in two or more different subgroups of the same main group of groups (7 patents), {Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group (6 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (5 patents), and they have worked with companies such as Micron Technology, Inc. (18 patents). Their most frequent collaborators include (5 collaborations), (5 collaborations), (5 collaborations).
Patent Filing Activity
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Technology Areas
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List of Technology Areas
- H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 7 patents
- H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 6 patents
- H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
- H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
- H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 4 patents
- H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
- H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
- H01L24/73 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
- H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 3 patents
- H10B12/482 (ELECTRONIC MEMORY DEVICES): 3 patents
- H10B12/485 (ELECTRONIC MEMORY DEVICES): 3 patents
- H10B12/488 (ELECTRONIC MEMORY DEVICES): 3 patents
- H10B80/00 (Assemblies of multiple devices comprising at least one memory device covered by this subclass): 2 patents
- H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L24/06 ({of a plurality of bonding areas}): 2 patents
- H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L2224/73204 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L21/76877 ({Thin films associated with contacts of capacitors}): 2 patents
- H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H10B41/27 (ELECTRONIC MEMORY DEVICES): 2 patents
- H10B41/35 (ELECTRONIC MEMORY DEVICES): 2 patents
- H01L2225/06517 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 2 patents
- H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H10B12/33 (ELECTRONIC MEMORY DEVICES): 2 patents
- H10B12/036 (ELECTRONIC MEMORY DEVICES): 2 patents
- H01L2224/83895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L2224/83896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
- H01L2924/1434 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/0557 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/06181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/96 ({the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting}): 1 patents
- H01L2224/96 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L24/92 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/92125 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/9222 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/29 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
- H01L21/50 (Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups): 1 patents
- H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
- H01L27/0688 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- G11C7/18 (STATIC STORES (semiconductor memory devices): 1 patents
- H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
- H01L2924/1443 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/49575 (Lead-frames {or other flat leads (): 1 patents
- H01L23/492 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/66 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L23/49513 (Lead-frames {or other flat leads (): 1 patents
- H01L23/49805 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L2225/0651 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06548 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06582 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10B43/40 (ELECTRONIC MEMORY DEVICES): 1 patents
- H01L23/53228 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10B41/41 (ELECTRONIC MEMORY DEVICES): 1 patents
- H10B43/27 (ELECTRONIC MEMORY DEVICES): 1 patents
- H10B43/35 (ELECTRONIC MEMORY DEVICES): 1 patents
- H01L2224/05124 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/05025 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- G06F3/064 ({Management of blocks}): 1 patents
- G06F1/06 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
- G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
- G06F3/0683 ({Plurality of storage devices}): 1 patents
- H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L23/49833 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
- H01L23/5382 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
- H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
- H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
- H01L2225/06513 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2225/06589 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16148 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/16238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/32145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L21/308 (using masks (): 1 patents
- G11C29/56004 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 1 patents
- G11C29/56016 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C2029/5602 (STATIC STORES (semiconductor memory devices): 1 patents
- H01L28/60 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/05647 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/0603 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/80201 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/80357 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2224/80379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/04642 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/0504 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/0544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H01L2924/059 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
- H10B12/50 (ELECTRONIC MEMORY DEVICES): 1 patents
- H10B12/315 (ELECTRONIC MEMORY DEVICES): 1 patents
- H10B12/0335 (ELECTRONIC MEMORY DEVICES): 1 patents
- G11C29/52 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/022 (STATIC STORES (semiconductor memory devices): 1 patents
- G11C29/025 (STATIC STORES (semiconductor memory devices): 1 patents
- H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
Companies
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List of Companies
- Micron Technology, Inc.: 18 patents
Collaborators
- James Brian Johnson of Boise ID (US) (5 collaborations)
- Brent Keeth of Boise ID (US) (5 collaborations)
- Amy Rae Griffin of Boise ID (US) (5 collaborations)
- Eiichi Nakano of Boise ID (US) (5 collaborations)
- Kyle K. Kirby of Eagle ID (US) (4 collaborations)
- Ameen D. Akel of Rancho Cordova CA (US) (3 collaborations)
- Terrence B. McDaniel of Boise ID (US) (3 collaborations)
- Fatma Arzum Simsek-Ege of Boise ID (US) (3 collaborations)
- Thiagarajan Raman of Boise ID (US) (2 collaborations)
- Bret K. Street of Meridian ID (US) (2 collaborations)
- Wei Zhou of Boise ID (US) (2 collaborations)
- Bharat Bhushan (1 collaborations)
- Akshay N. Singh of Boise ID (US) (1 collaborations)
- Jaekyu Song of Boise ID (US) (1 collaborations)
- Beau D. Barry of Boise ID (US) (1 collaborations)
Subcategories
This category has the following 2 subcategories, out of 2 total.
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Pages in category "Kunal R. Parekh of Boise ID (US)"
The following 23 pages are in this category, out of 23 total.
1
- 17821676. MEMORY WITH PARALLEL MAIN AND TEST INTERFACES simplified abstract (Micron Technology, Inc.)
- 17884475. SUBSTRATE FOR VERTICALLY ASSEMBLED SEMICONDUCTOR DIES simplified abstract (Micron Technology, Inc.)
- 17884484. THROUGH-SUBSTRATE CONNECTIONS FOR RECESSED SEMICONDUCTOR DIES simplified abstract (Micron Technology, Inc.)
- 18237259. SEMICONDUCTOR DEVICE WITH CIRCUIT COMPONENTS FORMED THROUGH INTER-DIE CONNECTIONS simplified abstract (Micron Technology, Inc.)
- 18315311. INTERFACES BETWEEN HIGHER VOLTAGE AND LOWER VOLTAGE WAFERS AND RELATED APPARATUSES AND METHODS simplified abstract (Micron Technology, Inc.)
- 18400745. FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)
- 18400994. TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY simplified abstract (Micron Technology, Inc.)
- 18426271. STACKED SEMICONDUCTOR DEVICE simplified abstract (Micron Technology, Inc.)
- 18478031. MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS simplified abstract (Micron Technology, Inc.)
- 18491711. MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS simplified abstract (Micron Technology, Inc.)
- 18507721. FRONT END OF LINE INTERCONNECT STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS simplified abstract (Micron Technology, Inc.)
- 18516734. TECHNIQUES FOR COUPLED HOST AND MEMORY DIES simplified abstract (Micron Technology, Inc.)
- 18525403. REPAIR TECHNIQUES FOR COUPLED MEMORY DIES simplified abstract (Micron Technology, Inc.)
- 18600146. MEMORY DEVICES AND RELATED METHODS OF FORMING A MEMORY DEVICE simplified abstract (Micron Technology, Inc.)
- 18649986. SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT simplified abstract (Micron Technology, Inc.)
M
- Micron technology, inc. (20240176523). TECHNIQUES FOR COUPLED HOST AND MEMORY DIES simplified abstract
- Micron technology, inc. (20240186274). TECHNIQUES FOR THERMAL DISTRIBUTION IN COUPLED SEMICONDUCTOR SYSTEMS simplified abstract
- Micron technology, inc. (20240194287). REPAIR TECHNIQUES FOR COUPLED MEMORY DIES simplified abstract
- Micron technology, inc. (20240237363). TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY simplified abstract
- Micron technology, inc. (20240282620). SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT simplified abstract
- Micron technology, inc. (20240297149). STACKED SEMICONDUCTOR DEVICE simplified abstract
Categories:
- James Brian Johnson of Boise ID (US)
- Brent Keeth of Boise ID (US)
- Amy Rae Griffin of Boise ID (US)
- Eiichi Nakano of Boise ID (US)
- Kyle K. Kirby of Eagle ID (US)
- Ameen D. Akel of Rancho Cordova CA (US)
- Terrence B. McDaniel of Boise ID (US)
- Fatma Arzum Simsek-Ege of Boise ID (US)
- Thiagarajan Raman of Boise ID (US)
- Bret K. Street of Meridian ID (US)
- Wei Zhou of Boise ID (US)
- Bharat Bhushan
- Akshay N. Singh of Boise ID (US)
- Jaekyu Song of Boise ID (US)
- Beau D. Barry of Boise ID (US)
- Kunal R. Parekh of Boise ID (US)
- Inventors
- Inventors filing patents with Micron Technology, Inc.
