Category:Jiun Yi Wu

Jiun Yi Wu

Executive Summary

Jiun Yi Wu is an inventor who has filed 11 patents. Their primary areas of innovation include {Multilayer substrates (multilayer metallisation on monolayer substrate (4 patents), Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups (4 patents), Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (11 patents). Their most frequent collaborators include (9 collaborations), (4 collaborations), (3 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 4 patents
• H01L21/4857 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 4 patents
• H01L23/49833 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 4 patents
• H01L23/49816 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 3 patents
• H01L23/5389 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 3 patents
• H01L21/4853 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 3 patents
• H01L23/3128 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/5383 ({Multilayer substrates (): 3 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 2 patents
• H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/81 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/16225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/565 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 2 patents
• H01L2224/214 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/31 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/49827 ({Via connections through the substrates, e.g. pins going through the substrate, coaxial cables (): 2 patents
• H01L23/49811 ({Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads (): 2 patents
• H01L24/16 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/3114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 2 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/563 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/566 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76816 ({Aspects relating to the layout of the pattern or to the size of vias or trenches (layout of the interconnections per se): 1 patents
• H01L23/3157 ({Partial encapsulation or coating (mask layer used as insulation layer): 1 patents
• H01L24/13 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68345 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68359 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68381 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02331 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/13101 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/13111 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/13147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/13155 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/73204 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/81005 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/81193 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/81801 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1436 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/15311 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/18161 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G02B6/12004 (of the integrated circuit kind (electric integrated circuits): 1 patents
• G02B6/262 (Optical coupling means (): 1 patents
• G02B6/4239 (Coupling light guides with opto-electronic elements): 1 patents
• G02B2006/12102 (OPTICAL ELEMENTS, SYSTEMS OR APPARATUS): 1 patents
• G02B2006/12104 (OPTICAL ELEMENTS, SYSTEMS OR APPARATUS): 1 patents
• H01L21/568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/19 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/20 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68372 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1431 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1434 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/19106 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
• H01L21/56 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2021/60022 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49866 ({characterised by the materials (materials of the substrates): 1 patents
• H01L23/49894 (Leads, {i.e. metallisations or lead-frames} on insulating substrates, {e.g. chip carriers (shape of the substrate): 1 patents
• H01L2224/16227 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/29 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/14 ({of a plurality of bump connectors}): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/14 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/8234 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/35 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/211 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/2101 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/2902 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/14104 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/8134 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/49861 ({Lead-frames fixed on or encapsulated in insulating substrates (): 1 patents
• H01L2224/82896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/17 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/73 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0231 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02373 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/02379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents

Companies

List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 11 patents

Collaborators

• Chen-Hua Yu (9 collaborations)
• Chung-Shi Liu (4 collaborations)
• Chien-Hsun Lee (3 collaborations)
• Yu-Min Liang (2 collaborations)
• Wei-Yu Chen (2 collaborations)
• Hao-Cheng Hou (1 collaborations)
• Hung-Jen Lin (1 collaborations)
• Jung Wei Cheng (1 collaborations)
• Tsung-Ding Wang (1 collaborations)
• Li-Wei Chou (1 collaborations)
• Szu-Wei Lu (1 collaborations)
• Chun-Chih Chuang (1 collaborations)
• Kuan-Lin Ho (1 collaborations)
• Shang-Yun Hou (1 collaborations)