Category:Jerome TEYSSEYRE

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Jerome TEYSSEYRE

Executive Summary

Jerome TEYSSEYRE is an inventor who has filed 7 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), and they have worked with companies such as SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (7 patents). Their most frequent collaborators include (2 collaborations), (2 collaborations), (2 collaborations).

Patent Filing Activity

Jerome TEYSSEYRE Monthly Patent Applications.png

Technology Areas

Jerome TEYSSEYRE Top Technology Areas.png

List of Technology Areas

  • H01L21/56 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L25/072 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L23/3121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/49555 (Lead-frames {or other flat leads (): 2 patents
  • H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 2 patents
  • H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 2 patents
  • H01L23/3735 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/3107 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/367 (Cooling facilitated by shape of device {(): 1 patents
  • H01L23/5389 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L24/24 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/82 ({by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] (interconnection structure between a plurality of semiconductor chips): 1 patents
  • H01L23/3677 (Cooling facilitated by shape of device {(): 1 patents
  • H01L23/467 (by flowing gases, e.g. air {(): 1 patents
  • H01L23/473 (by flowing liquids {(): 1 patents
  • H01L21/52 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/3114 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/3135 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/4334 ({Auxiliary members in encapsulations (): 1 patents
  • H01L23/49822 ({Multilayer substrates (multilayer metallisation on monolayer substrate): 1 patents
  • H01L24/20 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L29/861 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/72 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/90 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/492 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/4853 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
  • H01L21/4875 (Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups): 1 patents
  • H01L23/14 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/49811 ({Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads (): 1 patents
  • H01L23/50 (for integrated circuit devices, {e.g. power bus, number of leads} (): 1 patents
  • H01L24/06 ({of a plurality of bonding areas}): 1 patents
  • H01L24/14 ({of a plurality of bump connectors}): 1 patents
  • H01L23/5383 ({Multilayer substrates (): 1 patents
  • H01L25/0655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01R12/585 (terminals for insertion into holes): 1 patents

Companies

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List of Companies

  • SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC: 7 patents

Collaborators

Subcategories

This category has the following 8 subcategories, out of 8 total.

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