Category:Frederick A. Ware of Los Altos Hills CA (US)

Frederick A. Ware of Los Altos Hills CA (US)

Executive Summary

Frederick A. Ware of Los Altos Hills CA (US) is an inventor who has filed 20 patents. Their primary areas of innovation include {Single storage device} (8 patents), {Command handling arrangements, e.g. command buffers, queues, command scheduling} (5 patents), Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} (5 patents), and they have worked with companies such as Rambus Inc. (19 patents), RAMBUS INC. (1 patents). Their most frequent collaborators include (3 collaborations), (3 collaborations), (3 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• G06F3/0673 ({Single storage device}): 8 patents
• G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 5 patents
• G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 5 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 4 patents
• G11C29/52 (STATIC STORES (semiconductor memory devices): 4 patents
• G06F11/1068 ({in sector programmable memories, e.g. flash disk (): 3 patents
• G11C7/10 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 3 patents
• Y02D10/00 (No explanation available): 3 patents
• G11C11/4093 (Input/output [I/O] data interface arrangements, e.g. data buffers): 3 patents
• G11C5/04 (Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports): 3 patents
• G06F13/1673 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 3 patents
• G06F11/1076 ({Parity data used in redundant arrays of independent storages, e.g. in RAID systems}): 2 patents
• G06F13/1678 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
• G06F3/0634 ({by changing the state or mode of one or more devices}): 2 patents
• G06F3/0656 ({Data buffering arrangements}): 2 patents
• G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 2 patents
• G06F11/073 (Responding to the occurrence of a fault, e.g. fault tolerance): 2 patents
• G06F11/1044 ({with specific ECC/EDC distribution}): 2 patents
• G06F11/1048 ({using arrangements adapted for a specific error detection or correction feature}): 2 patents
• G06F13/1668 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 2 patents
• G11C11/4076 (Timing circuits (for regeneration management): 2 patents
• G11C11/4087 ({Address decoders, e.g. bit - or word line decoders; Multiple line decoders}): 2 patents
• G06F11/20 (using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements): 2 patents
• G06F12/02 (Addressing or allocation; Relocation (program address sequencing): 1 patents
• G06F12/0292 ({using tables or multilevel address translation means (): 1 patents
• G06F3/0638 ({Organizing or formatting or addressing of data}): 1 patents
• G11C7/1006 ({Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}): 1 patents
• G11C7/1009 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/1087 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/109 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/1093 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C29/023 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/028 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C2029/0411 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C2207/107 (STATIC STORES (semiconductor memory devices): 1 patents
• G06F3/0613 ({in relation to throughput}): 1 patents
• G06F11/1004 ({to protect a block of data words, e.g. CRC or checksum (): 1 patents
• G06F12/0868 (Data transfer between cache memory and other subsystems, e.g. storage devices or host systems): 1 patents
• G06F12/0888 (using selective caching, e.g. bypass): 1 patents
• G06F13/28 (using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (): 1 patents
• G06F2212/1016 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/1032 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/403 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F13/1684 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F13/4027 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F11/0751 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0784 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0772 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/2007 ({using redundant communication media}): 1 patents
• G06F11/1658 ({Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit}): 1 patents
• G06F11/079 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 1 patents
• G11C17/16 (using electrically-fusible links): 1 patents
• G11C17/18 (Auxiliary circuits, e.g. for writing into memory): 1 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 1 patents
• H01L25/18 (the devices being of types provided for in two or more different subgroups of the same main group of groups): 1 patents
• H01L2224/05552 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05568 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08148 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/8013 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80132 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80897 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06527 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/00014 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/0002 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/10253 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/14 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G06F13/4282 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• G06F13/1694 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F13/1689 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F12/0253 ({Garbage collection, i.e. reclamation of unreferenced memory}): 1 patents
• G06F12/0246 ({in block erasable memory, e.g. flash memory}): 1 patents
• G06F12/08 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G06F12/0802 (Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches): 1 patents
• G06F12/0804 (with main memory updating (): 1 patents
• G06F12/0891 (using clearing, invalidating or resetting means): 1 patents
• G06F12/1009 (Address translation): 1 patents
• G06F2212/1036 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/2022 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/60 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/7201 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/7205 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F2212/7211 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G11C11/40611 (STATIC STORES (semiconductor memory devices): 1 patents
• G06F13/1636 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G11C11/406 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C11/40615 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C11/40618 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C2211/4067 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 1 patents
• G11C7/08 (Control thereof): 1 patents
• G11C5/025 ({Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits,): 1 patents
• G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 1 patents
• G11C7/06 (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 1 patents
• G11C7/065 (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 1 patents
• G11C7/12 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C7/222 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management): 1 patents
• G11C8/08 (Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines): 1 patents
• G11C8/10 (Decoders): 1 patents
• G06F11/2094 ({Redundant storage or storage space (): 1 patents
• G06F2201/82 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models): 1 patents
• G06F3/064 ({Management of blocks}): 1 patents
• G06F11/006 ({Identification (): 1 patents
• G06F11/0745 (Responding to the occurrence of a fault, e.g. fault tolerance): 1 patents
• G06F11/0766 ({Error or fault reporting or storing}): 1 patents
• G06F11/0793 ({Remedial or corrective actions (recovery from an exception in an instruction pipeline): 1 patents
• G06F11/10 (Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's): 1 patents
• G06F11/1008 ({in individual solid state devices (): 1 patents
• G06F11/1402 ({Saving, restoring, recovering or retrying}): 1 patents
• G06F11/141 (Error detection or correction of the data by redundancy in operation (): 1 patents
• G06F11/1443 ({Transmit or communication errors}): 1 patents
• H03M13/03 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H04L1/004 ({by using forward error control (): 1 patents
• H04L1/0057 ({Block codes (): 1 patents
• H04L1/0061 ({Trellis-coded modulation}): 1 patents
• H04L1/0072 ({Error control for data other than payload data, e.g. control data}): 1 patents
• H04L1/08 (by repeating transmission, e.g. Verdan system {(): 1 patents
• H04L1/1809 (Automatic repetition systems, e.g. Van Duuren systems): 1 patents
• G06F13/00 (Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices): 1 patents
• G06F13/4243 (Bus transfer protocol, e.g. handshake; Synchronisation): 1 patents
• G06F3/0611 ({in relation to response time}): 1 patents
• G06F12/0607 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (): 1 patents
• G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
• G06F3/0629 ({Configuration or reconfiguration of storage systems}): 1 patents
• G06F11/1666 ({where the redundant component is memory or memory area}): 1 patents
• G11C29/42 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/4401 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/70 ({Masking faults in memories by using spares or by reconfiguring}): 1 patents
• H03M13/1575 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• G06F3/0647 ({Migration mechanisms}): 1 patents
• G11C8/18 (Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals): 1 patents
• G11C2207/2245 (STATIC STORES (semiconductor memory devices): 1 patents

Companies

List of Companies

• Rambus Inc.: 19 patents
• RAMBUS INC.: 1 patents

Collaborators

• Thomas Vogelsang of Mountain View CA (US) (3 collaborations)
• John Eric Linstadt of Palo Alto CA (US) (3 collaborations)
• Ely Tsern of Los Altos CA (US) (3 collaborations)
• Scott C. Best of Palo Alto CA (US) (3 collaborations)
• Craig E. Hampel of Los Altos CA (US) (2 collaborations)
• Kenneth L. Wright of Sunnyvale CA (US) (2 collaborations)
• Ely K. Tsern of Los Altos CA (US) (2 collaborations)
• Brent S. Haukness of Sunnyvale CA (US) (2 collaborations)
• Craig Hampel of Los Altos CA (US) (1 collaborations)
• Thomas J. Giovannini of San Jose CA (US) (1 collaborations)
• John Yan of San Jose CA (US) (1 collaborations)
• Brent Haukness of Sunnyvale CA (US) (1 collaborations)
• Brent Haukness of Monte Sereno CA (US) (1 collaborations)
• James E. Harris of Tyler TX (US) (1 collaborations)
• Ian P. Shaeffer of Los Gatos CA (US) (1 collaborations)
• Mark A. Horowitz of Menlo Park CA (US) (1 collaborations)
• Abhijit Abhyankar of Sunnyvale CA (US) (1 collaborations)
• Suresh Rajan of San Jose CA (US) (1 collaborations)
• Christopher Haywood of Fernandina Beach FL (US) (1 collaborations)
• Liji Gopalakrishnan of Sunnyvale CA (US) (1 collaborations)
• Michael Raymond Miller of Raleigh NC (US) (1 collaborations)
• Collins Williams of Raleigh NC (US) (1 collaborations)