Category:Bongsub Lee of Santa Clara CA (US)

Bongsub Lee of Santa Clara CA (US)

Executive Summary

Bongsub Lee of Santa Clara CA (US) is an inventor who has filed 4 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor} (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (4 patents). Their most frequent collaborators include (3 collaborations), (3 collaborations), (2 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 3 patents
• H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 3 patents
• H01L21/76898 ({formed through a semiconductor substrate}): 3 patents
• H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/4824 (consisting of lead-in layers inseparably applied to the semiconductor body {(electrodes): 2 patents
• H01L21/76843 ({formed in openings in a dielectric}): 2 patents
• H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 2 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2225/06544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/06 ({of a plurality of bonding areas}): 1 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents
• H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05184 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• B32B15/016 (all layers being exclusively metallic {(making layered metal workpieces by pressure cladding): 1 patents
• B32B3/266 ({characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells): 1 patents
• B32B3/30 (characterised by a layer formed with recesses or projections, e.g. {hollows, grooves, protuberances, ribs (apertured layer): 1 patents
• B32B15/017 (all layers being exclusively metallic {(making layered metal workpieces by pressure cladding): 1 patents
• B32B15/20 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2250/02 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2307/202 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2307/206 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2311/22 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2311/24 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents

Companies

List of Companies

• ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 4 patents

Collaborators

• Guilian Gao of San Jose CA (US) (3 collaborations)
• Cyprian Emeka Uzoh of San Jose CA (US) (3 collaborations)
• Gaius Gillman Fountain, JR. of Youngsville NC (US) (2 collaborations)
• Laura Wills Mirkarimi of Sunol CA (US) (2 collaborations)
• Belgacem Haba of Saratoga CA (US) (2 collaborations)
• Rajesh Katkar of Milpitas CA (US) (2 collaborations)
• Oliver Zhao of Sunnyvale CA (US) (1 collaborations)