Boe technology group co., ltd. (20240185936). SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE simplified abstract

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SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

Organization Name

boe technology group co., ltd.

Inventor(s)

Haigang Qing of Beijing (CN)

Yunsheng Xiao of Beijing (CN)

SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240185936 titled 'SHIFT REGISTER AND DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT, AND DISPLAY DEVICE

Simplified Explanation

The patent application describes a shift register and a driving method, a gate driving circuit, and a display device. The shift register includes various circuits to control the input and output of voltage signals.

  • Input circuit for inputting voltage to a first node
  • Control circuits for outputting control signals to output nodes
  • Output circuit for writing voltage signals into output terminals
    • Potential Applications:**

- Display devices - Electronic signage - LED screens

    • Problems Solved:**

- Efficient control of voltage signals - Precise output of voltage signals - Improved display quality

    • Benefits:**

- Enhanced display performance - Energy efficiency - Reduced signal interference

    • Potential Commercial Applications of this Technology:**

- Consumer electronics - Automotive displays - Industrial control panels

    • Possible Prior Art:**

- Shift registers in display devices - Gate driving circuits in electronic devices

    • Unanswered Questions:**

1. How does this technology compare to existing shift register designs in terms of speed and efficiency? 2. Are there any specific limitations or drawbacks to using this shift register in certain display applications?


Original Abstract Submitted

a shift register and a driving method thereof, a gate driving circuit, and a display device are provided. the shift register includes: an input circuit configured to input an input voltage to a first node under control of a first clock signal; a first control circuit configured to output a first control signal to a first output node under control of the first clock signal, a voltage of the first node, and a second clock signal; a second control circuit configured to output a second control signal to the second output node under control of the voltage of the first node; and an output circuit configured to write a first voltage signal or a second voltage signal into a first output terminal as a first output signal under control of the first control signal and the second control signal.