Boe technology group co., ltd. (20240178238). ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL simplified abstract
Contents
- 1 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
Organization Name
boe technology group co., ltd.
Inventor(s)
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178238 titled 'ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
Simplified Explanation
The array substrate described in the patent application includes gate lines, data lines, pixel units with thin film transistors, conductive layers, insulating layers, wiring patterns, interconnection patterns, via holes, and auxiliary lines.
- Gate lines and data lines are located on the base of the array substrate.
- Each pixel unit contains a thin film transistor.
- The first conductive layer includes a wiring pattern connected to the data lines.
- The second conductive layer includes an interconnection pattern connected to the wiring pattern.
- Orthographic projections of the wiring pattern and interconnection pattern overlap on the base.
- Data lines have auxiliary lines formed by the interconnection pattern in the second conductive layer.
- At least one of the data line and the interconnection pattern is connected to a source of the thin film transistor through a via hole.
Potential Applications
The technology described in the patent application could be used in the manufacturing of high-resolution displays, such as LCD screens, OLED panels, and touchscreens.
Problems Solved
This technology helps in improving the efficiency and performance of array substrates used in electronic displays by optimizing the layout of gate lines, data lines, and interconnection patterns.
Benefits
The benefits of this technology include enhanced image quality, increased pixel density, reduced power consumption, and improved overall reliability of electronic displays.
Potential Commercial Applications
"Optimized Layout Design for Array Substrates in Electronic Displays"
Possible Prior Art
One possible prior art for this technology could be the use of similar conductive layers and wiring patterns in the manufacturing of array substrates for electronic displays.
What materials are used in the fabrication of the array substrate described in the patent application?
The materials used in the fabrication of the array substrate include a base, conductive layers, insulating layers, and thin film transistors. These materials are essential for the proper functioning of the display panel.
How does the layout design of the array substrate contribute to the overall performance of the electronic display?
The layout design of the array substrate plays a crucial role in optimizing the connection between gate lines, data lines, and thin film transistors. This optimized layout design helps in improving the efficiency, resolution, and reliability of the electronic display.
Original Abstract Submitted
an array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. the first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. the first wiring pattern is connected with the first interconnection pattern through a via hole. each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. the first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.
