Boe technology group co., ltd. (20240162247). DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE simplified abstract

DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE

Organization Name

boe technology group co., ltd.

Inventor(s)

Fuqiang Li of Beijing (CN)

Zhen Zhang of Beijing (CN)

Zhenyu Zhang of Beijing (CN)

Lizhong Wang of Beijing (CN)

Ce Ning of Beijing (CN)

Yunping Di of Beijing (CN)

Zheng Fang of Beijing (CN)

Jiahui Han of Beijing (CN)

Chenyang Zhang of Beijing (CN)

Yawei Wang of Beijing (CN)

Chengfu Xu of Beijing (CN)

DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240162247 titled 'DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE

Simplified Explanation

The patent application describes a thin film transistor and its manufacturing method, as well as a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer, and a gate layer stacked together. The active layer consists of a source contact area, a drain contact area, and a channel area connecting the two contact areas. The channel area is further divided into a first channel area, a first resistance area, and a second channel area in a specific direction. The gate layer includes a first gate and a second gate, each covering a respective channel area when projected onto the plane where the active layer is located.

• The thin film transistor includes an active layer, a first insulating layer, and a gate layer stacked in a specific order.
• The active layer comprises a source contact area, a drain contact area, and a channel area connecting them.
• The channel area is divided into a first channel area, a first resistance area, and a second channel area.
• The gate layer consists of a first gate and a second gate, each covering a specific channel area when projected onto the active layer plane.

Potential Applications

The technology described in the patent application could be applied in the manufacturing of advanced display panels, touchscreens, and electronic devices requiring high-performance thin film transistors.

Problems Solved

This technology solves the problem of improving the efficiency and performance of thin film transistors by optimizing the layout and design of the active layer and gate layer.

Benefits

The benefits of this technology include enhanced display quality, increased device reliability, and improved energy efficiency in electronic devices utilizing thin film transistors.

Potential Commercial Applications

The technology has potential commercial applications in the consumer electronics industry, particularly in the production of smartphones, tablets, laptops, and other display devices.

Possible Prior Art

One possible prior art in this field is the development of thin film transistors with optimized channel designs and gate configurations to enhance device performance and reliability.

How does this technology compare to existing thin film transistor designs in terms of performance and efficiency?

The article does not provide a direct comparison between this technology and existing thin film transistor designs. Further research and testing would be needed to evaluate the performance and efficiency differences.

What are the potential challenges in implementing this technology on a large scale for commercial production?

The article does not address the potential challenges in scaling up this technology for commercial production. Factors such as cost, manufacturing processes, and compatibility with existing production lines would need to be considered.

Original Abstract Submitted

disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. the thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.