Arm Limited patent applications on April 3rd, 2025

Patent Applications by Arm Limited on April 3rd, 2025

Arm Limited: 15 patent applications

Arm Limited has applied for patents in the areas of G06T1/20 (7), G06T15/00 (2), G06F12/02 (2), G06T1/60 (2), G06T5/00 (2) G06T1/20 (5), G06T15/005 (2), G06F9/3885 (1), G06F12/023 (1), G06F12/0808 (1)

With keywords such as: data, rendering, texture, outputs, cache, processing, tasks, render, graphics, and stream in patent application abstracts.

Patent Applications by Arm Limited

20250110747. PARALLEL PROCESSING CONTROL_simplified_abstract_(arm limited)

Inventor(s): Maochang Dang of Shanghai CN for arm limited, Andreas Danner Nilsen of Trondheim NO for arm limited, Mark Underwood of Cambridge GB for arm limited, Brian Gordon Pearson of Trøndelag NO for arm limited, Espen Amodt of Shanghai CN for arm limited, Xinyu Chen of Trondheim NO for arm limited

IPC Code(s): G06F9/38, G06F9/30

CPC Code(s): G06F9/3885

Abstract: a method of preparing a command stream for a parallel processor, comprising: analysing the command stream to detect at least a first dependency; generating at least one timeline dependency point responsive to detecting the first dependency; determining a latest action for the first dependency to derive a completion stream timeline point for the first dependency; comparing the completion stream timeline point for the first dependency with a completion stream timeline point for a second dependency to determine a latest stream timeline point; generating at least one command stream synchronization control instruction according to the latest stream timeline point; and providing the command stream and the at least one command stream synchronization control instruction to an execution unit of the parallel processor.

20250110863. ACCESS REQUESTS TO LOCAL STORAGE CIRCUITRY_simplified_abstract_(arm limited)

Inventor(s): . ABHISHEK RAJA of Niagara Falls NY US for arm limited

IPC Code(s): G06F12/02

CPC Code(s): G06F12/023

Abstract: there is provided an apparatus, system, chip-containing product, method, and storage medium. the apparatus comprises memory access circuitry responsive to one or more types of memory access request, to retrieve specified data items from memory. the apparatus is also provided with local storage circuitry configured to store at least some of the retrieved data items. the local storage circuitry is n-way associative, and n is greater than 1. the apparatus is also provided with control circuitry responsive to an indication that an access request signalled to the local storage circuitry relating to an accessed data item corresponds to a predefined type of memory access request, to implement a restrictive access policy in relation to the accessed data item in the local storage circuitry. the restrictive access policy excludes at least one step of accessing an excluded subset of ways of the local storage circuitry.

20250110874. CACHE LOOKUP RESPONSE FILTERING_simplified_abstract_(arm limited)

Inventor(s): Fabrice Jean VERPLANKEN of Sheffield GB for arm limited, Rakesh RAMAN of Sheffield GB for arm limited, Nikita PrakashChandra BHANDARI of Austin TX US for arm limited

IPC Code(s): G06F12/0808, G06F12/02, G06F13/18

CPC Code(s): G06F12/0808

Abstract: cache invalidation circuitry responds to a cache invalidation command specifying invalidation scope information indicative of at least one invalidation condition, to control a cache to perform an invalidation process to invalidate cache entries satisfying the invalidation condition(s). cache lookup circuitry issues to the cache a cache lookup request specifying address information, to request that the cache returns a cache lookup response. cache lookup response filtering circuitry is responsive to a given hit-indicating cache lookup response which provides cached information and invalidation qualifying information returned from a corresponding valid cache entry, to determine whether the given hit-indicating cache lookup response conflicts with an in-progress cache invalidation command, based on the invalidation scope information specified by the in-progress cache invalidation command and the invalidation qualifying information, and when conflict is detected, causes the given hit-indicating cache lookup response to be treated as a miss-indicating cache lookup response.

20250111462. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Olof Henrik Uhrenholt of Lomma SE for arm limited, Philip Carlos Garcia of Austin TX US for arm limited, Mark Underwood of Cambridge GB for arm limited

IPC Code(s): G06T1/20

CPC Code(s): G06T1/20

Abstract: when generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced. in particular, there is disclosed a mechanism for suspending the sequence of rendering jobs (so that it may subsequently be resumed).

20250111463. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Olof Henrik Uhrenholt of Lomma SE for arm limited, Andreas Due Engh-Halstvedt of Trondheim NO for arm limited, Philip Carlos Garcia of Austin TX US for arm limited, Wing-Tsi Henry Wong of Lund SE for arm limited, Sandeep Kala of Cambridge GB for arm limited, Joseph Michael Richardson of Cambridge GB for arm limited

IPC Code(s): G06T1/20

CPC Code(s): G06T1/20

Abstract: when generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks from different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks for the different render outputs are enforced.

20250111464. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Mark Underwood of Cambridge GB for arm limited, Wing-Tsi Henry Wong of Lund SE for arm limited, Olof Henrik Uhrenholt of Lomma SE for arm limited, Philip Carlos Garcia of Austin TX US for arm limited, Daren Croxford of Swaffham Prior GB for arm limited

IPC Code(s): G06T1/20

CPC Code(s): G06T1/20

Abstract: when performing a sequence of rendering jobs, rendering tasks for separate rendering jobs are permitted to overlap within the graphics processor's processing (shader) cores. a record is maintained of which rendering tasks are currently being processed by the graphics processor's processing (shader) cores which record can then be used to enforce any data (processing) dependencies between different rendering jobs.

20250111465. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Olof Henrik Uhrenholt of Lomma SE for arm limited, Thomas Weber of Trondheim NO for arm limited

IPC Code(s): G06T1/20

CPC Code(s): G06T1/20

Abstract: a method of managing write-after-read (war) hazards in a graphics processor. a host processor when preparing a graphics processor command stream can identify possible war hazards between rendering jobs for example by detecting layout transitions and insert a suitable barrier into the graphics processor command stream. the graphics processor when encountering such a barrier can then determine whether it is possible to ignore the barrier and allow rendering jobs to be processed concurrently.

20250111467. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Olof Henrik Uhrenholt of Lomma SE for arm limited, Mark Underwood of Cambridge GB for arm limited, Daren Croxford of Swaffham Prior GB for arm limited, Joseph Michael Richardson of Cambridge GB for arm limited

IPC Code(s): G06T1/20, G06T1/60

CPC Code(s): G06T1/20

Abstract: when generating a sequence of render outputs using a graphics processor, the completion status of rendering tasks for different render outputs is tracked so that processing tasks for later render outputs in the sequence of outputs can be processed concurrently with processing tasks for earlier render outputs in the sequence of outputs whilst ensuring that any dependencies between the rendering tasks are enforced.

20250111540. IMAGE DATA PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Maxim NOVIKOV of Manchester GB for arm limited, Liam O'NEIL of Manchester GB for arm limited, Yanxiang WANG of Manchester GB for arm limited, Joshua James SOWERBY of Cambridge GB for arm limited

IPC Code(s): G06T9/00, G06T5/00, G06T5/50, G06T7/11

CPC Code(s): G06T9/00

Abstract: a method and system for processing image data having a first bit depth using at least one trained neural network configured to operate on data having a second bit depth, where the second bit depth is smaller than the first bit depth by generating a plurality of image data portions by splitting the image data. each of the plurality of image data portions is encoded to produce a plurality of encoded image data portions having the second bit depth. the plurality of image data portions are then processed by at least one trained neural network, before being decoded and combined to produce composite image data. the composite image data is then output.

20250111555. GRAPHICS TEXTURE PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Edvard Fielding of Trondheim NO for arm limited, Rodolfo Luis Jalabert Castellanos of Trondheim NO for arm limited, Jorn Nystad of Trondheim NO for arm limited

IPC Code(s): G06T11/00, G06T1/20, G06T1/60

CPC Code(s): G06T11/001

Abstract: when performing texture processing operations in a graphics processing system, for a texture processing operation that requires m input texture data elements from an array of texture data elements, each of the m texture data elements is selected from a different set of texture data elements having a different set of positions within the texture data array. the texture processing operation is then performed using the m texture data elements.

20250111576. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Rafal Stepuch of Cambridge GB for arm limited, Andreas Due Engh-Halstvedt of Trondheim NO for arm limited, Frank Klaeboe Langtind of Melhus NO for arm limited

IPC Code(s): G06T15/00, G06T15/04

CPC Code(s): G06T15/005

Abstract: when preparing and storing primitive lists in a tile-based graphics processing system, one or more primitive list pointer arrays store pointers, each pointer indicating a location in storage of one or more of the primitive lists. a further pointer array stores further pointers, each further pointer indicating a location in storage of one or more of the primitive list pointer arrays.

20250111577. GRAPHICS PROCESSING_simplified_abstract_(arm limited)

Inventor(s): Olof Henrik Uhrenholt of Lomma SE for arm limited, Jakob Axel Fries of Lund SE for arm limited

IPC Code(s): G06T15/00

CPC Code(s): G06T15/005

Abstract: a method of operating a graphics processor when performing a certain sequence of rendering jobs that produces a series of progressively lower resolution versions of the same render output comprising issuing rendering tasks for different rendering jobs concurrently and controlling processing for a later rendering job using a respective ‘task completion status’ data structure associated with the earlier rendering job on which it depends, wherein the looking up of respective entries in the ‘task completion status’ data structure takes into account the change in resolution between the first, earlier rendering job and the second, later rendering job.

20250111584. GRAPHICS TEXTURE MAPPING_simplified_abstract_(arm limited)

Inventor(s): Edvard Fielding of Trondheim NO for arm limited, Rodolfo Luis Jalabert Castellanos of Trondheim NO for arm limited

IPC Code(s): G06T15/04, G06T1/20

CPC Code(s): G06T15/04

Abstract: when performing a texture sampling operation that uses the results of plural texture filtering operations to provide an overall output sampled texture value in a graphics processing system, it is determined whether a texture filtering operation in the set of plural texture filtering operations that are to be performed to provide the overall output sampled texture value can be at least partially merged with another texture filtering operation in the set of texture filtering operations. if so a merged texture filtering operation is performed for the two texture filtering operations, with the result of the merged texture filtering operation being used when providing the overall output sampled texture value.

20250111602. SYSTEM, DEVICES AND/OR PROCESSES FOR IMAGE FRAME UPSCALING_simplified_abstract_(arm limited)

Inventor(s): Daren Croxford of Swaffham Prior GB for arm limited, Roberto Lopez Mendez of Cambridge GB for arm limited, Mina Ivanova Dimova of Great Shelford GB for arm limited, Maxim Novikov of Manchester GB for arm limited

IPC Code(s): G06T15/80, G06T3/40, G06T5/00, G06T7/20, G06T7/50

CPC Code(s): G06T15/80

Abstract: example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to enhance a rendered image. in an implementation, a process to enhance a portion of a rendered image may be affected based, at least in part, on a shading rate applied in rendering the portion of the rendered image.

20250112461. DYNAMIC SELECTION OF POWER ROUTES IN CIRCUITS_simplified_abstract_(arm limited)

Inventor(s): Alexander Klimov of Hadera IL for arm limited

IPC Code(s): H02J3/00, G06F21/72

CPC Code(s): H02J3/001

Abstract: an apparatus is provided for varying paths from power sources to components in order to inhibit side channel attacks. the power source provides power. the circuit component consumes the power to perform a function and a power grid provides a plurality of redundant paths by which the power can flow from between the circuit component and one of a power source and ground, to perform the function. the power grid is dynamically selects at least one active path of the redundant paths through which the power flows to perform the function.

Arm Limited patent applications on April 3rd, 2025