Applied materials, inc. (20240258164). METHODS OF FORMING INTERCONNECT STRUCTURES simplified abstract
Contents
METHODS OF FORMING INTERCONNECT STRUCTURES
Organization Name
Inventor(s)
Jiajie Cen of San Jose CA (US)
Carmen Leal Cervantes of Mountain View CA (US)
Yong Jin Kim of Albany CA (US)
Kevin Kashefi of San Ramon CA (US)
Xiaodong Wang of San Jose CA (US)
METHODS OF FORMING INTERCONNECT STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240258164 titled 'METHODS OF FORMING INTERCONNECT STRUCTURES
The patent application describes a method of forming devices by creating a dielectric layer on a substrate with at least one feature defining a gap with sidewalls and a bottom.
- A pre-clean process is conducted before a self-assembled monolayer (SAM) is formed on the bottom of the gap.
- A barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap.
- The SAM is removed after the barrier layer is selectively deposited on the sidewalls.
Potential Applications: - Semiconductor manufacturing - Microelectronics industry - Nanotechnology research
Problems Solved: - Improving device performance - Enhancing manufacturing processes - Increasing device reliability
Benefits: - Enhanced device functionality - Improved manufacturing efficiency - Greater control over device properties
Commercial Applications: Title: Advanced Dielectric Layer Formation Method for Semiconductor Devices This technology could revolutionize the semiconductor industry by offering a more precise and efficient method for forming dielectric layers in devices. This innovation has the potential to streamline manufacturing processes, improve device performance, and drive advancements in semiconductor technology.
Questions about the technology: 1. How does the selective deposition of the barrier layer on the sidewalls improve device performance? 2. What are the specific advantages of using a pre-clean process before forming the SAM layer?
Original Abstract Submitted
methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. a pre-clean process is performed before a self-assembled monolayer (sam) is formed on the bottom of the gap. a barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. the sam is removed after selectively depositing the barrier layer on the sidewalls.
