Applied Materials, Inc. patent applications published on December 14th, 2023

Patent applications for Applied Materials, Inc. on December 14th, 2023

MEMORY CELL SELECTOR FOR HIGH-VOLTAGE SET AND RESET OPERATIONS (17838718)

Main Inventor

Frank Tzen-Wen Guo

Brief explanation

The abstract of the patent application describes a selector for a memory cell in a memory array that uses different conductive paths to apply high and low voltages during set and reset operations. This allows for smaller transistors while still enabling high-voltage operations on resistive memory elements.

• The selector includes a first transistor that connects a high voltage to a terminal of the memory element during a reset operation.
• A second transistor connects a low voltage to the terminal of the memory element during a set operation.
• A third transistor is added in series with the first transistor, and a fourth transistor is added in series with the second transistor.
• The gates of the third and fourth transistors are biased at a voltage that is approximately halfway between the low and high voltages.

Potential applications of this technology:

• Memory arrays in electronic devices such as computers, smartphones, and IoT devices.
• Non-volatile memory systems that require high-voltage set and reset operations.

Problems solved by this technology:

• Enables high-voltage set and reset operations on resistive memory elements.
• Reduces the size of transistors used in the memory cell.

Benefits of this technology:

• Facilitates high-voltage operations on resistive memory elements while using smaller transistors.
• Allows for more compact memory arrays in electronic devices.
• Improves the efficiency and performance of non-volatile memory systems.

Abstract

A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a terminal of the memory element during a reset operation. Similarly, a second transistor may open a conductive path between a low voltage and the terminal of the memory element during a set operation. Some implementations may add a third transistor in series with the first transistor and a fourth transistor in series with the second transistor. The gates of the third and fourth transistors may be biased at a voltage that is about halfway between the low and high voltages. This selector may use smaller transistors while still facilitating high-voltage set and reset operations on resistive memory elements.

MOLTEN LIQUID TRANSPORT FOR TUNABLE VAPORIZATION IN ION SOURCES (17835107)

Main Inventor

Craig R. Chaney

Brief explanation

The abstract describes an ion source with a crucible that contains a solid dopant material. A porous wicking tip is placed in the crucible to control the flow rate of molten dopant material to the arc chamber. 

• The ion source includes a crucible with a solid dopant material.
• A porous wicking tip is inserted into the crucible.
• The wicking tip can be a tube with interior conduits, two concentric cylinders with rods in between, or one or more wound foil layers.
• The wicking tip controls the flow rate of molten dopant material to the arc chamber.

Potential Applications

• Ion implantation in semiconductor manufacturing.
• Ion beam analysis in materials science.
• Ion thrusters in spacecraft propulsion.

Problems Solved

• Controlling the flow rate of molten dopant material in an ion source.
• Ensuring consistent and precise delivery of dopant material to the arc chamber.

Benefits

• Improved control over the ion source operation.
• Enhanced precision and consistency in ion beam processes.
• Increased efficiency and reliability in various applications.

Abstract

An ion source with a crucible is disclosed. In some embodiments, the crucible contains a solid dopant material, such as a metal. A porous wicking tip is disposed in the crucible in contact with the solid dopant material. The porous wicking tip may be a tube with one or more interior conduits. Alternatively, the porous tip may be two concentric cylinders with a plurality of rods disposed in the annular ring between the two cylinders. Alternatively, the porous tip may be one or more foil layers wound together. In each of these embodiments, the wicking tip can be used to control the flow rate of molten dopant material to the arc chamber.

PULSED VOLTAGE SOURCE FOR PLASMA PROCESSING APPLICATIONS (17835864)

Main Inventor

A N M Wasekul AZAD

Brief explanation

The patent application describes a waveform generator used in plasma processing systems for the plasma processing of a substrate in a processing chamber.

• The waveform generator includes a first voltage stage with a voltage source, a switch, a ground reference, and a transformer with a primary winding and a secondary winding.
• The secondary winding is coupled to the ground reference and is connected to a load through a common node.
• A diode is also coupled in parallel with the primary winding of the transformer.
• The waveform generator also includes one or more additional voltage stages connected to the load through the common node.

Potential applications of this technology:

• Plasma processing systems used in semiconductor manufacturing.
• Plasma etching and deposition processes in the fabrication of integrated circuits.
• Plasma cleaning and surface treatment in various industries.

Problems solved by this technology:

• Provides a waveform generator for plasma processing systems that can generate the desired waveforms for efficient and effective plasma processing.
• Allows for precise control of the plasma processing parameters.
• Enables improved uniformity and repeatability of plasma processing results.

Benefits of this technology:

• Improved efficiency and effectiveness of plasma processing.
• Enhanced control over plasma processing parameters.
• Increased uniformity and repeatability of plasma processing results.
• Potential for cost savings and improved product quality in semiconductor manufacturing and other industries.

Abstract

Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; a ground reference; a transformer having a first transformer ratio, the first transformer comprising: a primary winding coupled to the first voltage source and the ground reference; and a secondary winding having a first end and a second end, wherein the first end is coupled to the ground reference, and the second end is configured to be coupled to a load through a common node; and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator generally also includes one or more additional voltage stages coupled to a load through the common node.

UNIFORM IN SITU CLEANING AND DEPOSITION (18457061)

Main Inventor

Saket Rathi

Brief explanation

The patent application describes a semiconductor processing system that includes an output manifold with a plasma outlet, a gasbox beneath the manifold, and a tapered inner wall in the gasbox that defines a central fluid lumen. There is also an annular spacer below the gasbox and a faceplate with apertures beneath the spacer.

• The system includes an output manifold with a plasma outlet.
• A gasbox is positioned beneath the output manifold.
• The gasbox has an inner wall that tapers outward from the inlet side to the outlet side.
• The gasbox also has a central fluid lumen defined by the inner wall.
• An annular spacer is placed below the gasbox.
• The inner diameter of the annular spacer is larger than the largest inner diameter of the central fluid lumen.
• A faceplate is positioned beneath the annular spacer.
• The faceplate has a plurality of apertures that extend through its thickness.

Potential applications of this technology:

• Semiconductor manufacturing processes
• Plasma etching and deposition processes

Problems solved by this technology:

• Efficient and controlled distribution of gases in a semiconductor processing system
• Improved plasma uniformity and process stability

Benefits of this technology:

• Enhanced performance and reliability of semiconductor devices
• Increased process efficiency and yield
• Reduced manufacturing costs

Abstract

Exemplary semiconductor processing systems may include an output manifold that defines at least one plasma outlet. The systems may include a gasbox disposed beneath the output manifold. The gasbox may include an inlet side facing the output manifold and an outlet side opposite the inlet side. The gasbox may include an inner wall that defines a central fluid lumen. The inner wall may taper outward from the inlet side to the outlet side. The systems may include an annular spacer disposed below the gasbox. An inner diameter of the annular spacer may be greater than a largest inner diameter of the central fluid lumen. The systems may include a faceplate disposed beneath the annular spacer. The faceplate may define a plurality of apertures extending through a thickness of the faceplate.

APPARATUS FOR GENERATING ETCHANTS FOR REMOTE PLASMA PROCESSES (17869987)

Main Inventor

Tae Seung CHO

Brief explanation

The abstract describes a remote plasma source (RPS) that uses symmetrical hollow cathode cavities to increase etchant rates. The RPS includes an upper electrode and a lower electrode, both with hollow cavities that induce a hollow cathode effect. The electrodes are separated by a gap, and an annular dielectric cover fills part of the gap, creating a second gap between the cover and the upper electrode.

• The RPS uses symmetrical hollow cathode cavities to generate etchants more efficiently.
• The upper and lower electrodes induce a hollow cathode effect within their respective hollow cavities.
• The annular dielectric cover fills part of the gap between the electrodes, creating a second gap.
• The annular dielectric cover fills approximately 50% to 95% of the height of the first gap.

Potential Applications

• Semiconductor manufacturing
• Thin film deposition
• Surface treatment processes

Problems Solved

• Low etchant rates
• Inefficient etching processes
• Uneven etching results

Benefits

• Increased etchant rates
• Improved etching efficiency
• More uniform and precise etching results

Abstract

A remote plasma source (RPS) for generating etchants leverages symmetrical hallow cathode cavities to increase etchant rates. The RPS includes an upper electrode with a first hollow cavity configured to induce a hollow cathode effect within the first hollow cavity, a lower electrode with a second hollow cavity configured to induce a hollow cathode effect within the second hollow cavity, wherein the first hollow cavity and the second hollow cavity are symmetrical, a first gap positioned between and electrically separating the upper electrode and the lower electrode, and an annular dielectric cover in direct contact with the lower electrode in the first gap and forms a second gap between an uppermost surface of the annular dielectric cover and a lowermost surface of the upper electrode. The annular dielectric cover fills approximately 50% to approximately 95% of a height of the first gap.

ELECTROSTATIC CHUCK ASSEMBLY FOR CRYOGENIC APPLICATIONS (18237673)

Main Inventor

Vijay D. PARKHE

Brief explanation

The abstract describes an electrostatic chuck assembly designed for use in cryogenic applications. The assembly includes an electrostatic chuck with a substrate supporting surface and a bottom surface, a cooling plate made of an aluminum alloy with a low coefficient of thermal expansion, and a bonding layer made of silicone material that secures the electrostatic chuck to the cooling plate.

• The electrostatic chuck assembly is suitable for use in cryogenic applications.
• The assembly includes an electrostatic chuck with a substrate supporting surface and a bottom surface.
• A cooling plate made of an aluminum alloy with a low coefficient of thermal expansion is included in the assembly.
• The bottom surface of the electrostatic chuck is secured to the top surface of the cooling plate using a bonding layer made of silicone material.

Potential applications of this technology:

• Semiconductor manufacturing: The electrostatic chuck assembly can be used in cryogenic environments during the manufacturing of semiconductors.
• Research and development: The assembly can be utilized in cryogenic research and development applications where precise temperature control is required.

Problems solved by this technology:

• Thermal expansion mismatch: The use of an aluminum alloy cooling plate with a low coefficient of thermal expansion helps to minimize thermal expansion mismatch between the electrostatic chuck and the cooling plate, reducing the risk of damage or failure.
• Temperature control: The electrostatic chuck assembly allows for precise temperature control in cryogenic applications, ensuring the stability and reliability of the process.

Benefits of this technology:

• Improved performance: The use of a cooling plate with a low coefficient of thermal expansion and a silicone bonding layer enhances the performance and reliability of the electrostatic chuck assembly in cryogenic environments.
• Cost-effective: The assembly provides a cost-effective solution for cryogenic applications, as it utilizes readily available materials and simple manufacturing processes.

Abstract

Embodiments of the present disclosure generally relate to an electrostatic chuck assembly suitable for use in cryogenic applications. In one or more embodiments, an electrostatic chuck assembly is provided and includes an electrostatic chuck having a substrate supporting surface opposite a bottom surface, a cooling plate having a top surface, where the cooling plate contains an aluminum alloy having a coefficient of thermal expansion (CTE) of less than 22 ppm/° C., and a bonding layer securing the bottom surface of the electrostatic chuck and the top surface of the cooling plate, where the bonding layer contains a silicone material.

PLASMA PRECLEAN SYSTEM FOR CLUSTER TOOL (17836657)

Main Inventor

Songjae LEE

Brief explanation

The abstract describes a plasma processing system used for cleaning a substrate. The system includes a process chamber with a substrate support and a vacuum pump. There are two exhaust lines connected between the process chamber and the vacuum pump, providing alternative paths for exhaust. The first exhaust line has a smaller internal diameter compared to the second exhaust line.

• The plasma processing system is designed for cleaning substrates.
• It includes a process chamber with a substrate support.
• The system utilizes a vacuum pump for exhaust.
• There are two exhaust lines connecting the process chamber and the vacuum pump.
• The first exhaust line has a smaller internal diameter than the second exhaust line.

Potential Applications

• Semiconductor manufacturing
• Thin film deposition
• Surface cleaning and etching processes

Problems Solved

• Efficient exhaust of gases and byproducts during plasma processing
• Controlling the flow and pressure within the process chamber

Benefits

• Improved cleaning and processing efficiency
• Enhanced control over exhaust flow and pressure
• Potential for higher quality and more precise plasma processing

Abstract

A plasma processing system for cleaning a substrate is provided. The plasma processing system includes a process chamber that includes: a chamber body enclosing an interior volume; and a substrate support disposed in the interior volume. The plasma processing system includes a vacuum pump; a first exhaust line fluidly coupled between the interior volume of the process chamber and the vacuum pump; and a second exhaust line fluidly coupled between the interior volume of the process chamber and the vacuum pump. The first exhaust line and the second exhaust line are arranged to provide alternative paths for the exhaust between the interior volume and the vacuum pump, and the first exhaust line has an internal diameter that is at least 50% smaller than the internal diameter of the second exhaust line.

METHODS AND APPARATUS FOR CONTROLLING ION FRACTION IN PHYSICAL VAPOR DEPOSITION PROCESSES (18237934)

Main Inventor

Xiaodong WANG

Brief explanation

The patent application describes methods and apparatus for processing substrates. It specifically focuses on a process chamber used for processing a substrate. The chamber includes various components such as a body, a target to be sputtered, a substrate support, a collimator, and three magnets. 

• The body of the chamber has an interior volume divided into a central portion and a peripheral portion.
• The substrate support is placed in the interior volume and has a surface that supports the substrate.
• The collimator is positioned between the target and the substrate support within the interior volume.
• The first magnet is located around the body near the collimator.
• The second magnet is positioned around the body above the support surface but below the collimator.
• The third magnet is placed around the body between the first and second magnets.
• The three magnets work together to generate magnetic fields that redistribute ions over the substrate.

Potential applications of this technology:

• Semiconductor manufacturing: This technology can be used in the production of semiconductor devices, where precise ion distribution is crucial for the performance of the devices.
• Thin film deposition: The technology can be applied in the deposition of thin films on substrates, ensuring uniformity and accuracy in the process.
• Solar cell production: Solar cells require precise ion distribution to optimize their efficiency, and this technology can help achieve that.

Problems solved by this technology:

• Uneven ion distribution: The technology addresses the issue of ions being distributed unevenly over the substrate during processing, which can lead to inconsistent results and reduced performance.
• Inefficient sputtering: By redistributing ions more effectively, the technology improves the efficiency of the sputtering process, reducing waste and improving overall productivity.

Benefits of this technology:

• Improved substrate processing: The technology ensures a more uniform distribution of ions over the substrate, resulting in improved processing and performance of the substrate.
• Increased efficiency: By optimizing ion distribution, the technology increases the efficiency of the sputtering process, reducing time and resources required for substrate processing.
• Enhanced product quality: The precise control of ion distribution provided by the technology leads to higher quality products with improved consistency and performance.

Abstract

Methods and apparatus for processing substrates are disclosed. In some embodiments, a process chamber for processing a substrate includes: a body having an interior volume and a target to be sputtered, the interior volume including a central portion and a peripheral portion; a substrate support disposed in the interior volume opposite the target and having a support surface configured to support the substrate; a collimator disposed in the interior volume between the target and the substrate support; a first magnet disposed about the body proximate the collimator; a second magnet disposed about the body above the support surface and entirely below the collimator and spaced vertically below the first magnet; and a third magnet disposed about the body and spaced vertically between the first magnet and the second magnet. The first, second, and third magnets are configured to generate respective magnetic fields to redistribute ions over the substrate.

PATTERNING LAYER MODIFICATION USING DIRECTIONAL RADICAL RIBBON BEAM (17837543)

Main Inventor

John Hautala

Brief explanation

The patent application describes methods for creating semiconductor patterning features. These features are formed by removing a portion of a resist layer or a carbon-based layer using a beam of neutral reactive radicals directed at a non-zero angle relative to the surface of the layer.

• The method involves providing a semiconductor device with a patterning layer that has multiple openings defined by its sidewalls.
• A beam of neutral reactive radicals is then directed into the sidewalls of the patterning layer.
• The beam is directed at a non-zero angle relative to the surface of the patterning layer.
• This beam of neutral reactive radicals removes a portion of the patterning layer, creating the desired semiconductor patterning features.

Potential Applications

• Semiconductor manufacturing
• Integrated circuit fabrication
• Nanotechnology research

Problems Solved

• Provides a method for creating semiconductor patterning features with high precision and accuracy.
• Allows for the formation of complex patterns and structures in semiconductor devices.
• Enables the fabrication of smaller and more efficient electronic components.

Benefits

• Improved control and accuracy in creating semiconductor patterning features.
• Enables the production of advanced semiconductor devices with higher performance.
• Reduces the size and complexity of electronic components, leading to smaller and more efficient devices.

Abstract

Disclosed are approaches for forming semiconductor patterning features. One method may include providing a plurality of openings through a patterning layer of a semiconductor device, wherein each opening of the plurality of openings is defined by a sidewall of the patterning layer, and wherein the patterning layer is a resist layer or a carbon-based layer. The method may further include removing a portion of the patterning layer by directing a beam of neutral reactive radicals into the sidewall, wherein the beam of neutral reactive radicals is directed at a non-zero angle relative to a perpendicular extending from an upper surface of the patterning layer.

METHOD OF FORMING CARBON-BASED SPACER FOR EUV PHOTORESIST PATTERNS (17839809)

Main Inventor

Xinke Wang

Brief explanation

The patent application describes methods for depositing a conformal carbon-containing spacer layer on a patterned surface and substrate. The carbon-containing film acts as a spacer to reduce the critical dimension (CD) and can also serve as an etch protection layer or an etch resistance layer for the sidewall of nanostructures. 

• Flow a first precursor over a patterned surface and substrate to form an initial carbon-containing film
• Remove the first precursor effluent from the substrate
• Flow a second precursor over the substrate to react with the initial carbon-containing film
• Remove the second precursor effluent from the substrate
• Etch the substrate to remove a portion of the carbon-containing film and expose the top surface of the patterned surface and substrate between the patterned surfaces
• The carbon-containing film can act as a liner material when no etch is performed

Potential applications of this technology:

• Semiconductor manufacturing
• Nanotechnology
• Microelectronics

Problems solved by this technology:

• Provides a method for depositing a conformal carbon-containing spacer layer on a patterned surface and substrate
• Reduces the critical dimension (CD) of nanostructures
• Acts as an etch protection layer or an etch resistance layer for the sidewall of nanostructures

Benefits of this technology:

• Enables precise control of critical dimensions in nanostructures
• Provides improved etch protection for sidewalls
• Enhances the performance and reliability of semiconductor devices

Abstract

Methods of depositing a conformal carbon-containing spacer layer are described. Exemplary processing methods may include flowing a first precursor over a patterned surface and a substrate to form a first portion of an initial carbon-containing film on the structure. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial carbon-containing film. The methods may include removing a second precursor effluent from the substrate. The methods may include etching the substrate to remove a portion of the carbon-containing film and expose a top surface of the patterned surface and expose the substrate between the patterned surfaces. The patterned surface may be an EUV photoresist pattern, and the carbon-containing film may be formed on the sidewall and act as a spacer to reduce the critical dimension (CD). The carbon-containing film may act as an etch protection layer or an etch resistance layer for the sidewall of the nanostructures. When no etch is performed, the carbon-containing film may act as a liner material.

METHOD AND APPARATUS FOR ETCHING A SEMICONDUCTOR SUBSTRATE IN A PLASMA ETCH CHAMBER (17837958)

Main Inventor

Daisuke SHIMIZU

Brief explanation

The patent application describes methods and apparatus for etching a substrate in a plasma etch chamber. It introduces a new technique involving the application of a voltage waveform to an electrode in the substrate support during plasma exposure. This technique is performed in a series of macro etch cycles, each consisting of a first macro etch period and a second macro etch period. The first macro etch period includes multiple micro etch cycles, each having a bias power on (BPON) period and a bias power off (BPOFF) period. Notably, the duration of the BPON period is shorter than the duration of the BPOFF period. During the second macro etch period, bias power is predominantly not applied to the electrode.

• The patent application introduces a novel method for etching a substrate in a plasma etch chamber.
• It involves applying a voltage waveform to an electrode in the substrate support during plasma exposure.
• The etching process is performed in a series of macro etch cycles, each consisting of a first macro etch period and a second macro etch period.
• The first macro etch period includes multiple micro etch cycles, each having a bias power on (BPON) period and a bias power off (BPOFF) period.
• The duration of the BPON period is shorter than the duration of the BPOFF period.
• During the second macro etch period, bias power is predominantly not applied to the electrode.

Potential Applications

• Semiconductor manufacturing
• Microelectronics fabrication
• Nanotechnology research

Problems Solved

• Provides an improved method for etching substrates in a plasma etch chamber
• Enhances the etching process by introducing a voltage waveform and specific timing parameters
• Improves the uniformity and precision of etching results

Benefits

• Increased efficiency and effectiveness of substrate etching
• Improved control over the etching process
• Enhanced uniformity and precision in etching results
• Potential for higher throughput in semiconductor manufacturing and microelectronics fabrication

Abstract

Methods and apparatus for etching a substrate in a plasma etch chamber are provided. In one example, the method includes exposing a substrate disposed on a substrate supporting surface of a substrate support to a plasma within a processing chamber, and applying a voltage waveform to an electrode disposed in the substrate support while the substrate is exposed to the plasma during a plurality of macro etch cycles. Each macro etch cycle includes a first macro etch period and a second macro etch period. The macro etch period includes a plurality of micro etch cycles. Each micro etch cycle has a bias power on (BPON) period and a bias power off (BPOFF) period, wherein a duration of the BPON period being less than a duration of the BPOFF period. Bias power is predominantly not applied to the electrode during the second macro etch period.

METHODS FOR PATTERNING SUBSTRATES TO ADJUST VOLTAGE PROPERTIES (18198064)

Main Inventor

Steven C. H. HUNG

Brief explanation

The abstract describes a method for adjusting the threshold voltage in a field-effect-transistor (FET) device. Here is a simplified explanation of the abstract:

• The method involves depositing a diffusion barrier layer over a gate dielectric layer in different regions of a semiconductor structure.
• A portion of the deposited diffusion layer is removed in one region, while a portion of the deposited diffusion barrier layer is partially removed in another region.
• A dipole layer is then deposited over the gate dielectric layer in one region and over the diffusion barrier layer in the other regions.
• An annealing process is performed to drive dipole dopants from the dipole layer into the gate dielectric layer.

Potential applications of this technology:

• This method can be used in the fabrication of field-effect-transistor (FET) devices.
• It can help in adjusting the threshold voltage of FET devices, which is important for their performance and functionality.

Problems solved by this technology:

• The method provides a way to adjust the threshold voltage in FET devices, which is crucial for controlling their operation.
• It allows for precise tuning of the threshold voltage without the need for complex fabrication processes.

Benefits of this technology:

• The method offers a simple and effective way to adjust the threshold voltage in FET devices.
• It provides flexibility in controlling the performance characteristics of FET devices.
• The process can be easily integrated into existing semiconductor fabrication processes.

Abstract

A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.

METHODS AND APPARATUS FOR PROCESSING A SUBSTRATE (17748270)

Main Inventor

Gaurav SHRIVASTAVA

Brief explanation

The patent application describes methods and apparatus for processing a substrate, such as a semiconductor wafer. It specifically focuses on a pressure system used in the processing volume to control the pressure.

• The pressure system includes a throttle valve assembly, which consists of a housing, a sensing device, and a fan.
• The sensing device is located inside the housing and is designed to detect temperature changes within the housing.
• When the pressure system is operating to control the pressure in the processing volume, the sensing device ensures that the fan remains off if the temperature inside the housing is below a certain predetermined temperature.
• However, when the temperature inside the housing reaches or exceeds the predetermined temperature, the sensing device automatically turns on the fan.

Potential applications of this technology:

• Semiconductor manufacturing: The processing of substrates, such as semiconductor wafers, often requires precise control of pressure. This technology can be used in semiconductor fabrication processes to maintain the desired pressure levels in the processing volume.
• Thin film deposition: Thin film deposition techniques, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), can benefit from accurate pressure control. The described pressure system can be utilized in these processes to ensure optimal conditions for thin film growth.

Problems solved by this technology:

• Maintaining pressure control: The pressure system described in the patent application helps to maintain the desired pressure levels in the processing volume by automatically adjusting the fan based on temperature changes.
• Preventing overheating: By turning on the fan when the temperature inside the housing reaches a certain threshold, the technology prevents overheating of the pressure system components, ensuring their longevity and reliability.

Benefits of this technology:

• Improved process control: The accurate control of pressure in the processing volume enhances the quality and consistency of the substrate processing, leading to improved overall process control.
• Extended equipment lifespan: By preventing overheating, the technology helps to prolong the lifespan of the pressure system components, reducing maintenance and replacement costs.
• Energy efficiency: The fan is only activated when necessary, based on temperature changes, resulting in energy savings during operation.

Abstract

Methods and apparatus for processing a substrate are provided herein. For example, a processing volume for processing a substrate and a pressure system in fluid communication with the processing volume and comprising a throttle valve assembly including a housing, a sensing device disposed in an interior of the housing, and a fan open to the interior of the housing, wherein, during operation of the pressure system to control a pressure within the processing volume, the sensing device is responsive to temperature changes in the interior of the housing such that the fan remains off when a temperature of the interior of the housing is less than a predetermined temperature and automatically turns on when the temperature within interior of the housing is equal to or greater than the predetermined temperature.

AUTO FINE-TUNER FOR DESIRED TEMPERATURE PROFILE (17835711)

Main Inventor

Yi Wang

Brief explanation

The patent application describes a method for setting a target profile by combining gain curves for temperature sensor offsets and zone multipliers into a thermal model. This model is then used to generate temperature sensor offsets and zone multipliers to apply to a reference data set in order to generate the target profile.

• The method involves obtaining gain curves for temperature sensor offsets and zone multipliers.
• These gain curves are combined into a thermal model.
• A reference data set is obtained.
• The thermal model is used to generate temperature sensor offsets and zone multipliers.
• These offsets and multipliers are applied to the reference data set to generate the target profile.

Potential Applications

• This technology can be applied in various industries where temperature control is crucial, such as HVAC systems, industrial processes, and electronic devices.
• It can be used to optimize temperature regulation and improve energy efficiency in buildings and manufacturing processes.

Problems Solved

• The method solves the problem of accurately setting a target profile by taking into account temperature sensor offsets and zone multipliers.
• It provides a more precise and reliable way to generate temperature profiles for different applications.

Benefits

• The method allows for better temperature control and regulation, leading to improved performance and energy efficiency.
• It provides a systematic approach to setting target profiles, reducing the need for manual adjustments and trial-and-error methods.
• The use of gain curves and a thermal model enhances accuracy and reliability in generating target profiles.

Abstract

Embodiments disclosed herein include a method of setting a target profile. In an embodiment, the method comprises obtaining a first gain curve for one or more temperature sensor offsets, and obtaining a second gain curve for one or more zone multipliers. In an embodiment, the method further comprises combining the first gain curve and the second gain curve into a thermal model. In an embodiment, the method further comprises obtaining a reference data set, and using the thermal model to generate temperature sensor offsets and/or zone multipliers to apply to the reference data set in order to generate the target profile.

TAB ARRANGEMENT FOR RETAINING SUPPORT ELEMENTS OF SUBSTRATE SUPPORT (17839235)

Main Inventor

Fred Eric RUHLAND

Brief explanation

The patent application describes substrate supports that are used in various applications. These supports have the following features:

• The substrate support consists of a first plate with multiple openings that extend from the top surface to the bottom surface of each opening.
• Each opening contains three or more tabs that extend towards the top surface of the first plate.
• The openings also contain support elements that are surrounded by the tabs, ensuring that the support elements are securely held in place.

Potential applications of this technology include:

• Semiconductor manufacturing: The substrate supports can be used to hold and position semiconductor wafers during various manufacturing processes.
• Printed circuit board assembly: The supports can be utilized to hold and align circuit boards during assembly and soldering processes.
• Optics manufacturing: The supports can be used to hold and position optical components during the manufacturing of lenses, mirrors, and other optical devices.

Problems solved by this technology include:

• Secure retention: The tabs surrounding the support elements ensure that they are held securely in place, preventing any movement or displacement during use.
• Simplified design: The use of tabs and support elements simplifies the design of the substrate support, making it easier to manufacture and assemble.
• Enhanced stability: The support elements, along with the tabs, provide increased stability to the substrate, reducing the risk of damage or misalignment.

Benefits of this technology include:

• Improved manufacturing efficiency: The substrate supports allow for faster and more accurate positioning of substrates, leading to increased productivity in manufacturing processes.
• Cost savings: The simplified design and ease of assembly result in cost savings during production.
• Enhanced product quality: The secure retention and stability provided by the supports contribute to improved product quality by reducing the risk of damage or misalignment.

Abstract

Embodiments of substrate supports are provided herein. In some embodiments, a substrate support includes: a first plate having a plurality of openings extending into the first plate from an upper surface of the first plate to a bottom surface of each respective opening of the plurality of openings; a plurality of tabs comprising three or more tabs disposed in each respective opening and extending towards the upper surface of the first plate; and a plurality of support elements disposed in each of the plurality of openings, wherein the plurality of tabs are disposed around each of the plurality of support elements and configured to retain the plurality of support elements in the plurality of openings.

SYSTEM FOR NON RADIAL TEMPERATURE CONTROL FOR ROTATING SUBSTRATES (18237669)

Main Inventor

Wolfgang R. ADERHOLD

Brief explanation

The present invention relates to an apparatus and method for reducing non-uniformity during thermal processing. The invention provides a chamber body with a processing volume, a substrate support that can rotate the substrate, a sensor assembly to measure temperature at multiple locations on the substrate, and pulse heating elements to provide pulsed energy to the processing volume.

• The invention aims to reduce non-uniformity during thermal processing.
• The apparatus includes a chamber body with a processing volume.
• A substrate support is provided within the processing volume, capable of rotating the substrate.
• A sensor assembly is included to measure the temperature of the substrate at various locations.
• One or more pulse heating elements are used to provide pulsed energy towards the processing volume.

Potential Applications

This technology can be applied in various industries and processes, including:

• Semiconductor manufacturing
• Thin film deposition
• Solar cell production
• LED fabrication
• Chemical vapor deposition

Problems Solved

The invention addresses the issue of non-uniformity during thermal processing, which can lead to inconsistent results and reduced product quality. By measuring the temperature at multiple locations on the substrate and providing pulsed energy, the invention helps to achieve more uniform heating and processing.

Benefits

The benefits of this technology include:

• Improved product quality and consistency
• Enhanced process control and efficiency
• Reduction in non-uniformity during thermal processing
• Increased yield and throughput
• Cost savings through improved energy utilization

Abstract

Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume.