Applied Materials, Inc. patent applications on July 25th, 2024

From WikiPatents
Jump to navigation Jump to search

Patent Applications by Applied Materials, Inc. on July 25th, 2024

Applied Materials, Inc.: 31 patent applications

Applied Materials, Inc. has applied for patents in the areas of C23C16/455 (6), H01J37/32 (6), H01L21/67 (4), C23C16/458 (3), C23C16/44 (3) G02B26/0816 (2), C08J3/21 (1), G05B23/024 (1), H01L21/6833 (1), H01L21/31122 (1)

With keywords such as: substrate, processing, layer, chamber, surface, process, embodiments, include, region, and methods in patent application abstracts.



Patent Applications by Applied Materials, Inc.

20240247113. METHOD OF FORMING AN AQUEOUS POLYMER COMPOSITION_simplified_abstract_(applied materials, inc.)

Inventor(s): Joseph Cameron BYERS of Kalispell MT (US) for applied materials, inc.

IPC Code(s): C08J3/21

CPC Code(s): C08J3/21



Abstract: embodiments of the disclosure relate to a substrate etching system and process. a method may include generating a first solution comprising a first polymer resin and a second polymer resin, receiving a second solution comprising the first polymer resin and a third solution comprising the second polymer resin, assessing a viscosity of the first solution, and adjusting the viscosity using the second solution and the third solution according to a downstream viscosity range.


20240247362. NOZZLE FOR A DISTRIBUTOR OF A MATERIAL DEPOSITION SOURCE, MATERIAL DEPOSITION SOURCE, VACUUM DEPOSITION SYSTEM AND METHOD FOR DEPOSITING MATERIAL_simplified_abstract_(applied materials, inc.)

Inventor(s): Julian AULBACH of Alzenau (DE) for applied materials, inc., Andreas MÜLLER of Karlstein (DE) for applied materials, inc., Harald WURSTER of Mömbris (DE) for applied materials, inc., Andreas LOPP of Freigericht (DE) for applied materials, inc., David Friedrich FREIHERR VON LINDENFELS of Obertshausen (DE) for applied materials, inc., Takashi ANJIKI of Aschaffenburg (JP) for applied materials, inc.

IPC Code(s): C23C14/24, C23C14/12

CPC Code(s): C23C14/243



Abstract: a nozzle for an evaporated material distributor is described. the nozzle includes a nozzle inlet for receiving evaporated material; a nozzle outlet; and a nozzle passage extending between the nozzle inlet and the nozzle outlet having a first passage portion, a second passage portion and a third passage portion, the second passage portion having an aperture angle which continuously increases in a direction from the nozzle inlet to the nozzle outlet and the third passage portion having an essentially constant aperture angle.


20240247365. MULTICATHODE PVD SYSTEM FOR HIGH ASPECT RATIO BARRIER SEED DEPOSITION_simplified_abstract_(applied materials, inc.)

Inventor(s): Harish V. PENMETHSA of Dublin CA (US) for applied materials, inc., Ming-Jui LI of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): C23C14/50, C23C14/04, C23C14/14, C23C14/35

CPC Code(s): C23C14/505



Abstract: apparatus and methods for multi-cathode barrier seed deposition for high aspect ratio features in a physical vapor deposition (pvd) process are provided herein. in some embodiments, a pvd chamber includes a pedestal disposed within a processing region of the pvd chamber. the pedestal rotates with a workpiece on it. the pvd chamber includes a lid assembly includes a first target and a second target of a same target material, where a first surface of the first target defines a first zone of the processing region a first distance from the upper surface of the pedestal, and a second surface of the second target defines a second zone of the processing region a second distance from the plane of the upper surface of the pedestal. a system controller is configured to simultaneously control a first voltage bias for the first target and a second voltage bias for the second target.


20240247370. ATOMIC LAYER DEPOSITION OF RUTHENIUM OXIDE COATINGS_simplified_abstract_(applied materials, inc.)

Inventor(s): Jeffrey W. Anthis of Redwood City CA (US) for applied materials, inc., Nasrin Kazem of Santa Clara CA (US) for applied materials, inc., Lakmal Charidu Kalutarage of San Jose CA (US) for applied materials, inc., Jayden Stephen John Shackerley Potter of Menlo Park CA (US) for applied materials, inc., Thomas Joseph Knisley of Livonia MI (US) for applied materials, inc., Lisa Enman of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): C23C16/40, C23C16/455, H01B1/08, H01L21/285, H01L33/42

CPC Code(s): C23C16/40



Abstract: a method includes depositing a coating including stoichiometric one-to-one ruthenium oxide (ruo) onto a surface of a substrate. the coating is deposited by performing an atomic layer deposition (ald) process using at least one precursor.


20240247371. SEMICONDUCTOR PROCESSING CHAMBERS AND METHODS FOR CLEANING THE SAME_simplified_abstract_(applied materials, inc.)

Inventor(s): Nitin Pathak of Mumbai (IN) for applied materials, inc., Yuxing Zhang of San Jose CA (US) for applied materials, inc., Tuan A. Nguyen of San Jose CA (US) for applied materials, inc., Kalyanjit Ghosh of Pleasanton CA (US) for applied materials, inc., Amit Bansal of Milpitas CA (US) for applied materials, inc., Juan Carlos Rocha-Alvarez of San Carlos CA (US) for applied materials, inc.

IPC Code(s): C23C16/44, C23C16/458, C23C16/52, H01J37/32

CPC Code(s): C23C16/4405



Abstract: a processing chamber may include a gas distribution member, a substrate support, and a pumping liner. the gas distribution member and the substrate support may at least in part define a processing volume. the pumping liner may define an internal volume in fluid communication with the processing volume via a plurality of apertures of the pumping liner circumferentially disposed about the processing volume. the processing chamber may further include a flow control mechanism operable to direct fluid flow from the internal volume of the pumping liner into the processing volume via a subset of the plurality of apertures of the pumping liner during fluid distribution into the processing volume from the gas distribution member.


20240247373. ADJUSTABLE CROSS-FLOW PROCESS CHAMBER LID_simplified_abstract_(applied materials, inc.)

Inventor(s): Muhannad Mustafa of Milpitas CA (US) for applied materials, inc., Sanjeev Baluja of Campbell CA (US) for applied materials, inc.

IPC Code(s): C23C16/455, C23C16/44, C23C16/458

CPC Code(s): C23C16/45517



Abstract: apparatus and methods for improving deposition uniformity in a cross-flow processing chamber are described. a precursor inlet is configured to allow a cross-flow of precursor from the precursor inlet side of the lid to an exhaust side of the lid opposite a center of the lid from the precursor inlet side. at least one purge gas inlet is in fluid communication with a purge gas channel, the purge gas channel having at least one opening aligned to provide a flow of gas to a center of a substrate in the cross-flow process chamber.


20240247374. PRECURSOR DELIVERY SYSTEM FOR SEMICONDUCTOR DEVICE FORMATION_simplified_abstract_(applied materials, inc.)

Inventor(s): Shashidhara Patel H B of Bangalore (IN) for applied materials, inc., Nagaraj Naik of Bangalore (IN) for applied materials, inc., Muhannad Mustafa of Milpitas CA (US) for applied materials, inc.

IPC Code(s): C23C16/455, C23C16/44

CPC Code(s): C23C16/45561



Abstract: embodiments of precursor delivery systems are described herein. the precursor delivery systems include a reservoir having a cylindrical body, a conical shaped inlet on a first end of the cylindrical body, and a conical shaped outlet on a second end of the cylindrical body. each of the conical shaped inlet and the conical shaped outlet independently have an angle in a range of from 5 degrees to 45 degrees. the amount of time to purge the reservoir described herein is reduced by at least 50% compared to reservoirs not having a conical shaped inlet and/or a conical shaped outlet. additional embodiments relate to methods for removing particles from the reservoir. an increased number of particles are removed from the reservoir described herein compared to reservoirs not having a conical shaped inlet and/or a conical shaped outlet.


20240247376. Fluorinated Aluminum Coated Component for a Substrate Processing Apparatus and Method of Producing_simplified_abstract_(applied materials, inc.)

Inventor(s): Douglas LONG of Sunnyvale CA (US) for applied materials, inc., Jallepally RAVI of San Ramon CA (US) for applied materials, inc., Dien-yeh WU of San Jose CA (US) for applied materials, inc.

IPC Code(s): C23C16/455, C23C4/08, C23C4/134, C23C16/42, C23C16/50, C23C18/16, C23C18/31, C25D3/44, C25D5/48, H01L21/285, H01L21/687

CPC Code(s): C23C16/45565



Abstract: a component of an apparatus for processing a substrate having a coating comprising fluorinated aluminum disposed on at least a portion of a surface of the component. a method of coating the component, a method of repairing a coating on a component, and a method of processing a substrate are also disclosed.


20240247379. FORMATION OF METALLIC FILMS ON ELECTROLESS METAL PLATING OF SURFACES_simplified_abstract_(applied materials, inc.)

Inventor(s): Chao Liu of San Jose CA (US) for applied materials, inc., David John Jorgensen of Mountain View CA (US) for applied materials, inc., Marc Shull of Los Gatos CA (US) for applied materials, inc., Christopher Laurent Beaudry of San Jose CA (US) for applied materials, inc., Joseph Frederick Behnke of San Jose CA (US) for applied materials, inc.

IPC Code(s): C23C28/00

CPC Code(s): C23C28/323



Abstract: embodiments of the disclosure relate to articles, coated chamber components, and techniques of coating chamber components and systems. in particular, disclosed is a chamber component and methods of forming the chamber component that includes a substrate and a first layer disposed on the substrate, the first layer including a metal with a first atomic concentration. the chamber component further includes a second layer disposed on the first layer, the second layer including the metal with a second atomic concentration that is at least 5 percent higher than the first atomic concentration.


20240247404. PRE-HEAT RINGS AND PROCESSING CHAMBERS INCLUDING BLACK QUARTZ, AND RELATED METHODS_simplified_abstract_(applied materials, inc.)

Inventor(s): Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Zhepeng CONG of San Jose CA (US) for applied materials, inc., Ashur J. ATANOS of San Jose CA (US) for applied materials, inc.

IPC Code(s): C30B25/10, C30B25/08, C30B25/14, C30B25/16

CPC Code(s): C30B25/10



Abstract: embodiments of the present disclosure generally relate to a pre-heat ring for use in a substrate processing chamber, and related methods. a pre-heat ring including black quartz (such as formed of black quartz) facilitates material properties that can facilitate heating benefits. in one or more embodiments, a pre-heat ring applicable for use in a semiconductor processing chamber includes one or more ring segments. the one or more ring segments include an inner edge defining an inner dimension, an outer edge defining an outer dimension, a first side surface between the inner edge and the outer edge, and a second side surface between the inner edge and the outer edge. the second side surface is opposing the first side surface. the one or more ring segments include black quartz. the black quartz includes silicon dioxide (sio) impregnated with undoped silicon (si).


20240247405. METHOD FOR CONTROLLING LAYER-TO-LAYER THICKNESS IN MULTI-TIER EPITAXIAL PROCESS_simplified_abstract_(applied materials, inc.)

Inventor(s): Alexandros ANASTASOPOULOS of San Francisco CA (US) for applied materials, inc., Zuoming ZHU of Sunnyvale CA (US) for applied materials, inc., Maribel MALDONADO-GARCIA of Valle de Santiago (MX) for applied materials, inc., Thomas KIRSCHENHEITER of Tempe AZ (US) for applied materials, inc., Flora Fong-Song CHANG of Saratoga CA (US) for applied materials, inc.

IPC Code(s): C30B25/22, C30B15/14, C30B25/12, C30B25/16, C30B29/06, C30B29/08

CPC Code(s): C30B25/22



Abstract: a method for substrate processing includes flowing one or more process reactive gases into an upper volume of a processing chamber, flowing cleaning gas into a lower volume of the processing chamber, measuring temperature of an inner surface of the lower volume of the processing chamber, and adjusting temperature of the inner surface of the lower volume of the processing chamber, based on the measured temperature.


20240247407. INDIUM-GALLIUM-NITRIDE LIGHT EMITTING DIODES WITH INCREASED QUANTUM EFFICIENCY_simplified_abstract_(applied materials, inc.)

Inventor(s): Michael Chudzik of Mountain View CA (US) for applied materials, inc., Max Batres of Redwood City CA (US) for applied materials, inc., Michel Khoury of Santa Barbara CA (US) for applied materials, inc.

IPC Code(s): C30B29/40, C30B25/02, C30B33/08, H01L21/02, H01L33/00

CPC Code(s): C30B29/406



Abstract: exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. the exemplary methods may further include forming at least one gallium nitride (gan)-containing region on the nucleation layer, and forming an indium-gallium-nitride (ingan)-containing layer on the gan-containing region. a porosified region may be formed on a portion of at least one of the gan-containing region and the ingan-containing layer, and an active region may be formed on the porosified region. in embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. in further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the gan-containing region. in still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.


20240248046. MULTI-HEAD OPTICAL INSPECTION SYSTEMS AND TECHNIQUES FOR SEMICONDUCTOR MANUFACTURING_simplified_abstract_(applied materials, inc.)

Inventor(s): Keith Wells of Santa Clara CA (US) for applied materials, inc., Ron Naftali of Shoham (IL) for applied materials, inc., Elad Eizner of Rehovot (IL) for applied materials, inc., Tal Kuzniz of Rehovot (IL) for applied materials, inc., Chi-Ming Tsai of Santa Clara CA (US) for applied materials, inc.

IPC Code(s): G01N21/95, G01N21/88

CPC Code(s): G01N21/9501



Abstract: implementations disclosed describe, among other things, a system and a method of using a wafer inspection system that includes a plurality of inspection heads configured to concurrently inspect a separate region of a plurality of regions of a wafer. each inspection head includes an illumination subsystem to illuminate a corresponding region of the wafer, a collection subsystem to collect a portion of light reflected/scattered from the corresponding region of the wafer. each inspection head further includes a light detection subsystem to detect the collected light and generate one or more signals representative of a state of the corresponding region of the wafer. the wafer inspection system further includes a processing device configured to determine, using the one or more signals received from each of the inspection heads, the quality of the wafer.


20240248282. APPARATUS AND METHODS FOR HEATING TUNABILITY IN PROCESSING CHAMBERS_simplified_abstract_(applied materials, inc.)

Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Saurabh CHOPRA of Santa Clara CA (US) for applied materials, inc., Lori D. WASHINGTON of San Jose CA (US) for applied materials, inc.

IPC Code(s): G02B7/28, G01J5/10, G02B26/02, H01L21/67

CPC Code(s): G02B7/28



Abstract: embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. in one embodiment, a substrate processing chamber includes a lid, a floor, and a processing volume between the lid and the floor. an upper window is disposed between the lid and the processing volume, a lower window is disposed between the floor and the processing volume. a lamp head is disposed between the lower window and the floor or between the upper window and the lid. at least one lamp is disposed within the lamp head, and a lens is disposed between the lamp head and the processing volume. in another embodiment, a plurality of lamps is disposed within the lamp head including at least one first lamp operating at a first wavelength and at least one second lamp operating at a second wavelength.


20240248297. APPARATUS AND METHODS FOR HEATING TUNABILITY IN PROCESSING CHAMBERS_simplified_abstract_(applied materials, inc.)

Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Saurabh CHOPRA of Santa Clara CA (US) for applied materials, inc., Lori D. WASHINGTON of San Jose CA (US) for applied materials, inc.

IPC Code(s): G02B26/08, G02B17/00, H01L21/67, H05B3/00

CPC Code(s): G02B26/0816



Abstract: embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. in an embodiment, an adjustable reflector includes a plurality of reflector elements. each of the plurality of elements as a first surface, a second surface, and a plurality of sidewalls. the first surface is a reflective surface and is configured to face a lamp. the adjustable reflector includes one or more actuation mechanisms coupled to the plurality of elements. a method of thermally processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under or over a lamp and the adjustable reflector, and in response to the thermal intensity being outside of desired parameters, adjusting the reflector profile of the reflector assembly along a centerline path.


20240248298. APPARATUS AND METHODS FOR HEATING TUNABILITY IN PROCESSING CHAMBERS_simplified_abstract_(applied materials, inc.)

Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Saurabh CHOPRA of Santa Clara CA (US) for applied materials, inc., Lori D. WASHINGTON of San Jose CA (US) for applied materials, inc.

IPC Code(s): G02B26/08, G02B17/00, H01L21/67, H05B3/00

CPC Code(s): G02B26/0816



Abstract: embodiments herein are generally directed to electronic device manufacturing and, more particularly, to systems and methods for lamp heating in thermal processing chambers. in an embodiment, an adjustable reflector assembly includes a plurality of elements including at least one stationary element and at least one rotating element, wherein a first surface of each of the plurality of elements is a reflective surface, and at least one actuation mechanism configured to actuate the at least one rotating element relative to the stationary element. a method of processing a substrate includes measuring a thermal intensity of a thermal profile of an area of a substrate under a lamp and the reflector assembly, determining if the thermal intensity is outside of desired parameters, and in response to the thermal intensity being outside of desired parameters, and adjusting a reflector profile of the reflector assembly.


20240248339. FLEXIBLE MULTI-LAYERED COVER LENS STACKS FOR FOLDABLE DISPLAYS_simplified_abstract_(applied materials, inc.)

Inventor(s): Manivannan THOTHADRI of Mountain View CA (US) for applied materials, inc., Harvey YOU of Mountain View CA (US) for applied materials, inc., Helinda NOMINANDA of San Jose CA (US) for applied materials, inc., Neil MORRISON of Seeheim-Jugenheim (DE) for applied materials, inc., Daniel Paul FORSTER of San Jose CA (US) for applied materials, inc., Arvinder CHADHA of San Jose CA (US) for applied materials, inc.

IPC Code(s): G02F1/1333, G02B1/11, G02B1/14

CPC Code(s): G02F1/133331



Abstract: embodiments described and discussed herein generally relate to flexible or foldable display devices, and more specifically to flexible cover lens assemblies. in one or more embodiments, a flexible cover lens assembly contains a glass layer, an adhesion promotion layer on the glass layer, an anti-reflectance layer disposed on the adhesion promotion layer, a dry hardcoat layer having a nano-indentation hardness in a range from about 1 gpa to about 5 gpa and disposed on the anti-reflectance layer, and an anti-fingerprint coating layer disposed on the dry hardcoat layer.


20240248466. PROCESS CHAMBER QUALIFICATION FOR MAINTENANCE PROCESS ENDPOINT DETECTION_simplified_abstract_(applied materials, inc.)

Inventor(s): Arvind Shankar Raman of Austin TX (US) for applied materials, inc., Harikrishnan Rajagopal of Santa Clara CA (US) for applied materials, inc., Minal Balkrishna Shettigar of San Jose CA (US) for applied materials, inc., Vishwath Ram Amarnath of Chenna (IN) for applied materials, inc., Yi Qi of Niskayuna NY (US) for applied materials, inc.

IPC Code(s): G05B23/02

CPC Code(s): G05B23/024



Abstract: methods and systems for process chamber qualification for maintenance process endpoint detection are provided. data collected by one or more sensors of a process chamber of a manufacturing system is identified. the identified data is collected during performance of initial maintenance operation(s) of a maintenance process. a current state of the process chamber is determined, based on the identified data, after the performance of the initial maintenance operation(s) based on the identified data. in response to a determination that the current state does not satisfy one or more chamber maintenance criteria, a set of subsequent maintenance operations to be performed to cause the current state of the process chamber to satisfy the criteria is identified. performance of the set of subsequent maintenance operations is initiated at the process chamber.


20240249052. SYSTEMS AND METHODS FOR PREDICTING FILM THICKNESS USING VIRTUAL METROLOGY_simplified_abstract_(applied materials, inc.)

Inventor(s): Debkalpo Das of Chennai (IN) for applied materials, inc., Raman K. Nurani of Chennai (IN) for applied materials, inc., Ramachandran Subramanian of Chennai (IN) for applied materials, inc., Bibhavendra Singh of Lucknow (IN) for applied materials, inc., Bharath Sundar of Chennai (IN) for applied materials, inc.

IPC Code(s): G06F30/33, G06F18/213, G06F18/214, H01L21/70

CPC Code(s): G06F30/33



Abstract: a method includes obtaining sensor data associated with a deposition process performed in a process chamber to deposit film on a surface of a substrate. a plurality of physics-based outputs are generated using a transformation function and the sensor data. the transformation function is used to at least one of estimate site availability for growth at an equilibrium condition for the process chamber or estimate boundary layer thickness in an equilibrium condition for the process chamber. the physics-based outputs are mapped to a training set and a virtual model is trained based on the training set and the sensor data. the virtual model is trained to generate predictive metrology data associated with the film.


20240249062. OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC)_simplified_abstract_(applied materials, inc.)

Inventor(s): Tamer COSKUN of San Jose CA (US) for applied materials, inc., Aidyn KEMELDINOV of Santa Clara CA (US) for applied materials, inc., Chung-Shin KANG of San Jose CA (US) for applied materials, inc., Uwe HOLLERBACH of Fremont CA (US) for applied materials, inc., Thomas L. LAIDIG of Richmond CA (US) for applied materials, inc.

IPC Code(s): G06F30/392, G06N20/00, H01L21/68

CPC Code(s): G06F30/392



Abstract: systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. in placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. according to certain embodiments, a machine learning (ml) model is trained on historical and simulated pixel models of chip-group connections and design connection points. upon determining the chip-group misalignment by a metrology measurement, the trained ml model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.


20240249904. Ion Source For Controlling Decomposition Buildup Using Chlorine Co-Gas_simplified_abstract_(applied materials, inc.)

Inventor(s): Mateo Navarro Goldaraz of Cambridge MA (US) for applied materials, inc., Graham Wright of Newburyport MA (US) for applied materials, inc., Ori Noked of Brookline MA (US) for applied materials, inc.

IPC Code(s): H01J27/02, H01J27/26

CPC Code(s): H01J27/022



Abstract: an ion source for generating an ion beam containing aluminum ions is disclosed. the ion source includes a first gas source to introduce an organoaluminium compound into the arc chamber of the ion source. a second gas, different from the first gas, which is a chlorine-containing gas is also introduced to the arc chamber. the chloride co-flow reduces the buildup of decomposition material that occurs within the arc chamber. this buildup may occur at the gas bushing, the extraction aperture or near the repeller. in some embodiments, the second gas is introduced continuously. in other embodiments, the second gas is periodically introduced, based on hours of operation or the measured uniformity of the extracted ion beam. the second gas may be introduced from second gas source or from a vaporizer.


20240249908. Dose Cup Assembly for an Ion Implanter_simplified_abstract_(applied materials, inc.)

Inventor(s): Frank Sinclair of Hartland ME (US) for applied materials, inc., Paul Joseph Murphy of Reading MA (US) for applied materials, inc., Bon-Woong Koo of Andover MA (US) for applied materials, inc., Gregory Edward Stratoti of Sandown NH (US) for applied materials, inc., Tseh-Jen Hsieh of Rowley MA (US) for applied materials, inc., Glenn Green of Woburn MA (US) for applied materials, inc.

IPC Code(s): H01J37/244, C23C14/48, H01J37/09, H01J37/317

CPC Code(s): H01J37/244



Abstract: a dose cup assembly that results in less particles in a process chamber is disclosed. the dose cup assembly includes a faceplate attached to a back wall of the process chamber, and having an opening; an aperture plate defining a plurality of slots; and a tunnel having walls and sidewalls and having a proximal end and a distal end, located between the faceplate and the aperture plate, such that the proximal end is nearer to the faceplate and the distal end is nearer to the aperture plate; wherein at least one of the faceplate, the walls, the sidewalls or the aperture plate has one or more exposed outer surfaces that comprise silicon. the exposed outer surfaces may be silicon. in some embodiments, the faceplate, the walls, the sidewalls or the aperture plate may be graphite, aluminum, or stainless steel which is coated with silicon or silicon carbide.


20240249915. PLASMA EXCITATION WITH ION ENERGY CONTROL_simplified_abstract_(applied materials, inc.)

Inventor(s): Yang YANG of San Diego CA (US) for applied materials, inc., Yue GUO of Redwood City CA (US) for applied materials, inc., Kartik RAMASWAMY of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01J37/32, H03H7/01

CPC Code(s): H01J37/32146



Abstract: embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. one embodiment includes a waveform generator having a voltage source selectively coupled to an output node, where the output node is configured to be coupled to an electrode disposed within a processing chamber, and where the output node is selectively coupled to a ground node. the waveform generator may also include a radio frequency (rf) signal generator, and a first filter coupled between the rf signal generator and the output node.


20240249918. Processing Chamber With Multiple Plasma Units_simplified_abstract_(applied materials, inc.)

Inventor(s): Kazuya Daito of Milipitas CA (US) for applied materials, inc., Yi Xu of San Jose CA (US) for applied materials, inc., Yu Lei of Belmont CA (US) for applied materials, inc., Takashi Kuratomi of San Jose CA (US) for applied materials, inc., Jallepally Ravi of San Ramon CA (US) for applied materials, inc., Pingyan Lei of San Jose CA (US) for applied materials, inc., Dien-Yeh Wu of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01J37/32, C23C16/455, C23C16/50, H01L21/67, H05H1/46

CPC Code(s): H01J37/32357



Abstract: provided is a processing chamber configured to contain a semiconductor substrate in a processing region of the chamber. the processing chamber includes a remote plasma unit and a direct plasma unit, wherein one of the remote plasma unit or the direct plasma unit generates a remote plasma and the other of the remote plasma unit or the direct plasma unit generates a direct plasma. the combination of a remote plasma unit and a direct plasma unit is used to remove, etch, clean, or treat residue on a substrate from previous processing and/or from native oxide formation. the combination of a remote plasma unit and direct plasma unit is used to deposit thin films on a substrate.


20240249920. REMOVABLE MASK LAYER TO REDUCE OVERHANG DURING RE-SPUTTER PROCESS IN PVD CHAMBERS_simplified_abstract_(applied materials, inc.)

Inventor(s): Wenting HOU of Sunnyvale CA (US) for applied materials, inc., Jianxin LEI of Fremont CA (US) for applied materials, inc.

IPC Code(s): H01J37/32

CPC Code(s): H01J37/32366



Abstract: apparatus and methods for processes of depositing a film on a substrate in an electronic device fabrication process are provided herein, and more particularly, apparatus and methods for improving deposited film uniformity within high aspect ratio features. in some embodiments, a metal layer deposition process is performed to deposit a metal layer in a feature definition formed in a substrate. a mask layer deposition process is performed to deposit a carbon layer on the metal layer. following the mask layer deposition process, a resputtering process is performed by applying a radio frequency (rf) signal to the substrate in a presence of an inert gas. following performing the resputtering process, an etching process is performed to remove the carbon.


20240249924. BIPOLAR ELECTROSTATIC CHUCK ELECTRODE DESIGNS_simplified_abstract_(applied materials, inc.)

Inventor(s): Jian Li of Fremont CA (US) for applied materials, inc., Kallol Bera of Fremont CA (US) for applied materials, inc., Edward P. Hammond of Hillsborough CA (US) for applied materials, inc., Dmitry A. Dzilno of Sunnyvale CA (US) for applied materials, inc., Juan Carlos Rocha-Alvarez of San Carlos CA (US) for applied materials, inc., Xiaopu Li of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01J37/32, C23C16/458, H01L21/683

CPC Code(s): H01J37/32724



Abstract: exemplary substrate support assemblies may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. the assemblies may include a support stem coupled with the electrostatic chuck body. the assemblies may include a first bipolar electrode embedded within the electrostatic chuck body. the assemblies may include a second bipolar electrode embedded within the electrostatic chuck body. an entirety of the second bipolar electrode may be radially inward of at least a portion of the first bipolar electrode. the first bipolar electrode and the second bipolar electrode may be coaxial with one another. each of the first bipolar electrode and the second bipolar electrode may be coupled with at least one rf power supply. each of the first bipolar electrode and the second bipolar electrode may be coupled with at least one dc power supply.


20240249934. INTEGRATED METHOD AND TOOL FOR HIGH QUALITY SELECTIVE SILICON NITRIDE DEPOSITION_simplified_abstract_(applied materials, inc.)

Inventor(s): Naomi Yoshida of Sunnyvale CA (US) for applied materials, inc., Bhaskar Jyoti Bhuyan of San Jose CA (US) for applied materials, inc., Hsueh Chung Chen of Cohoes NY (US) for applied materials, inc., Scott A. DeVries of Albany NY (US) for applied materials, inc., Raghuveer Satya Makala of Campbell CA (US) for applied materials, inc.

IPC Code(s): H01L21/02, C23C16/455, H01L21/768

CPC Code(s): H01L21/0217



Abstract: methods of manufacturing electronic devices, e.g., logic devices or memory devices, are provided. the method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; pre-treating the top surface of the film stack to form a treated surface; exposing the treated surface to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. the processing method is performed in a processing tool without breaking vacuum.


20240249936. METHODS FOR REDUCING MICRO AND MACRO SCALLOPING ON SEMICONDUCTOR DEVICES_simplified_abstract_(applied materials, inc.)

Inventor(s): Mang-Mang LING of San Jose CA (US) for applied materials, inc., Jong Mun KIM of San Jose CA (US) for applied materials, inc., Srinivas D. NEMANI of Sunnyvale CA (US) for applied materials, inc., Ellie Y. YIEH of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01L21/02, H01L21/033, H01L21/3213, H01L21/768

CPC Code(s): H01L21/02244



Abstract: embodiments of the present disclosure relate to methods for patterning a material layer on a substrate. the method includes forming a hard mask layer on a material layer disposed on a substrate. the material layer includes a plurality of first layers and a plurality of second layers alternately formed over the substrate. the method further includes performing a first etch process to form features in the material layer through the hard mask layer by supplying a first etching gas; performing an oxidation process to oxidize a sidewall of the features by supplying an oxidation gas; and performing a second etch process to etch the sidewall of the features formed in the material layer by suppling a second etching gas.


20240249953. DRY ETCH OF BORON-CONTAINING MATERIAL_simplified_abstract_(applied materials, inc.)

Inventor(s): Yeonju Kwak of Sunnyvale CA (US) for applied materials, inc., Jeong Hwan Kim of San Jose CA (US) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc., Siyu Zhu of San Jose CA (US) for applied materials, inc., Hang Yu of San Jose CA (US) for applied materials, inc., Srinivas Guggilla of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01L21/311, H01J37/32

CPC Code(s): H01L21/31122



Abstract: exemplary methods of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. the substrate may include a boron-containing material overlying a carbon-containing material. the methods may include generating plasma effluents of the fluorine-containing precursor. the methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor. the methods may include removing the boron-containing material from the substrate.


20240249965. SUBSTRATE SUPPORT CARRIER HAVING MULTIPLE CERAMIC DISCS_simplified_abstract_(applied materials, inc.)

Inventor(s): Arvinder Manmohan Singh CHADHA of San Jose CA (US) for applied materials, inc., Jonathan SIMMONS of San Jose CA (US) for applied materials, inc., Stephen Donald PROUTY of San Jose CA (US) for applied materials, inc., Christopher BEAUDRY of Santa Clara CA (US) for applied materials, inc., Glen T. MORI of Gilroy CA (US) for applied materials, inc., Anand DURAIRAJAN of San Jacinto CA (US) for applied materials, inc.

IPC Code(s): H01L21/683, H01L21/687

CPC Code(s): H01L21/6833



Abstract: a substrate support carrier includes an electrostatic chuck (esc) assembly includes a top ceramic disc having a recess formed from a lower surface of the top ceramic disc, a bottom ceramic disc having a hole through the bottom ceramic disc, an upper bonding layer interposed between the lower surface of the top ceramic disc and an upper surface of the bottom ceramic disc, and a porous plug within at least one of the recess of the top ceramic disc and the hole of the bottom ceramic disc, a temperature control base, and a lower bonding layer interposed between a lower surface of the bottom ceramic disc and an upper surface of the temperature control base.


20240251546. DRAM Transistor Including Pillars Formed Using Low-Temperature Ion Implant_simplified_abstract_(applied materials, inc.)

Inventor(s): Sipeng Gu of Clifton Park NY (US) for applied materials, inc., Qintao Zhang of Mt Kisco NY (US) for applied materials, inc.

IPC Code(s): H10B12/00

CPC Code(s): H10B12/34



Abstract: disclosed herein are approaches for forming a dynamic random-access memory device (dram). in one approach, a method may include forming a plurality of bridge layers in a substrate by directing first ions into the substrate while the substrate is at a low temperature, wherein the ions are directed into the substrate in a series of implants, and annealing the plurality of bridge layers. the method may further include forming a contact by directing second ions into an upper surface of the plurality of bridge layers while the substrate is at the low temperature, and forming a pillar over the contact.


Applied Materials, Inc. patent applications on July 25th, 2024