Applied Materials, Inc. patent applications on December 19th, 2024
Patent Applications by Applied Materials, Inc. on December 19th, 2024
Applied Materials, Inc.: 30 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01J37/32 (12), H01L21/02 (7), H01L21/67 (4), H01L21/311 (4), H01L21/683 (4) H01L21/6833 (2), H01J37/3244 (2), H01J37/32724 (2), B25J9/163 (1), H01L21/02164 (1)
With keywords such as: layer, substrate, body, material, processing, surface, methods, gas, include, and chamber in patent application abstracts.
Patent Applications by Applied Materials, Inc.
20240416514. CALIBRATION SYSTEM_simplified_abstract_(applied materials, inc.)
Inventor(s): Nicholas Michael Kopec of Sunnyvale CA (US) for applied materials, inc., Lyle Kosinski of San Jose CA (US) for applied materials, inc., Matvey Farber of Redwood City CA (US) for applied materials, inc., Jeffrey Hudgens of San Francisco CA (US) for applied materials, inc.
IPC Code(s): B25J9/16, B25J21/00, H01L21/00, H01L21/67, H01L21/673
CPC Code(s): B25J9/163
Abstract: a calibration system is of a wafer processing system. the calibration system includes a calibration substrate configured to be disposed on a plurality of support structures of the wafer processing system. the calibration substrate includes a calibration pin. the calibration substrate enables a calibration operation of a robot arm of the wafer processing system to automatically determine robot arm error of the robot arm.
Inventor(s): Peter J. GUERCIO of Queen Creek AZ (US) for applied materials, inc., Paul WESTPHAL of Scottsdale AZ (US) for applied materials, inc., Kirk Allen FISHER of Tempe AZ (US) for applied materials, inc.
IPC Code(s): C01B32/318, C01B32/336, C01B32/372, C23C16/02, C23C16/32, C23C16/44
CPC Code(s): C01B32/318
Abstract: the present invention relates to a new process for manufacturing a silicon carbide (sic) coated body by depositing sic in a chemical vapor deposition method using dimethyldichlorosilane (dms) as the silane source on a graphite substrate. a further aspect of the present invention relates to the new silicon carbide coated body, which can be obtained by the new process of the present invention, and to the use thereof for manufacturing articles for high temperature applications, susceptors and reactors, semiconductor materials, and wafer.
Inventor(s): David Alexander SELL of Santa Clara CA (US) for applied materials, inc., Evan WANG of Palo Alto CA (US) for applied materials, inc., Simon LORENZO of Santa Clara CA (US) for applied materials, inc., Kevin MESSER of Mountain View CA (US) for applied materials, inc.
IPC Code(s): G02B27/01, G02B6/34
CPC Code(s): G02B27/0172
Abstract: single-sheet waveguide combiners having increased field-of-view for multiple colors by enabling separate action on different colors without creating spurious paths are provided. a waveguide includes a first region including an in-coupler (ic) grating for a first color; a second region including an ic grating for a second color and a third color; a third region including an out-coupler (oc) grating for the first color and an eye-pupil-expander (epe) grating for the second color and the third color; a fourth region including an epe grating for the first color; and a fifth region including an oc grating for the second color and the third color and an epe grating for the first color, wherein the fifth region at least partially overlaps with the third region.
Inventor(s): Lin ZHOU of Santa Clara CA (US) for applied materials, inc., Gabriela ALVA of Santa Clara CA (US) for applied materials, inc., Zhiyu HUANG of Santa Clara CA (US) for applied materials, inc., Yung-chen LIN of Los Angeles CA (US) for applied materials, inc., Chi-I LANG of Cupertino CA (US) for applied materials, inc.
IPC Code(s): G03F7/38, G03F7/004, G03F7/20
CPC Code(s): G03F7/38
Abstract: embodiments discloses herein describe methods for treating a substrate. in one example, a method of treating a layer of a film stack includes pre-treating a surface of an underlayer of a film stack formed on a substrate and forming a metal oxide in a photoresist layer of the film stack by heating a methyl-containing material in a processing environment proximate a film stack. the film stack includes the photoresist layer disposed on top of and in contact with an underlayer, and the underlayer disposed on top of a substrate. the metal oxide implanted photoresist later is then etched.
Inventor(s): Michael Howells of San Jose CA (US) for applied materials, inc., Thorsten Kril of Santa Cruz CA (US) for applied materials, inc., Hemanth Konanur Nagendra of Santa Clara CA (US) for applied materials, inc., Jatinder Sasan of San Jose CA (US) for applied materials, inc.
IPC Code(s): G05B19/4155, G05B19/18
CPC Code(s): G05B19/4155
Abstract: an electronic device manufacturing system that includes a process tool, an evaluation system, and a communication node. the communication node is configured to obtain one or more attributes from the evaluation system and identify a data collection plan that is based on the one or more attributes. the communication node is further configured to register with the process tool to receive data according to the data collection plan and receive, from the process tool, data according to the data collection plan. the communication node is further configured to send the received data to the evaluation system.
Inventor(s): Fei Li of Houston TX (US) for applied materials, inc., Jimmy Iskandar of Fremont CA (US) for applied materials, inc., Michael D. Armacost of San Jose CA (US) for applied materials, inc.
IPC Code(s): G06F21/60, G06F21/62, H04L9/08
CPC Code(s): G06F21/602
Abstract: an electronic device manufacturing system configured to receive, by a first computing system, a request for manufacturing process data request. the system further uses a first cryptographic key controlled by a first entity and a second cryptographic key controlled by a second entity, a database management system to retrieve the manufacturing process data from a data store. the system further obtains, using the database management system, the manufacturing process data stored in the data store. the manufacturing process data is encrypted. the system further sends the encrypted manufacturing process data to a second computing system configured to perform one or more anonymization operations on the manufacturing process data.
Inventor(s): Aaron P. WEBB of Austin TX (US) for applied materials, inc., Krag R. SENIOR of Austin TX (US) for applied materials, inc., Chris CZAJKA of Dripping Springs TX (US) for applied materials, inc., Charles T. CARLSON of Cedar Park TX (US) for applied materials, inc., Jason M. SCHALLER of Austin TX (US) for applied materials, inc.
IPC Code(s): H01J37/30, H01J37/317, H05H9/04
CPC Code(s): H01J37/3007
Abstract: an ion implantation system including an ion source for generating an ion beam, an end station for holding a substrate to be implanted by the ion beam, and a linear accelerator disposed between the ion source and the end station and adapted to accelerate the ion beam, the linear accelerator comprising at least one acceleration stage including a resonator coil coupled to a drift tube assembly, the drift tube assembly including a first drift tube coupled to a first end of a first insulting rod via interference fit, a second drift tube coupled to a first end of a second insulting rod via interference fit, and a mounting bracket coupled to a second end of the first insulting rod and to a second end of the second insulting rod via interference fit.
20240420920. INTEGRATED GAS BOX AND ION SOURCE_simplified_abstract_(applied materials, inc.)
Inventor(s): William H. Leavitt of Haverhill MA (US) for applied materials, inc., Shengwu Chang of South Hamilton MA (US) for applied materials, inc., William H. Park, JR. of Marblehead MA (US) for applied materials, inc.
IPC Code(s): H01J37/317, H01J37/08, H01J37/32
CPC Code(s): H01J37/3171
Abstract: an integrated gas box is disclosed. the integrated gas box is an enclosure, wherein one wall of the enclosure includes an aperture. a bushing is affixed to the exterior of this wall. the distal end of the bushing has a flange that is affixed to a wall of the vacuum chamber. the ion source is introduced into the bushing through an access door in the enclosure and slides into the aperture. the base flange of the ion source is sufficiently large such that it cannot pass through the aperture and forms a seal between the bushing and the interior of the integrated gas box. the integrated gas box includes the gas canisters and associated valves which are used to supply feed gas and diluent gasses to the ion source. the integrated gas box also houses the power supplies used to bias the components within the ion source.
Inventor(s): Kenneth S. Collins of San Jose CA (US) for applied materials, inc., Tianhong Wang of Sunnyvale CA (US) for applied materials, inc., Kartik Ramaswamy of San Jose CA (US) for applied materials, inc., Craig Anton Rosslee of San Jose CA (US) for applied materials, inc., Oscar Lopez of San Jose CA (US) for applied materials, inc., Michael Rice of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32119
Abstract: embodiments disclosed herein include immersed inductively coupled and capacitively coupled plasma excitation methods, apparatuses and processes for large area substrates. a process chamber includes a pedestal for supporting a workpiece in a processing volume, an array of inductive elements in a portion of the processing volume above the pedestal, and a chamber top or lid over the array of inductive elements.
Inventor(s): Amit Sahu of Bangalore (IN) for applied materials, inc., Shashidhara Patel H B of Bangalore (IN) for applied materials, inc., Muhannad Mustafa of Milpitas CA (US) for applied materials, inc., Rakesh Ramadas of San Jose CA (US) for applied materials, inc., Sanjeev Baluja of Campbell CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/67
CPC Code(s): H01J37/3244
Abstract: cooling flanges and semiconductor manufacturing processing chamber comprising the cooling flanges are disclosed. the cooling flanges comprise a flange body with a gas channel extending through the length thereof. the gas channel has an inlet funnel, a middle channel and an outlet funnel with a purge gas inlet in a side of the flange body. the purge gas inlet connects to the middle channel of the gas channel.
Inventor(s): Michael R. RICE of Pleasanton CA (US) for applied materials, inc., Hanish Kumar PANAVALAPPIL KUMARANKUTTY of Bangalore (IN) for applied materials, inc., Steven D. MARCUS of San Jose CA (US) for applied materials, inc., Kirubanandan Naina SHANMUGAM of Bangalore (IN) for applied materials, inc., Sriharsha DHARMAPURA SATHYANARAYANAMURTHY of Bengaluru (IN) for applied materials, inc., Madhukar KRISHNA of Bengaluru (IN) for applied materials, inc., Shivaprakash Padadayya HIREMATH of Bangalore (IN) for applied materials, inc., Senthil Kumar NATTAMAI SUBRAMANIAN of Hosur (IN) for applied materials, inc., Sankar Menon CHERUBALA PATHAYAPURA of () for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/455, C23C16/458, C23C16/46
CPC Code(s): H01J37/3244
Abstract: methods and apparatus for coating processing reactor component parts are provided herein. in some embodiments, a method for coating a part via atomic layer deposition includes: fastening a workpiece to be coated to an interior volume facing portion of a part coating reactor; and performing an ald process on the fastened workpiece within the part coating reactor.
20240420932. SUBSTRATE SUPPORT_simplified_abstract_(applied materials, inc.)
Inventor(s): Yogananda Sarode Vishwanath of Bangalore (IN) for applied materials, inc., Xue Yang Chang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/683, H01L21/687
CPC Code(s): H01J37/32724
Abstract: substrate support components including an integrally formed insulator body including a first surface and a second surface opposite the first surface, and a thickness of the insulator body exceeds an arcing threshold between the first body and the second body when the insulator body is arranged between a first electrically conductive body and a second electrically conductive body. the insulator body includes gas conduits within the insulator body and forming a gas flow path from the first surface to the second surface, including a gas conductance plug embedded within a first portion of the gas conduit and having at least a threshold gas conductance through the gas conductance plug, wherein the gas conductance plug obstructs an electrical discharge path between the first body and the second body when the insulator body is arranged with respect to the first body and the second body.
Inventor(s): Amir H. Tavakoli of San Jose CA (US) for applied materials, inc., Jian Li of Fremont CA (US) for applied materials, inc., Peter Reimer of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/683
CPC Code(s): H01J37/32724
Abstract: substrate support assembly and methods of making such substrate support assemblies are provided. substrate support assemblies include an electrostatic chuck body defining a substrate support surface, a support stem coupled with the electrostatic chuck body, and an electrode embedded within the electrostatic chuck body. substrate support surfaces exhibit a resistivity of 1�10�-cm to 1�10�-cm at a temperature of greater than 650� c. substrate support surfaces can include a composite ceramic material having a base dielectric material and a second dielectric material having an electrical resistivity at least about two times higher than an electrical resistivity of the base dielectric material at a temperature of greater than 650� c.
Inventor(s): Bhaskar Soman of San Jose CA (US) for applied materials, inc., Yanze Wu of Sunnyvale CA (US) for applied materials, inc., Zeqing Shen of San Jose CA (US) for applied materials, inc., Supriya Ghosh of San Jose CA (US) for applied materials, inc., Susmit Singha Roy of Campbell CA (US) for applied materials, inc., Abhijit Basu Mallick of Sunnyvale CA (US) for applied materials, inc., Siyao Wang of San Jose CA (US) for applied materials, inc., Keith Tatseun Wong of North Bend WA (US) for applied materials, inc., Lakmal C. Kalutarage of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/02, H01L21/311
CPC Code(s): H01J37/32816
Abstract: exemplary methods of semiconductor processing may include methods for nonconformally building up silicon-and-oxygen-containing material where the top of the feature preferentially fills at a slower rate as compared to the bottom of the feature. such methods may include iterative nonconformal etching operations and/or iterative nonconformal inhibition operations. for example, after building up a layer comprising silicon-and-oxygen-containing material, the layer may be nonconformally etched before building up another layer comprising silicon-and-oxygen-containing material. in another example, in the building up of the layer, an inhibitor may be introduced preferentially at and near the top of the features to provide nonconformal buildup of the silicon-and-oxygen-containing material.
Inventor(s): Yu Cheng LIU of Tainan City (TW) for applied materials, inc., Cheng-yuan LIN of Tainan City (TW) for applied materials, inc., Hsiang AN of San Jose CA (US) for applied materials, inc., Sam S. WANG of Tainan City (TW) for applied materials, inc.
IPC Code(s): H01J37/34, H01J37/317, H01J37/32
CPC Code(s): H01J37/3435
Abstract: embodiments of the present disclosure provide a radio frequency (rf) return device. one example rf return device generally includes a bracket for coupling to a chamber body, a cover coupled to the bracket, and a contact plate coupled to the cover and configured contact a substrate support. using the rf return device described herein generally enables a reduction in temperature that the rf return device and its various components are exposed to, increasing the durability and lifetime of the rf return device. in addition, the rf return device disclosed herein may block chemicals (e.g., fluorine (f)) used in the process chamber from attacking components included in the rf return device, thereby providing enhanced protection to the rf return device.
Inventor(s): Shiyu YUE of Santa Clara CA (US) for applied materials, inc., Jiajie CEN of Santa Clara CA (US) for applied materials, inc., Sahil Jaykumar PATEL of Sunnyvale CA (US) for applied materials, inc., Zhimin QI of Santa Clara CA (US) for applied materials, inc., Ju Hyun OH of San Jose CA (US) for applied materials, inc., Aixi ZHANG of Santa Clara CA (US) for applied materials, inc., Xingyao GAO of Santa Jose CA (US) for applied materials, inc., Wei LEI of Santa Clara CA (US) for applied materials, inc., Yi XU of San Jose CA (US) for applied materials, inc., Yu LEI of Belmont CA (US) for applied materials, inc., Tsung-Han YANG of San Jose CA (US) for applied materials, inc., Xiaodong WANG of San Jose CA (US) for applied materials, inc., Xiangjin XIE of Fremont CA (US) for applied materials, inc., Yixiong YANG of San Jose CA (US) for applied materials, inc., Kevin KASHEFI of Dublin CA (US) for applied materials, inc., Rongjun WANG of Dublin CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/311
CPC Code(s): H01L21/02046
Abstract: a method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (mocl, mocl) at a temperature of between 250� c. and 350� c., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.
Inventor(s): Abhijeet S. Bagal of Sunnyvale CA (US) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc., Kuan-Ting Liu of Santa Clara CA (US) for applied materials, inc., Chung Liu of Hillsborough CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/263
CPC Code(s): H01L21/02115
Abstract: semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. a deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. a deposition plasma having an electron temperature less than or about 4 ev is generated from the deposition gas. the methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.
Inventor(s): Woongsik Nam of Santa Clara CA (US) for applied materials, inc., Euhngi Lee of San Jose CA (US) for applied materials, inc., Tianyang Li of San Jose CA (US) for applied materials, inc., Jisung Park of Sunnyvale CA (US) for applied materials, inc., Hang Yu of San Jose CA (US) for applied materials, inc., Deenesh Padhi of Saratoga CA (US) for applied materials, inc., Shichen Fu of Santa Clara CA (US) for applied materials, inc., Yufeng Jiang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/02164
Abstract: exemplary processing methods may include i) providing one or more deposition precursors to a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. the substrate may include one or more features defining one or more sidewalls. the methods may include ii) forming plasma effluents of the one or more deposition precursors. the methods may include iii) contacting the substrate with the plasma effluents of the one or more deposition precursors. the contacting may deposit a doped silicon-and-oxygen-containing material on the substrate. a first portion of the doped silicon-and-oxygen-containing material deposited on the one or more sidewalls of the one or more features may be characterized by a poorer film quality than a second portion of the doped silicon-and-oxygen-containing material deposited on a lower portion of the one or more features.
Inventor(s): Xiang Ji of Cupertino CA (US) for applied materials, inc., Shuchi Sunil Ojha of Sunnyvale CA (US) for applied materials, inc., Praket Prakash Jha of San Jose CA (US) for applied materials, inc., Jingmei Liang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/3205, H01L21/3213, H01L21/768
CPC Code(s): H01L21/02252
Abstract: exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. a substrate may be housed in the processing region. the substrate may define a feature. the methods may include forming plasma effluents of the silicon-containing precursor and depositing a silicon-containing material on the substrate. the methods may include providing a hydrogen-containing precursor to the processing region, forming plasma effluents of the hydrogen-containing precursor, and etching the silicon-containing material from a sidewall of the feature.
Inventor(s): Bhaskar Soman of San Jose CA (US) for applied materials, inc., Supriya Ghosh of San Jose CA (US) for applied materials, inc., Yanze Wu of Sunnyvale CA (US) for applied materials, inc., Zeqing Shen of San Jose CA (US) for applied materials, inc., Susmit Singha Roy of Campbell CA (US) for applied materials, inc., Abhijit Basu Mallick of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/3205, H01L21/321
CPC Code(s): H01L21/0228
Abstract: exemplary methods of semiconductor processing may include iteratively repeating a deposition cycle several times on a substrate disposed within a processing region of a semiconductor processing chamber. each deposition cycle may include depositing a silicon-containing material on the substrate and exposing the silicon-containing material to a first oxygen plasma to convert the silicon-containing material to a silicon-and-oxygen-containing material. after the iterative repeating of the deposition cycle, the method may include performing a densification operation by exposing the silicon-and-oxygen-containing material to a second oxygen plasma to produce a densified silicon-and-oxygen-containing material where the quality of the densified silicon-and-oxygen-containing material is greater than the silicon-and-oxygen-containing material. the method may further include iteratively repeating the iteratively repeated deposition cycles and the densification operation several times.
Inventor(s): Rui Lu of Santa Clara CA (US) for applied materials, inc., Bo Xie of San Jose CA (US) for applied materials, inc., Wei Liu of Fremont CA (US) for applied materials, inc., Shanshan Yao of San Jose CA (US) for applied materials, inc., Xiaobo Li of San Jose CA (US) for applied materials, inc., Jingmei Liang of San Jose CA (US) for applied materials, inc., Li-Qun Xia of Cupertino CA (US) for applied materials, inc., Shankar Venkataraman of San Jose CA (US) for applied materials, inc., Chi-I Lang of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01L21/02
CPC Code(s): H01L21/0234
Abstract: exemplary processing methods may include providing a treatment precursor to a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. the substrate may include a layer of a silicon-containing material. the methods may include forming inductively-coupled plasma effluents of the treatment precursor. the methods may include contacting the layer of the silicon-containing material with the inductively-coupled plasma effluents of the treatment precursor to produce a treated layer of the silicon-containing material. the contacting may reduce a dielectric constant of the layer of the silicon-containing material.
Inventor(s): Doreen Wei Ying Yong of Singapore (SG) for applied materials, inc., Tuck Foong Koh of Singapore (SG) for applied materials, inc., John Sudijono of Singapore (SG) for applied materials, inc., Mikhail Korolik of San Jose CA (US) for applied materials, inc., Paul E. Gee of San Jose CA (US) for applied materials, inc., Thai Cheng Chua of Cupertino CA (US) for applied materials, inc., Philip A. Kraus of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/311, H01J37/32
CPC Code(s): H01L21/31116
Abstract: embodiments of the present disclosure are directed to selective etching processes. the processes include an etching chemistry (a plasma of a fluorine-containing precursor and a first gas mixture), and a passivating chemistry (a plasma of a sulfur-containing precursor and a second gas mixture). in some embodiments, the sulfur-containing precursor and the second gas mixture are present in a ratio of sulfur-containing precursor to second gas mixture in a range of from 0.01 to 5. the methods include etching a substrate having a plurality of alternating layers of silicon oxide and silicon nitride thereon and a trench formed through the plurality of alternating layers. the silicon nitride layers are selectively etched relative to the silicon oxide layers at an etch selectivity of greater than or equal to 500:1.
20240420966. COPPER REFLOW BY SURFACE MODIFICATION_simplified_abstract_(applied materials, inc.)
Inventor(s): Zhiyuan Wu of San Jose CA (US) for applied materials, inc., Zheng Ju of Sunnyvale CA (US) for applied materials, inc., Feng Chen of San Jose CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc., Feng Q. Liu of San Jose CA (US) for applied materials, inc., Jeffrey W. Anthis of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/3213, H01L21/3205
CPC Code(s): H01L21/32133
Abstract: embodiments of the disclosure relate to methods of etching a copper material. in some embodiments, the copper material is exposed to a halide reactant to form a copper halide species. the substrate is then heated to remove the copper halide species. in some embodiments, the etching methods are performed at relatively low temperatures. additional embodiments of the disclosure relate to methods of copper gapfill. in some embodiments, a copper material within a substrate feature is exposed to a halide reactant to form a copper halide species. the copper halide species is then heated and flowed to fill at least a portion of the substrate feature. the reflow methods are performed at lower temperatures than similar reflow methods without formation of the copper halide species.
Inventor(s): Varoujan Chakarian of San Jose CA (US) for applied materials, inc., Blake W Erickson of Gilroy CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, G01J3/02, G01J3/32, G01J3/36, G01N33/00, H01J37/32, H01L21/66
CPC Code(s): H01L21/67253
Abstract: the disclosure describes apparatus and method for detecting an endpoint in plasma-assisted wafer processing in a chamber. a fiber array comprising a plurality of fibers collects optical emission light from the chamber during the plasma-assisted wafer processing. the fiber array is split into two or more sub-arrays of fibers, each group carrying a portion of the light to a segment of a photodetector. each segment of photodetector has a corresponding narrowband optical filter designed for a specific range of wavelengths. a computer processor analyzes detected signals from the plurality of segments of the photodetector, and determines, based on the analysis of the detected signals, an endpoint of the plasma-assisted wafer processing as indicated by the presence or the absence of the one or more chemical species in the chamber. the photodetector can be based on photomultiplier tubes (pmt), specifically multi-anode pmt.
Inventor(s): Jeffrey C. Hudgens of San Francisco CA (US) for applied materials, inc., Ulrich Oldendorf of Darmstadt (DE) for applied materials, inc.
IPC Code(s): H01L21/677, B65G54/02, H01L21/67
CPC Code(s): H01L21/67709
Abstract: disclosed herein are systems and methods relating to a transfer chamber for an electronic device processing system. the transfer chamber includes a first magnetic levitation platform, having a magnetic levitation track disposed along a horizontal length of the transfer chamber and configured to generate a first magnetic field. the transfer chamber also includes a second magnetic levitation track disposed along a horizontal width of the transfer chamber and configured to generate a second magnetic field. a first plane of the first magnetic field crosses a second plane of the second magnetic field at a junction. the platform further includes at least one substrate carrier configured to move according to at least one of the first magnetic field or the second magnetic field.
20240420984. ELECTROSTATIC SUBSTRATE SUPPORT_simplified_abstract_(applied materials, inc.)
Inventor(s): Andrew Nguyen of San Jose CA (US) for applied materials, inc., Yogananda Sarode Vishwanath of Bangalore (IN) for applied materials, inc., Tom K. Cho of Los Altos Hills CA (US) for applied materials, inc., Jennifer Y. Sun of Mountain View CA (US) for applied materials, inc., Xue Yang Chang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/683, H01J37/32, H01L21/3065, H01L21/673
CPC Code(s): H01L21/6833
Abstract: an electrostatic chuck (esc) including a ceramic body having a first surface with two or more regions defined on the first surface arranged concentrically with respect to each other on the first surface. each region includes a retaining ring arranged on the first surface and defining an outer edge of the region, and structures arranged on the first surface and within the region configured to support a surface of a substrate when the substrate is retained by the electrostatic chuck. the esc includes gas conduits configured to introduce a gas into the two or more regions through the ceramic body and to the first surface, and embedded electrodes within the ceramic body and arranged with respect to the first surface and configured to generate a retaining force on the surface of the substrate.
20240420986. FORMING MESAS ON AN ELECTROSTATIC CHUCK_simplified_abstract_(applied materials, inc.)
Inventor(s): Wendell Glenn BOYD, JR. of Morgan Hill CA (US) for applied materials, inc., Stanley WU of San Ramon CA (US) for applied materials, inc., Matthew BOYD of Morgan Hill CA (US) for applied materials, inc.
IPC Code(s): H01L21/683, C23C16/02, C23C16/30, C23C16/458
CPC Code(s): H01L21/6833
Abstract: a body of an electrostatic chuck comprises mesas disposed on a polished surface of the body. each of the mesas comprises an adhesion layer disposed on the polished surface of the body, a transition layer disposed over the adhesion layer, and a coating layer disposed over the transition layer. the coating layer has a hardness of at least 14 gpa. the body further comprises a sidewall coating disposed over a sidewall of the body. a method for preparing the body comprises polishing the surface of the body and cleaning the polished surface. the method further comprises depositing the mesas by depositing the adhesion layer on the body, the transition layer over the adhesion layer, and the coating layer over the transition layer. further, the method includes, polishing the mesas.
Inventor(s): Jiajie Cen of San Jose CA (US) for applied materials, inc., Zhiyuan Wu of San Jose CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc., Yong Jin Kim of Albany CA (US) for applied materials, inc., Yang Zhou of Milpitas CA (US) for applied materials, inc., Zheng Ju of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01J37/32, H01L21/311
CPC Code(s): H01L21/76844
Abstract: methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. the methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (sam) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (sam) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.
Inventor(s): Yang Zhou of Milpitas CA (US) for applied materials, inc., Jiajie Cen of San Jose CA (US) for applied materials, inc., Zhiyuan Wu of San Jose CA (US) for applied materials, inc., Ge Qu of Sunnyvale CA (US) for applied materials, inc., Yong Jin Kim of Albany CA (US) for applied materials, inc., Zheng Ju of Sunnyvale CA (US) for applied materials, inc., Feng Chen of San Jose CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc.
IPC Code(s): H01L21/768
CPC Code(s): H01L21/76846
Abstract: methods of forming devices comprise forming a dielectric material on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. the methods include passivating a metal material at a bottom of the gap with an alkyl reactant to form a passivation layer on the metal material, the gap defined by the bottom and sidewalls comprising the dielectric material with having a barrier layer thereon. a metal liner is selectively deposited on the barrier layer on the sidewall over the passivation layer on the bottom.
20240423015. FLEXIBLE COVER LENS FILMS_simplified_abstract_(applied materials, inc.)
Inventor(s): Manivannan THOTHADRI of Mountain View CA (US) for applied materials, inc., Daniel Paul FORSTER of San Jose CA (US) for applied materials, inc., Robert F. PRAINO, Jr. of Westwood MA (US) for applied materials, inc., Harvey YOU of Mountain View CA (US) for applied materials, inc.
IPC Code(s): H10K50/844, G02F1/1333, G02F1/1335, H10K77/10, H10K102/00
CPC Code(s): H10K50/844
Abstract: flexible display devices, such as flexible cover lens films, are discussed and provided herein. the flexible cover lens film has good strength, elasticity, optical transmission, wear resistance, and thermostability. the cover lens film includes a hard coat layer with a thickness from about 5 �m to 40 �m, an impact absorption layer with a thickness from about 20 �m to 110 �m, and a substrate layer with a thickness from about 10 �m to 175 �m and is disposed between the hard coat layer and the impact absorption layer. by combining the hard coat layer and the impact resistant layer, the cover lens film is both flexible and strong with hardness from 6h to 9h.
Applied Materials, Inc. patent applications on December 19th, 2024
- Applied Materials, Inc.
- B25J9/16
- B25J21/00
- H01L21/00
- H01L21/67
- H01L21/673
- CPC B25J9/163
- Applied materials, inc.
- C01B32/318
- C01B32/336
- C01B32/372
- C23C16/02
- C23C16/32
- C23C16/44
- CPC C01B32/318
- G02B27/01
- G02B6/34
- CPC G02B27/0172
- G03F7/38
- G03F7/004
- G03F7/20
- CPC G03F7/38
- G05B19/4155
- G05B19/18
- CPC G05B19/4155
- G06F21/60
- G06F21/62
- H04L9/08
- CPC G06F21/602
- H01J37/30
- H01J37/317
- H05H9/04
- CPC H01J37/3007
- H01J37/08
- H01J37/32
- CPC H01J37/3171
- CPC H01J37/32119
- CPC H01J37/3244
- C23C16/455
- C23C16/458
- C23C16/46
- H01L21/683
- H01L21/687
- CPC H01J37/32724
- H01L21/02
- H01L21/311
- CPC H01J37/32816
- H01J37/34
- CPC H01J37/3435
- CPC H01L21/02046
- H01L21/263
- CPC H01L21/02115
- CPC H01L21/02164
- H01L21/3205
- H01L21/3213
- H01L21/768
- CPC H01L21/02252
- H01L21/321
- CPC H01L21/0228
- CPC H01L21/0234
- CPC H01L21/31116
- CPC H01L21/32133
- G01J3/02
- G01J3/32
- G01J3/36
- G01N33/00
- H01L21/66
- CPC H01L21/67253
- H01L21/677
- B65G54/02
- CPC H01L21/67709
- H01L21/3065
- CPC H01L21/6833
- C23C16/30
- CPC H01L21/76844
- CPC H01L21/76846
- H10K50/844
- G02F1/1333
- G02F1/1335
- H10K77/10
- H10K102/00
- CPC H10K50/844
