Applied Materials, Inc. patent applications on August 8th, 2024

Patent Applications by Applied Materials, Inc. on August 8th, 2024

Applied Materials, Inc.: 23 patent applications

Applied Materials, Inc. has applied for patents in the areas of H01L21/67 (7), H01L21/66 (5), H01J37/32 (4), H01L21/768 (3), C23C14/54 (3) H01L22/12 (2), C23C14/505 (1), H01L21/68742 (1), H10B41/27 (1), H10B12/053 (1)

With keywords such as: substrate, layer, include, material, techniques, disposed, process, scl, processing, and further in patent application abstracts.

Patent Applications by Applied Materials, Inc.

20240263299. MODULE FOR FLIPPING SUBSTRATES IN VACUUM_simplified_abstract_(applied materials, inc.)

Inventor(s): Karunakaran NATARAJ of Coimbatore (IN) for applied materials, inc., Sathiyamurthi GOVINDASAMY of Coimbatore (IN) for applied materials, inc., Suresh PALANISAMY of Coimbatore (IN) for applied materials, inc., Harish V. PENMETHSA of Dublin CA (US) for applied materials, inc., Naresh Kumar ASOKAN of Coimbatore (IN) for applied materials, inc.

IPC Code(s): C23C14/50, C23C14/52

CPC Code(s): C23C14/505

Abstract: apparatus and methods for flipping substrates in vacuum between pvd sputtering of each side for increasing throughput are provided herein. in some embodiments disclosed herein, a module of a processing system for flipping a substrate in vacuum is provided. the module includes a clamp assembly for securing the substrate, a motor assembly coupled to the substrate clamp assembly, for rotating the clamp assembly, a lift pin assembly, and a lift pin actuator for raising and lowering the lift pin assembly.

20240264336. NON-LINE-OF-SIGHT DEPOSITION OF COATING ON INTERNAL COMPONENTS OF ASSEMBLED DEVICE_simplified_abstract_(applied materials, inc.)

Inventor(s): Alexander Berger of Palo Alto CA (US) for applied materials, inc., Cheng-Hsuan Chou of Santa Clara CA (US) for applied materials, inc., David Knapp of Santa Clara CA (US) for applied materials, inc.

IPC Code(s): G02B1/14, B05D1/00, B05D7/22, C23C16/04, G02B3/00

CPC Code(s): G02B1/14

Abstract: described herein is a method of depositing a conformal, optically transparent coating onto a surface of one or more internal components that are enclosed within an assembled device including an optical encoder using a non-line-of-sight deposition process without altering a structure of the assembled device or impacting functionality of the assembled device. also described is an assembled device including an optical encoder, where one or more internal components enclosed within the optical encoder and a coating deposited onto a surface of the internal components, where the coating is a conformal, optically transparent coating that is resistant to corrosion by at least one of fluorine-, chlorine-, sulfur-, hydrogen-, bromine-, or nitrogen-based acids and that does not negatively impact functionality of the internal components.

20240266146. PLASMA PROCESSING IMPROVEMENT_simplified_abstract_(applied materials, inc.)

Inventor(s): Christopher S. OLSEN of Fremont CA (US) for applied materials, inc., Rene GEORGE of San Carlos CA (US) for applied materials, inc., Victor CALDERON of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): H01J37/32

CPC Code(s): H01J37/32422

Abstract: a process chamber is provided including a chamber body disposed around a process volume, the process volume bounded by one or more interior side walls; a substrate support in the process volume; a plasma source disposed over the substrate support, the plasma source having a top and one or more sides disposed around a plasma-generating volume; and a first deflector positioned at least partially in the process volume, the first deflector comprising an annular body having a top, a bottom, one or more outer side surfaces connecting the top with the bottom, and one or more inner side surfaces connecting the top with the bottom. the one or more outer side surfaces of the annular body are spaced apart from the one or more interior side walls of the process volume.

20240266152. PLASMA UNIFORMITY CONTROL SYSTEM AND METHODS_simplified_abstract_(applied materials, inc.)

Inventor(s): Michael Andrew STEARNS of San Jose CA (US) for applied materials, inc., Alok RANJAN of Santa Clara CA (US) for applied materials, inc., Kartik RAMASWAMY of San Jose CA (US) for applied materials, inc., Peng TIAN of Santa Clara CA (US) for applied materials, inc., Timothy Joseph FRANKLIN of Campbell CA (US) for applied materials, inc., Chris BLANK of Santa Clara CA (US) for applied materials, inc., Carlaton WONG of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): H01J37/32, H01F27/28, H01L21/3065

CPC Code(s): H01J37/3266

Abstract: embodiments of the present disclosure include an apparatus and methods for the plasma processing of a substrate. some embodiments are directed to a plasma processing chamber. the plasma processing chamber generally includes a planar coil region comprising a concentric coil region comprising a first concentric coil and a second concentric coil, and a power supply circuit coupled to the first concentric coil and the second concentric coil. the first concentric coil may include a first coil with a diameter measured in a direction parallel to a first plane that is smaller than the diameter of a second coil included in the second concentric coil. the power supply circuit may be configured to bias the first concentric coil and the second concentric coil to adjust a generated magnetic field in a region of control of a plasma in the plasma processing chamber to control a plasma density of the plasma.

20240266163. TREATMENTS TO ENHANCE MATERIAL STRUCTURES_simplified_abstract_(applied materials, inc.)

Inventor(s): Srinivas GANDIKOTA of Santa Clara CA (US) for applied materials, inc., Yixiong YANG of San Jose CA (US) for applied materials, inc., Jacqueline Samantha WRENCH of Santa Clara CA (US) for applied materials, inc., Yong YANG of Mountain View CA (US) for applied materials, inc., Steven C. H. HUNG of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): H01L21/02, H01L21/28, H01L21/67

CPC Code(s): H01L21/02247

Abstract: a method of forming a high-� dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-� dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-� dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-� dielectric cap layer, and removing the sacrificial silicon cap layer.

20240266171. BORON CONCENTRATION TUNABILITY IN BORON-SILICON FILMS_simplified_abstract_(applied materials, inc.)

Inventor(s): Yi Yang of San Jose CA (US) for applied materials, inc., Krishna Nittala of San Jose CA (US) for applied materials, inc., Rui Cheng of San Jose CA (US) for applied materials, inc., Karthik Janakiraman of San Jose CA (US) for applied materials, inc., Diwakar Kedlaya of San Jose CA (US) for applied materials, inc., Zubin Huang of Santa Clara CA (US) for applied materials, inc., Aykut Aydin of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): H01L21/033, C23C16/38

CPC Code(s): H01L21/0337

Abstract: embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. the methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (h) into the substrate processing region of the semiconductor processing chamber. the boron-containing precursor and the hmay be flowed at a boron-to-hydrogen flow rate ratio. the flow rate of the boron-containing precursor and the hmay be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. the boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.

20240266174. MITIGATION OF SADDLE DEFORMATION OF SUBSTRATES USING FILM DEPOSITION AND EDGE ION IMPLANTATION_simplified_abstract_(applied materials, inc.)

Inventor(s): Wonjae Lee of Fremont CA (US) for applied materials, inc., Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., D. Jeffrey Lischer of Acton MA (US) for applied materials, inc., Frank Sinclair of Hartland ME (US) for applied materials, inc.

IPC Code(s): H01L21/265, H01L21/66, H01L21/67

CPC Code(s): H01L21/265

Abstract: disclosed systems and techniques are directed to correct an out-of-plane deformation (opd) of a substrate. the techniques include obtaining, using optical inspection data, a profile of the out-of-plane deformation of the substrate and identifying, using the obtained profile, one or more parameters characterizing a saddle-shaped stress of the substrate. the techniques further include computing, using the one or more identified parameters, one or more characteristics of a stress-compensation layer (scl) for the substrate and causing the scl to be deposited on the substrate. the techniques further include causing a stress-mitigation beam to be applied to a plurality of edge regions of the scl, wherein settings of the stress-mitigation beam are determined using the one or more identified parameters.

20240266175. CARBON AND BORON IMPLANTATION FOR BACKSIDE CHEMICAL MECHANICAL PLANARIZATION CONTROL_simplified_abstract_(applied materials, inc.)

Inventor(s): Yan Zhang of Westford MA (US) for applied materials, inc., Johannes M. van Meer of Middleton MA (US) for applied materials, inc., Jae Young Lee of Bedford MA (US) for applied materials, inc., Naushad Variam of Marblehead MA (US) for applied materials, inc.

IPC Code(s): H01L21/265, H01L21/306, H01L21/768

CPC Code(s): H01L21/26506

Abstract: a method of processing a workpiece that will include a backside power delivery network is disclosed. the method includes forming a cmp marker layer in the workpiece at the depth to which the workpiece is to be thinned. this cmp marker layer, which may be a boron-rich layer, serves to slow the chemical-mechanical planarization (cmp) process. to minimize the diffusion of boron in this boron-rich layer, the boron-rich layer is sandwiched by implants of a first species of ions, where this first species of ions serves to slow the diffusion of the boron. in certain embodiments, carbon is used as the first species of ions.

20240266180. ENHANCED ETCH SELECTIVITY USING HALIDES_simplified_abstract_(applied materials, inc.)

Inventor(s): David Knapp of Santa Clara CA (US) for applied materials, inc., Feng Qiao of San Jose CA (US) for applied materials, inc., Hailong Zhou of San Jose CA (US) for applied materials, inc., Junkai He of San Jose CA (US) for applied materials, inc., Qian Fu of Pleasanton CA (US) for applied materials, inc., Mark J. Saly of Santa Clara CA (US) for applied materials, inc., Jeffrey Anthis of Redwood City CA (US) for applied materials, inc., Jayoung Choi of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01L21/3065, H10B12/00

CPC Code(s): H01L21/3065

Abstract: a method includes performing a dry etch process to remove a portion of a first layer disposed on a second layer of a stack of alternating layers. the first layer includes a first material and the second layer includes a second material different from the first material, and the dry etch process forms a passivation layer including a byproduct on surfaces of the second material. a amount of first material of the portion of the first layer remains after performing the dry etch process, the method further includes introducing a halide gas to enhance the passivation layer on the surfaces of the second material.

20240266185. SELECTIVE ETCHING OF SILICON-CONTAINING MATERIAL RELATIVE TO METAL-DOPED BORON FILMS_simplified_abstract_(applied materials, inc.)

Inventor(s): Han Wang of Sunnyvale CA (US) for applied materials, inc., Yu Yang of Sunnyvale CA (US) for applied materials, inc., Jing Zhang of Santa Clara CA (US) for applied materials, inc., Aykut Aydin of Sunnyvale CA (US) for applied materials, inc., Guoqing Li of Santa Clara CA (US) for applied materials, inc., Guangyan Zhong of Sunnyvale CA (US) for applied materials, inc., Rui Cheng of San Jose CA (US) for applied materials, inc., Gene H. Lee of San Jose CA (US) for applied materials, inc., Srinivas Guggilla of San Jose CA (US) for applied materials, inc., Sinae Heo of Santa Clara CA (US) for applied materials, inc., Eswaranand Venkatasubramanian of Santa Clara CA (US) for applied materials, inc., Abhijit Basu Mallick of Sunnyvale CA (US) for applied materials, inc., Karthik Janakiraman of San Jose CA (US) for applied materials, inc.

IPC Code(s): H01L21/311, H01L21/033

CPC Code(s): H01L21/31144

Abstract: exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. the metal-doped boron-containing material may include a metal dopant comprising tungsten. the substrate may include a silicon-containing material. the methods may include depositing one or more additional materials over the metal-doped boron-containing material. the one or more additional materials may include a patterned photoresist material. the methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. the methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. the methods may include etching the silicon-containing material with a fluorine-containing precursor. the metal dopant may enhance an etch rate of the silicon-containing material. the methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

20240266186. STRESS MANAGEMENT FOR PRECISE SUBSTRATE -TO- SUBSTRATE BONDING_simplified_abstract_(applied materials, inc.)

Inventor(s): San-Kuei Lin of Los Gatos CA (US) for applied materials, inc., Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., Wonjae Lee of Fremont CA (US) for applied materials, inc., Ramkumar Karur Shanmugam of Cupertino CA (US) for applied materials, inc.

IPC Code(s): H01L21/3115, C23C14/48, C23C14/54, G01B11/16, H01L21/66, H01L21/67

CPC Code(s): H01L21/31155

Abstract: disclosed systems and techniques are directed to mitigating stresses in substrate-to-substrate bonding processes. disclosed techniques include obtaining a first substrate supporting transferred feature(s) (tfs) and transferring tfs from the first substrate to a second substrate, transferring tfs from the first substrate to the second substrate, and applying stress mitigation to a target substrate. the target substrate can be the first substrate, an auxiliary substrate supporting tfs prior to transferring tfs from the auxiliary substrate to the first substrate, or the second substrate. applying stress mitigation to the target substrate includes obtaining an out-of-plane deformation (opd) profile of the target substrate, causing a stress compensation layer (scl) to be deposited on the target substrate, and exposing the scl to a stress-mitigation beam. settings of the scl and/or the stress-mitigation beam are determined using the opd profile of the target substrate.

20240266200. Electrostatic Chuck_simplified_abstract_(applied materials, inc.)

Inventor(s): Sarath BABU of Singapore (RS) for applied materials, inc., Mukund SUNDARARAJAN of Bangalore (IN) for applied materials, inc., Cheng-Hsiung TSAI of Cupertino CA (US) for applied materials, inc., Ananthkrishna JUPUDI of Singapore (SG) for applied materials, inc., Ross MARSHALL of Campbell CA (US) for applied materials, inc.

IPC Code(s): H01L21/683, H01L21/67

CPC Code(s): H01L21/6833

Abstract: an electrostatic chuck assembly including a body including a body recess and a heat transfer plate disposed in the body recess, wherein the heat transfer plate includes an upper surface, a lower surface, a first opening, and a second opening. the electrostatic chuck assembly further includes an rf transmission tube configured to transfer rf power to the lower surface of the heat transfer plate. the electrostatic chuck assembly further includes a puck bonded to the upper surface of the heat transfer plate. the electrostatic chuck assembly further includes a first chucking electrode disposed in the first opening and a second chucking electrode is disposed in the second opening, wherein the first and second chucking electrodes are configured to transfer a chucking voltage to the puck.

20240266206. LIFT PIN ASSEMBLY_simplified_abstract_(applied materials, inc.)

Inventor(s): Yogananda SARODE VISHWANATH of Bangalore (IN) for applied materials, inc., Anand KUMAR of Bangalore (IN) for applied materials, inc.

IPC Code(s): H01L21/687, C23C16/44, H01J37/32, H01L21/67, H01L21/683

CPC Code(s): H01L21/68742

Abstract: apparatuses for substrate transfer are provided. a lift pin assembly can include a lift pin, a purge cylinder, and a lift pin guide. the lift pin guide is disposed adjacent the purge cylinder. the lift pin guide and the purge cylinder have a passage formed therethrough in which the lift pin is disposed. the purge cylinder includes one or more nozzles that direct the flow of gas radially inward into a portion of the passage disposed in the purge cylinder. the one or more nozzles are disposed radially outward from the lift pin. the purge cylinder reduces particle deposition on the substrate by preventing contact between the lift pin and the support assembly as the lift pin is in motion.

20240266215. LOW STRESS TUNGSTEN LAYER DEPOSITION_simplified_abstract_(applied materials, inc.)

Inventor(s): Xi CEN of San Jose CA (US) for applied materials, inc., Yang LI of Sunnyvale CA (US) for applied materials, inc., Kai WU of Palo Alto CA (US) for applied materials, inc., Mehran BEHDJAT of Santa Clara CA (US) for applied materials, inc., Jallepally RAVI of San Ramon CA (US) for applied materials, inc.

IPC Code(s): H01L21/768, H01L21/3205

CPC Code(s): H01L21/76876

Abstract: a method of forming a structure on a substrate, includes forming a nucleation layer within an opening of the substrate within a processing chamber. the method further includes forming a passivation layer on at least a portion of the nucleation layer by introducing radical treatment into the processing chamber. the method further includes forming a tungsten fill layer within the opening over the passivation layer and the nucleation layer, wherein the tungsten fill layer is formed by a plurality of treatment cycles. each treatment cycle includes pulsing a first gas at the substrate for a pulse time duration while concurrently flowing a second gas over the substrate, and purging the first gas and the second gas by flowing a purge gas over the substrate for a purge time duration.

20240266220. INTEGRATED LASER AND PLASMA ETCH DICING_simplified_abstract_(applied materials, inc.)

Inventor(s): Jonathan Bryant MELLEN of Portland OR (US) for applied materials, inc., Clinton GOH of Singapore (SG) for applied materials, inc., Cheng SUN of Singapore (SG) for applied materials, inc.

IPC Code(s): H01L21/78, B23K26/38, B23K26/40, H01J37/32, H01L21/268, H01L21/3065, H01L21/67, H01L23/544

CPC Code(s): H01L21/78

Abstract: a method for dicing a die from a substrate for bonding that leverages laser and multiple etch processes. the method may include performing a laser cutting process to form a cut that removes a first portion of a dicing street in the substrate, performing a first plasma etch process to increase the laser kerf width to a first plasma etch width that is less than a dicing street width and to remove any non-silicon material from a bottom of the cut, and performing a second plasma etch process to increase the first plasma etch width to the dicing street width and to remove any remaining portion of the dicing street to completely separate the die from the substrate.

20240266230. OPTIMIZED FILM DEPOSITION AND ION IMPLANTATION FOR MITIGATION OF STRESS AND DEFORMATION IN SUBSTRATES_simplified_abstract_(applied materials, inc.)

Inventor(s): Wonjae Lee of Fremont CA (US) for applied materials, inc., Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., D. Jeffrey Lischer of Acton MA (US) for applied materials, inc., Frank Sinclair of Hartland ME (US) for applied materials, inc.

IPC Code(s): H01L21/66, G01B11/16, H01L21/3115, H01L21/67

CPC Code(s): H01L22/12

Abstract: disclosed systems and techniques are directed to correct an out-of-plane deformation (opd) of a substrate (e.g., wafer) by identifying, using optical inspection data, a profile of the opd of the substrate and performing a polynomial decomposition of the profile to determine polynomial coefficients characterizing elemental deformation shapes of the substrate. the techniques further include identifying, based on the polynomial coefficients, characteristics of a stress-compensation layer (scl) for the substrate and causing the scl to be deposited on the substrate. the techniques further include performing statistical simulations to identify settings for a non-uniform stress-mitigation irradiation of the scl, by sampling from one or more statistical distributions associated with previously performed stress-mitigation irradiations, and performing the non-uniform stress-mitigation irradiation of the scl using the identified settings.

20240266231. CYLINDRIC DECOMPOSITION FOR EFFICIENT MITIGATION OF SUBSTRATE DEFORMATION WITH FILM DEPOSITION AND ION IMPLANTATION_simplified_abstract_(applied materials, inc.)

Inventor(s): Wonjae Lee of Fremont CA (US) for applied materials, inc., Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., D. Jeffrey Lischer of Acton MA (US) for applied materials, inc., Frank Sinclair of Hartland ME (US) for applied materials, inc.

IPC Code(s): H01L21/66, C23C14/54, G01B9/02, G01B11/16, H01L23/00

CPC Code(s): H01L22/12

Abstract: disclosed systems and techniques are directed to correct an out-of-plane deformation (opd) of a substrate. the techniques include obtaining, using optical inspection data, an opd profile of the substrate and obtaining a polynomial representation of the opd profile to determine a plurality of polynomial coefficients characterizing respective elemental deformation shapes of the substrate. the techniques further include identifying one or more cylindric decompositions of a quadratic part of the opd profile and computing, using a selected cylindric decomposition of the one or more cylindric decompositions, one or more characteristics of a stress-compensation layer (scl) for the substrate. the techniques further include causing the scl to be deposited on the substrate and the scl to be exposed to a stress-mitigation beam.

20240266233. INFLUENCE FUNCTION-BASED MITIGATION OF SUBSTRATE DEFORMATION WITH FILM DEPOSITION AND ION IMPLANTATION_simplified_abstract_(applied materials, inc.)

Inventor(s): Wonjae Lee of Fremont CA (US) for applied materials, inc., Pradeep Kumar Subrahmanyan of San Jose CA (US) for applied materials, inc., D. Jeffrey Lischer of Acton MA (US) for applied materials, inc., Frank Sinclair of Hartland ME (US) for applied materials, inc.

IPC Code(s): H01L21/66, C23C14/48, C23C14/54, H01L21/02

CPC Code(s): H01L22/20

Abstract: disclosed systems and techniques are directed to correcting an out-of-plane (opd) deformation of a substrate by causing a stress-compensation layer (scl) to be deposited on the substrate, obtaining, using optical inspection data, a profile of the opd of the substrate. the techniques further include obtaining a dataset with a representation of an influence function for the substrate, the influence function characterizing a deformation response of the substrate caused by a point-like mechanical influence. the techniques further include performing a regression computation to determine, based at least on the profile of the opd of the substrate and the influence function, a distribution of a stress-mitigation irradiation of the scl that mitigate the opd of the substrate. the techniques further include performing, using the determined distribution of the stress-mitigation irradiation, a stress-mitigation irradiation of the scl.

20240266319. Method of Multi-layer Die Stacking with Die-to-Wafer Bonding_simplified_abstract_(applied materials, inc.)

Inventor(s): Guan Huei SEE of Singapore (SG) for applied materials, inc., Jinho AN of San Jose CA (US) for applied materials, inc., Arvind SUNDARRAJAN of Singapore (SG) for applied materials, inc.

IPC Code(s): H01L23/00, H01L21/56, H01L21/768

CPC Code(s): H01L24/80

Abstract: embodiments of methods of die stacking are provided herein. in some embodiments, a method of die stacking with die-to-wafer bonding includes: bonding a plurality of first dies to a substrate via a hybrid bonding process; performing a selective silicon (si) thinning process to reduce a thickness of the plurality of first dies that are bonded to form a plurality of thinned first dies; passivating the plurality of thinned first dies to form a plurality of passivated thinned first dies to protect the plurality of thinned first dies; filling gaps between adjacent dies of the plurality of thinned first dies with a first fill material, wherein the plurality of passivated thinned first dies and the first fill material together form a first layer; and forming a plurality of first conductive vias through the first layer to the substrate.

20240266414. MULTI-VT INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES_simplified_abstract_(applied materials, inc.)

Inventor(s): Srinivas Gandikota of Santa Clara CA (US) for applied materials, inc., Yixiong Yang of Fremont CA (US) for applied materials, inc., Tengzhou Ma of San Jose CA (US) for applied materials, inc., Tianyi Huang of Santa Clara CA (US) for applied materials, inc., Geetika Bajaj of Cupertino CA (US) for applied materials, inc., Hsin-Jung Yu of Santa Clara CA (US) for applied materials, inc., Seshadri Ganguli of Sunnyvale CA (US) for applied materials, inc.

IPC Code(s): H01L29/423, H01L21/8238, H01L27/092, H01L29/06, H01L29/49, H01L29/51, H01L29/66, H01L29/775, H01L29/786

CPC Code(s): H01L29/42392

Abstract: embodiments of the disclosure advantageously provide methods of manufacturing semiconductor devices having multi-vt capability in the scaled space between nanosheets in advanced gaa nodes. one or more embodiments provide an integration scheme to advantageously reduce the gate resistance by combining n-/p-dipole and mid-gap metal with low resistance to achieve desired work function and low-resistance metal gate. in one or more embodiments, a mid-gap metal is used to fill nanosheets and act as a liner for subsequent fill by a low resistance metal. after dipole engineering, instead of filling the gate-all-around nanosheet with traditional n or p metal, in one or more embodiments, the nanosheet is advantageously filled with a single work function mid-gap metal to achieve n and p work function. if the work function was shifted in either p-dipole or n-dipole bandedge after dipole engineering, the mid-gap materials can also shift the bandedge the opposite way.

20240268095. 4F2 DRAM Including Buried Bitline_simplified_abstract_(applied materials, inc.)

Inventor(s): Qintao Zhang of Mt Kisco NY (US) for applied materials, inc., Sipeng Gu of Clifton Park NY (US) for applied materials, inc.

IPC Code(s): H10B12/00, H01L29/66, H01L29/78

CPC Code(s): H10B12/053

Abstract: disclosed are approaches for forming 4fvertical dram devices including buried bitlines. one dram device may include a plurality of bitlines between a plurality of vertical structures extending from a substrate, and a bottom source/drain formed in each of the plurality of vertical structures in a saddle area, wherein the saddle area comprises a saddle trench formed through the plurality of vertical structures. the dram device may further include a dielectric film formed over the plurality of vertical structures in the saddle area, wherein the dielectric film is present along a portion of the plurality of bitlines and along just a first sidewall the plurality of vertical structures in the saddle area, and a fill material over the plurality of vertical structures of the saddle area, wherein the fill material directly contacts the plurality of bitlines.

20240268108. V-NAND STACKS WITH DIPOLE REGIONS_simplified_abstract_(applied materials, inc.)

Inventor(s): Yong Yang of Boston MA (US) for applied materials, inc., Jacqueline S. Wrench of San Jose CA (US) for applied materials, inc., Yixiong Yang of Fremont CA (US) for applied materials, inc., Pradeep K. Subrahmanyan of Los Gatos CA (US) for applied materials, inc., Srinivas Gandikota of Santa Clara CA (US) for applied materials, inc.

IPC Code(s): H10B41/27, G11C5/06, H01L21/8234, H10B43/27

CPC Code(s): H10B41/27

Abstract: a memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. the dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

20240268205. OLED STRUCTURE AND PROCESS BASED ON PIXEL PASSIVATION BY REMOVING OLED STACK OVER HEAT ABSORBENT STRUCTURES_simplified_abstract_(applied materials, inc.)

Inventor(s): Ji Young CHOUNG of Hwaseong-si (KR) for applied materials, inc., Chung-chia CHEN of Hsinchu City (TW) for applied materials, inc., Jungmin LEE of Santa Clara CA (US) for applied materials, inc., Yu-hsin LIN of Zhubei City (TW) for applied materials, inc., Takuji KATO of Yokohama City (JP) for applied materials, inc.

IPC Code(s): H10K59/80, H10K59/12, H10K59/122

CPC Code(s): H10K59/8794

Abstract: devices with sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (oled) display. in one example, a device includes a substrate, a plurality of pixel-defining layer (pdl) structures disposed over the substrate, each pdl structure having an upper pdl surface, and a plurality of heat absorbent structures disposed on the upper pdl surface of the plurality pdl structures. each adjacent heat absorbent structure includes a top surface and two sidewalls. adjacent heat absorbent structures define sub-pixels of the device, each sub-pixel includes an anode, an oled material disposed over the anode, a cathode disposed over the oled material, and an encapsulation layer disposed over the cathode and over a first portion of the top surface of the first heat absorbent structure and a second portion of the top surface of the second heat absorbent structure.

Applied Materials, Inc. patent applications on August 8th, 2024