Applied Materials, Inc. patent applications on August 22nd, 2024
Patent Applications by Applied Materials, Inc. on August 22nd, 2024
Applied Materials, Inc.: 17 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (6), H01L21/67 (3), H01L21/768 (3), H01L29/66 (3), H01J37/32 (3) C23C16/45553 (1), H01L21/6719 (1), H05K9/0064 (1), H01L29/0634 (1), H01L29/0619 (1)
With keywords such as: layer, material, substrate, device, include, region, fill, surface, processing, and trench in patent application abstracts.
Patent Applications by Applied Materials, Inc.
Inventor(s): Chandan Kr Barik of Singapore (SG) for applied materials, inc., Andrea Leoncini of Singapore (SG) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/18
CPC Code(s): C23C16/45553
Abstract: molybdenum(0) precursors and methods of forming molybdenum-containing films on a substrate surface are described. the molybdenum(0) precursors have a purity of greater than or equal to 90% molybdenum (mo) on a molar basis. the substrate is exposed to a molybdenum(0) precursor and a reactant to form a molybdenum-containing film having greater than or equal to 80% molybdenum (mo) on an atomic basis. in some embodiments, the molybdenum-containing film has greater than or equal to 80% molybdenum (mo) on a molar basis. the exposures can be sequential or simultaneous.
Inventor(s): CHI-MING TSAI of San Jose CA (US) for applied materials, inc., THOMAS L. LAIDIG of Richmond CA (US) for applied materials, inc., DOUGLAS VAN DEN BROEKE of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): G03F7/00
CPC Code(s): G03F7/70475
Abstract: a digital lithography system includes scan regions including a first scan region and a second scan region adjacent to the first scan region. the digital lithography system further includes exposure units located above the scan regions, a memory, and at least one processing device operatively coupled to the memory. the exposure units include a first exposure unit associated with the first scan region and a second exposure unit associated with the second scan region. the processing device is to perform operations including initiating a digital lithography process to pattern a substrate disposed on the stage in accordance with instructions, and performing exposure unit boundary smoothing with respect to the first and second exposure units during the digital lithography process.
Inventor(s): Chi-Ming TSAI of San Jose CA (US) for applied materials, inc.
IPC Code(s): G03F7/20
CPC Code(s): G03F7/70558
Abstract: embodiments of the present disclosure relate to methods, systems and apparatus for improving dose uniformity of the photolithography system. the method includes projecting a write beam from a projection unit toward a mask to form a plurality of incident lights, adjusting the projection unit to create a distribution of incidence angles corresponding to the incident lights, focusing the plurality of incident lights toward a photoresist layer disposed over a substrate with a lens, removing portions of the photoresist layer to form the device pattern, and forming structures on the substrate corresponding to the device pattern. the mask has a mask pattern corresponding to a device pattern. by focusing the plurality of incident lights towards the photoresist, a swing curve of the incident lights interfere to reduce a total swing curve of the incident lights to develop a photoresist layer with a photoresist pattern corresponding to the device pattern.
Inventor(s): Martinus Maria Berkens of Eindhoven (NL) for applied materials, inc., Bhuvaneshwari Ayyagari of Cupertino CA (US) for applied materials, inc., Simon Johannes Klaver of Weert (NL) for applied materials, inc., Vinod Reddy of San Jose CA (US) for applied materials, inc., Rene Gerardus Maria Beugels of Eindhoven (NL) for applied materials, inc., Andres Llopis Lozano of Majadahonda (ES) for applied materials, inc.
IPC Code(s): G06F30/337, G06F30/392
CPC Code(s): G06F30/337
Abstract: a method of automatically generating standard cells may include receiving a definition of a circuit for a standard cell. the definition may include one or more semiconductor devices. the method may also include identifying a plurality of slices that implement a device in the one or more semiconductor devices. each of the plurality of slices may include a partial layout for the device. the method may further include combining more than one of the plurality of slices into a combined layout to implement the device when forming the standard cell.
20240282554. MODULAR HIGH-FREQUENCY SOURCE_simplified_abstract_(applied materials, inc.)
Inventor(s): Thai Cheng Chua of Cupertino CA (US) for applied materials, inc., Christian Amormino of San Jose CA (US) for applied materials, inc., Hanh Nguyen of San Jose CA (US) for applied materials, inc., Kallol Bera of San Jose CA (US) for applied materials, inc., Philip Allan Kraus of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, H03F3/19, H03F3/21
CPC Code(s): H01J37/32201
Abstract: embodiments include a modular high-frequency emission source. in an embodiment, the modular high-frequency emission source includes a plurality of high-frequency emission modules, where each high-frequency emission module comprises and oscillator module, an amplification module, and an applicator. in an embodiment the oscillator module comprises a voltage control circuit and a voltage controlled oscillator. in an embodiment, the amplification module is coupled to the oscillator module. in an embodiment, the applicator is coupled to the amplification module. in an embodiment, each high-frequency emission module includes a different oscillator module.
Inventor(s): Lara HAWRYLCHAK of Gilroy CA (US) for applied materials, inc., Chaitanya A. PRASAD of Cupertino CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, B08B7/00, H01L21/02, H01L21/67, H01L21/687
CPC Code(s): H01J37/32724
Abstract: implementations of the present disclosure generally relate to an improved substrate support pedestal assembly. in one implementation, the substrate support pedestal assembly includes a shaft. the substrate support pedestal assembly further includes a substrate support pedestal, mechanically coupled to the shaft. the substrate support pedestal comprises substrate support plate coated on a top surface with a ceramic material.
Inventor(s): Sathiyamurthi GOVINDASAMY of Coimbatore (IN) for applied materials, inc., Harish V. PENMETHSA of Dublin CA (US) for applied materials, inc., Suresh PALANISAMY of Coimbatore (IN) for applied materials, inc., Naresh Kumar ASOKAN of Coimbatore (IN) for applied materials, inc., Karunakaran NATARAJ of Coimbatore (IN) for applied materials, inc.
IPC Code(s): H01J37/34
CPC Code(s): H01J37/3408
Abstract: apparatus and methods for improving film uniformity in a physical vapor deposition (pvd) process are provided herein. in some embodiments, a magnetron translation assembly comprises a first linear actuator assembly with a first rail which is aligned in a first direction and a first actuator that is configured to position a first mount along the first rail; a magnet assembly is mounted on the first mount, the magnet assembly constructed and arranged to be rotated about an axis perpendicular to the first rail; and a second linear actuator assembly comprising a second mount that is configured to be positioned along a second rail, which is aligned in a second direction and the first linear actuator assembly is coupled to a mounting surface of the second mount.
Inventor(s): Bin Yao of Santa Clara CA (US) for applied materials, inc., Zihui Li of Santa Clara CA (US) for applied materials, inc., Anchuan Wang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/3213, H01L29/66
CPC Code(s): H01L21/32138
Abstract: exemplary semiconductor processing methods may include providing a treatment precursor to a processing a remote plasma system of a semiconductor processing chamber. the methods may include generating plasma effluents of the treatment precursor in the remote plasma system. the methods may include flowing plasma effluents of the treatment precursor to a processing region of the semiconductor processing chamber. a substrate including alternating layers of material may be disposed within the processing region. the alternating layers of material may include a silicon-and-germanium-containing material. the methods may include contacting the substrate with the plasma effluents of the treatment precursor. the contacting may remove a residue from a surface of the silicon-and-germanium-containing material.
Inventor(s): Chaitanya Anjaneyalu Prasad of Cupertino CA (US) for applied materials, inc., Christopher Sean Olsen of Fremont CA (US) for applied materials, inc., Lara Hawrylchak of Gilroy CA (US) for applied materials, inc., Erika Gabrielle Hansen of San Jose CA (US) for applied materials, inc., Daniel C. Glover of Danville CA (US) for applied materials, inc., Naman Apurva of Patna (IN) for applied materials, inc., Tsung-Han Yang of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/02
CPC Code(s): H01L21/67115
Abstract: embodiments of methods of performing a selective oxidation process on non-metal surfaces are provided herein. in some embodiments, a method of performing a selective oxidation process on non-metal surfaces includes: forming a first mixture of a carrier gas and a liquid in a mixer having a mixing block coupled to one or more control valves with a mixing line disposed therebetween; flowing the first mixture from the mixer to a vaporizer to vaporize the first mixture outside of an rtp chamber; and delivering the vaporized first mixture to the rtp chamber via a gas delivery line to expose a substrate disposed in the rtp chamber with the vaporized first mixture to perform a selective oxidation process on the substrate at a temperature of about 500 to about 1100 degrees celsius.
Inventor(s): Rupankar CHOUDHURY of Bangalore (IN) for applied materials, inc., Sanjay G. KAMATH of Fremont CA (US) for applied materials, inc., Sridhar BACHU of Bangalore (IN) for applied materials, inc.
IPC Code(s): H01L21/67, F24F13/14, F24F13/32, H01L21/673
CPC Code(s): H01L21/6719
Abstract: an apparatus and system for minimizing particle return to the processing area of a processing chamber are disclosed herein. in one example, a particle shield for a semiconductor vacuum processing chamber includes an annular ring, a plurality of rib supports, and a plurality of louver fins. the annular ring has top surface, a bottom surface, and a plurality of cutaways. the top surface has an upper outer portion and a lower inner portion. the plurality of rib supports are disposed on and supported by the lower inner portion. the plurality of louver fins have a truncated conical shape, a bottom surface of the louver fins supported in a recess formed in a top surface of the rib supports. each of the plurality of louver fins are disposed between adjacent concentric louver fins that have an outer diameter greater than an inner diameter of the outwardly adjacent louver fin.
Inventor(s): Xi CEN of San Jose CA (US) for applied materials, inc., Kai WU of Palo Alto CA (US) for applied materials, inc., Yao XU of Santa Clara CA (US) for applied materials, inc., Yang LI of Sunnyvale CA (US) for applied materials, inc., Meng ZHU of Santa Clara CA (US) for applied materials, inc., Insu HA of San Jose CA (US) for applied materials, inc., Jianqiu GUO of San Jose CA (US) for applied materials, inc., Chao LI of Santa Clara CA (US) for applied materials, inc., Rongjun WANG of Dublin CA (US) for applied materials, inc., Xianmin TANG of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/02, H01L21/285
CPC Code(s): H01L21/76879
Abstract: a method of filling a via having a necking point includes performing a pre-clean process to remove residues from an exposed surface of a metal layer at a bottom of a via and recover inner surfaces of the via, wherein the via is formed within a dielectric layer and has a necking point protruding within the via, performing a selective deposition process to partially fill the via with metal fill material from the exposed surface of the metal layer below the necking point, performing a liner deposition process to form a liner layer on exposed inner surfaces of the via, and performing a metal fill process to fill the via with the metal fill material.
Inventor(s): Zachary J. Devereaux of Webberville MI (US) for applied materials, inc., Bhaskar Jyoti Bhuyan of Santa Clara CA (US) for applied materials, inc., Thomas Joseph Knisley of Livonia MI (US) for applied materials, inc., Zeqing Shen of San Jose CA (US) for applied materials, inc., Susmit Singha Roy of Campbell CA (US) for applied materials, inc., Mark J. Saly of Santa Clara CA (US) for applied materials, inc., Abhijit Basu Mallick of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, C23C16/04, C23C16/32, C23C16/40, C23C16/455, H01L21/02
CPC Code(s): H01L21/76897
Abstract: a method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ild) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. the at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.
Inventor(s): Zhaoxuan WANG of Sunnyvale CA (US) for applied materials, inc., Jianxin LEI of Fremont CA (US) for applied materials, inc., Wenting HOU of San Jose CA (US) for applied materials, inc., David Maxwell GAGE of San Jose CA (US) for applied materials, inc., Zihao HE of Fremont CA (US) for applied materials, inc.
IPC Code(s): H01L23/532, H01L21/02, H01L21/3205, H01L21/321, H01L21/768
CPC Code(s): H01L23/53266
Abstract: a method to produce a layered substrate includes depositing a ruthenium layer having a first average grain size on a substrate; annealing the substrate at a temperature and for a period of time sufficient to produce an annealed ruthenium layer having a second average grain size which is greater than the first average grain size; and removing a portion of the ruthenium layer by chemical mechanical planarization to form a planarized ruthenium layer, to produce the layered substrate. a layered substrate is also disclosed.
Inventor(s): Amirhasan NOURBAKHSH of Albany NY (US) for applied materials, inc., Raman GAIRE of Mechanicville NY (US) for applied materials, inc., Pei LIU of Rexford NY (US) for applied materials, inc., Tyler SHERWOOD of Fonda NY (US) for applied materials, inc., Ryan Scott SMITH of Clifton Park NY (US) for applied materials, inc., Roger QUON of Rhinebeck NY (US) for applied materials, inc., Siddarth KRISHNAN of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L29/06, H01L29/10, H01L29/66
CPC Code(s): H01L29/0619
Abstract: a super junction device with an increased voltage rating may be formed by decreasing the width of the p-type region and increasing the doping concentration, while also increasing the height of the overall device. however, instead of etching a trench in the n-type material to fill with the p-type material, a trench may be etched for both the p-type region and an adjacent n-type region. this allows the height of the overall device to be increased while maintaining a feasible aspect ratio for the trench. the p-type material may then be formed as a sidewall liner on the trench that is relatively thin compared to the remaining width of the trench. the trench may then be filled with n-type material such that the p-type region fills the space between the n-type regions without any voids or seams, while having a width that would be unattainable using traditional etch-and-fill methods for the p-type region alone.
Inventor(s): Amirhasan Nourbakhsh of Albany NY (US) for applied materials, inc., Raman Gaire of Mechanicville NY (US) for applied materials, inc., Roger Quon of Rhinebeck NY (US) for applied materials, inc., Siddarth Krishnan of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L29/06, H01L21/02, H01L21/3065, H01L29/66, H01L29/78
CPC Code(s): H01L29/0634
Abstract: a super junction device with an increased manufacturing throughput may be formed by forming narrow trenches lined with a p-type liner and rapidly filled with a passive fill material. instead of etching trenches with aspect ratio large enough to reliably fill with doped p-type material, the aspect ratio of the trench may be reduced to shrink the size of the device. this smaller trench may then be lined with a relatively thin (e.g., about 1 �m to about 2 �m) p-type liner instead of completely filling the trench with p-type material. inside the p-type liner, the trench may then be filled with a passive fill material. filling the trench with the passive fill material may be carried out in a matter of minutes at relatively high temperatures, thereby likely causing a void or seam to form within the passive fill material. however, because the passive fill material does not affect the operation of the device, this type of defect can exist in the device.
Inventor(s): Gayatri Natu of Mumbai (IN) for applied materials, inc., Geetika Bajaj of Mumbai (IN) for applied materials, inc., Prerna Goradia of Mumbai (IN) for applied materials, inc., Darshan Thakare of Thane West (IN) for applied materials, inc., David Fenwick of Los Altos Hills CA (US) for applied materials, inc., XiaoMing He of Fremont CA (US) for applied materials, inc., Sanni Seppaelae of Karlstein am Main (DE) for applied materials, inc., Jennifer Sun of Fremont CA (US) for applied materials, inc., Rajkumar Thanu of Santa Clara CA (US) for applied materials, inc., Jeff Hudgens of San Francisco CA (US) for applied materials, inc., Karuppasamy Muthukamatchy of Bangalore (IN) for applied materials, inc., Arun Dhayalan of Austin TX (US) for applied materials, inc.
IPC Code(s): H05K9/00, H01J37/20, H01J37/32, H01L21/687, H05F1/02
CPC Code(s): H05K9/0064
Abstract: a coated chamber component comprises a chamber component and a coating deposited on a surface of the chamber component, the coating comprising an electrically-dissipative material. the electrically-dissipative material is to provide a dissipative path from the coating to a ground. the coating is uniform, conformal, and has a thickness ranging from about 10 nm to about 900 nm.
20240284703. POLARIZER-FREE LED DISPLAYS_simplified_abstract_(applied materials, inc.)
Inventor(s): Chung-Chih Wu of Taipei (TW) for applied materials, inc., Po-Jui Chen of Taipei (TW) for applied materials, inc., Hoang Yan Lin of Taipei (TW) for applied materials, inc., Guo-Dong Su of Taipei (TW) for applied materials, inc., Wei-Kai Lee of Taipei (TW) for applied materials, inc., Chi-Jui Chang of Taichung City (TW) for applied materials, inc., Wan-Yu Lin of Taipei City (TW) for applied materials, inc., Byung Sung Kwak of Mountain View CA (US) for applied materials, inc., Robert Jan Visser of Menlo Park CA (US) for applied materials, inc.
IPC Code(s): H10K50/858, H10K50/86, H10K71/00
CPC Code(s): H10K50/858
Abstract: exemplary subpixel structures include a directional light-emitting diode structure characterized by a full-width-half-maximum (fwhm) of emitted light having a divergence angle of less than or about 10�. the subpixel structure further includes a lens positioned a first distance from the light-emitting diode structure, where the lens is shaped to focus the emitted light from the light-emitting diode structure. the subpixel structure still further includes a patterned light absorption barrier positioned a second distance from the lens. the patterned light absorption barrier defines an opening in the barrier, and the focal point of the light focused by the lens is positioned within the opening. the subpixels structures may be incorporated into a pixel structure, and pixel structures may be incorporated into a display that is free of a polarizer layer.
Applied Materials, Inc. patent applications on August 22nd, 2024
- Applied Materials, Inc.
- C23C16/455
- C23C16/18
- CPC C23C16/45553
- Applied materials, inc.
- G03F7/00
- CPC G03F7/70475
- G03F7/20
- CPC G03F7/70558
- G06F30/337
- G06F30/392
- CPC G06F30/337
- H01J37/32
- H03F3/19
- H03F3/21
- CPC H01J37/32201
- B08B7/00
- H01L21/02
- H01L21/67
- H01L21/687
- CPC H01J37/32724
- H01J37/34
- CPC H01J37/3408
- H01L21/3213
- H01L29/66
- CPC H01L21/32138
- CPC H01L21/67115
- F24F13/14
- F24F13/32
- H01L21/673
- CPC H01L21/6719
- H01L21/768
- H01L21/285
- CPC H01L21/76879
- C23C16/04
- C23C16/32
- C23C16/40
- CPC H01L21/76897
- H01L23/532
- H01L21/3205
- H01L21/321
- CPC H01L23/53266
- H01L29/06
- H01L29/10
- CPC H01L29/0619
- H01L21/3065
- H01L29/78
- CPC H01L29/0634
- H05K9/00
- H01J37/20
- H05F1/02
- CPC H05K9/0064
- H10K50/858
- H10K50/86
- H10K71/00
- CPC H10K50/858
