Applied Materials, Inc. patent applications on August 1st, 2024
Patent Applications by Applied Materials, Inc. on August 1st, 2024
Applied Materials, Inc.: 27 patent applications
Applied Materials, Inc. has applied for patents in the areas of H01L21/02 (6), C23C16/455 (5), H01L21/687 (5), H01L21/67 (5), C23C16/458 (4) C30B25/14 (2), B24B37/32 (1), H01L21/0254 (1), H01L29/105 (1), H01L21/76844 (1)
With keywords such as: substrate, processing, layer, chamber, surface, gas, process, embodiments, lithium, and support in patent application abstracts.
Patent Applications by Applied Materials, Inc.
20240253179. POLISHING HEAD WITH LOCAL WAFER PRESSURE_simplified_abstract_(applied materials, inc.)
Inventor(s): Andrew NAGENGAST of Sunnyvale CA (US) for applied materials, inc., Steven M. ZUNIGA of Soquel CA (US) for applied materials, inc., Jay GURUSAMY of Santa Clara CA (US) for applied materials, inc., Charles C. GARRETSON of Sunnyvale CA (US) for applied materials, inc., Vladimir GALBURT of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): B24B37/32, B24B37/005, B24B37/04
CPC Code(s): B24B37/32
Abstract: a polishing system includes a carriage arm having an actuator disposed on a lower surface thereof. the actuator includes a piston and a roller coupled to a distal end of the piston. the polishing system includes a polishing pad and a substrate carrier suspended from the carriage arm and configured to apply a pressure between a substrate and the polishing pad. the substrate carrier includes a housing, a retaining ring, and a membrane. the substrate carrier includes an upper load ring disposed in the housing. the roller of the actuator is configured to contact the upper load ring during relative rotation between the substrate carrier and the carriage arm. the actuator is configured to apply a load to a portion of the upper load ring thereby altering the pressure applied between the substrate and the polishing pad.
Inventor(s): Priscilla Michelle Diep LAROSA of San Jose CA (US) for applied materials, inc., Haosheng WU of Fremont CA (US) for applied materials, inc., Jimin ZHANG of San Jose CA (US) for applied materials, inc., Taketo SEKINE of Cuppertino CA (US) for applied materials, inc., Chen-Wei CHANG of San Jose CA (US) for applied materials, inc., Jianshe TANG of San Jose CA (US) for applied materials, inc., Brian J. BROWN of Palo Alto CA (US) for applied materials, inc., Wei LU of Fremont CA (US) for applied materials, inc., Ekaterina A. MIKHAYLICHENKO of San Jose CA (US) for applied materials, inc., Huanbo ZHANG of San Jose CA (US) for applied materials, inc., Jeonghoon OH of Saratoga CA (US) for applied materials, inc., Eric LAU of Santa Clara CA (US) for applied materials, inc., Andrew NAGENGAST of Sunnyvale CA (US) for applied materials, inc., Takashi FUJIKAWA of Sunnyvale CA (US) for applied materials, inc., Thomas H. OSTERHELD of Mountain View CA (US) for applied materials, inc., Steven M. ZUNIGA of Soquel CA (US) for applied materials, inc.
IPC Code(s): B24B57/02, B24B37/015, B24B53/017
CPC Code(s): B24B57/02
Abstract: a method and apparatus for dispensing polishing fluids and onto a polishing pad within a chemical mechanical polishing (cmp) system are disclosed herein. in particular, embodiments herein relate to a cmp system with a first fluid delivery arm and a second fluid delivery arm disposed over the polishing pad to dispense fluid, such as a polishing fluid or water, and/or provide a vacuum pressure. the second fluid delivery arm is configured to dispense a fluid or vacuum pressure onto the polishing pad to effect the polishing rate at the edge of the substrate.
20240253968. LIQUID LITHIUM SUPPLY AND REGULATION_simplified_abstract_(applied materials, inc.)
Inventor(s): Jean DELMAS of Santa Clara CA (US) for applied materials, inc., Bernard FREY of Livermore CA (US) for applied materials, inc.
IPC Code(s): B67D7/02, B65D88/74, B67D7/16, B67D7/32, B67D7/36, B67D7/62, B67D7/76, B67D7/78, B67D7/82, H05B1/02
CPC Code(s): B67D7/02
Abstract: methods and systems for the production and delivery of lithium metal of high purity are provided herein. in one or more embodiments, method for flowing liquid lithium to a processing chamber is provided and includes flowing liquid lithium from a lithium refill container to a liquid lithium delivery module, where the liquid lithium delivery module is fluidly coupled to the lithium refill container, and flowing the liquid lithium from the liquid lithium delivery module to the processing chamber. the liquid lithium delivery module contains a lithium storage region operable to store liquid lithium and containing a fluid supply line fluidly coupling an outlet port of a liquid lithium storage tank, and a flow meter positioned downstream from the lithium storage region along the fluid supply line and operable to monitor the flow of the liquid lithium through the fluid supply line.
Inventor(s): Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Manjunath SUBBANNA of Bangalore (IN) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/458, C23C16/46
CPC Code(s): C23C16/45502
Abstract: embodiments of the present disclosure relate to plate assemblies, process kits, processing chambers, and related components and methods for semiconductor manufacturing. in one implementation, a plate assembly for disposition in a processing chamber includes an inner section that includes an opaque material. the inner section has an outer diameter. the plate assembly includes a first outer section that is arcuate in shape and includes the opaque material. the first outer section includes a first inner shoulder, and a first inner lip extending inwardly relative to the first inner shoulder.
Inventor(s): Raja Murali DHAMODHARAN of Madurai (IN) for applied materials, inc., Kalaivanan MOHANADASS of Sunnyvale CA (US) for applied materials, inc., Aniketnitin PATIL of San Jose CA (US) for applied materials, inc., Martin Jeffrey SALINAS of San Jose CA (US) for applied materials, inc., Shu-Kwan LAU of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): C23C16/455, C23C16/458, C30B25/12, C30B25/14
CPC Code(s): C23C16/45563
Abstract: embodiments of the present disclosure relate to injectors, liners, process kits, processing chambers, and related methods for gas flow in batch processing operations. in one or more embodiments, the liners facilitate gas flow uniformity in batch processing. in one or more embodiments, a liner includes a plurality of inlet openings on an inlet side, the plurality of inlet openings extending into an outer face of the liner. the plurality of inlet openings include a plurality of first inlet openings that include a first row extending into a first side face, and a second row extending into a second side face. the plurality of inlet openings include a plurality of second inlet openings extending between an inner face and the outer face. the liner includes one or more outlet openings on an outlet side. the outlet side opposes the inlet side. the one or more outlet openings extend into the inner face.
Inventor(s): Jing Xu of Kalispell MT (US) for applied materials, inc., John Klocke of Kalispell MT (US) for applied materials, inc.
IPC Code(s): C25D3/38, C25D5/02, C25D5/10, C25D5/34, C25D7/12, H01L21/02, H01L21/768
CPC Code(s): C25D3/38
Abstract: a semiconductor wafer, including a substrate, at least one via formed in the substrate, and copper electroplating inside the at least one via, where the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper. further, a method of making a semiconductor wafer, the method comprising providing a substrate; etching the substrate to form at least one via; and depositing copper electroplating inside the at least one via, wherein the copper electroplating comprises a first layer of nanotwin copper, and a second layer of bulk copper.
Inventor(s): Amir H. TAVAKOLI of San Jose CA (US) for applied materials, inc., Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc., Shawn Thanhson LE of San Jose CA (US) for applied materials, inc.
IPC Code(s): C30B25/10, C30B25/08
CPC Code(s): C30B25/10
Abstract: an epitaxial growth processing chamber has a component that has a macrocell support structure. the macrocell support structure has interconnecting physical supports that define fluidly-connected pores. a component configured for use in an epitaxial growth processing chamber has a macrocell support structure with interconnecting physical supports defining fluidly-connected pores. the component may be one or more of a lower liner, an upper liner, a baseplate, an exhaust cap, an injection ring, and an injection cap. the interconnecting physical supports may comprise a material such as a metal, a ceramic or glass material, a polymeric material, and combinations thereof. the component may have a free-standing configuration, a plate-supported configuration, a sandwich configuration, a surface sealed configuration, and a solid polymer-filled configuration.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Ala MORADIAN of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): C30B25/14, C23C16/455, C23C16/46, C30B25/10, H01L21/687
CPC Code(s): C30B25/14
Abstract: the present disclosure relates to methods and devices for processing substrates, suitable for use in semiconductor manufacturing. the method includes heating a substrate positioned on a substrate support. the method includes moving an isolation plate adjust one or more of: a height of the isolation plate, or an angle of the isolation plate such that the isolation plate moves to a non-parallel orientation relative to the substrate. the method includes flowing one or more process gases over the substrate to deposit a material on the substrate, the flowing of the one or more process gases over the substrate including guiding the one or more process gases through one or more flow paths defined at least in part by a space between the isolation plate and the substrate.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Tao SHENG of Santa Clara CA (US) for applied materials, inc., Errol Antonio C. SANCHEZ of Tracy CA (US) for applied materials, inc., Michael R. RICE of Pleasanton CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Ashur J. ATANOS of San Jose CA (US) for applied materials, inc.
IPC Code(s): C30B25/14, C23C16/44, C23C16/455, C23C16/46, C30B25/10
CPC Code(s): C30B25/14
Abstract: a method and apparatus for processing substrates suitable for use in semiconductor manufacturing. the method includes heating a substrate positioned on a substrate support. the method includes flowing a purge gas over an isolation plate disposed above the substrate, the flowing the purge gas including diverting a portion of the purge gas below the isolation plate through a plurality of perforations in the isolation plate. the method includes flowing one or more process gases over the substrate to deposit a material on the substrate, the flowing of the one or more process gases over the substrate comprising guiding the one or more process gases through one or more flow paths defined at least in part by a space between the isolation plate and the substrate.
Inventor(s): Eric Jay Simmons of Ballston Spa NY (US) for applied materials, inc., Qintao Zhang of Mt Kisco NY (US) for applied materials, inc., Wei Zou of Lexington MA (US) for applied materials, inc., Andrew Michael Waite of Beverly MA (US) for applied materials, inc., Jared Forrest Traynor of San Jose CA (US) for applied materials, inc., Miguel Sam Fung of Cupertino CA (US) for applied materials, inc., Vincent V. Granuzzo of Albany NY (US) for applied materials, inc., David J. Lee of Poughkeepsie NY (US) for applied materials, inc.
IPC Code(s): G02B6/134, H01L27/144
CPC Code(s): G02B6/1347
Abstract: disclosed herein are approaches for forming a uniform film with reduced surface roughness for photonic applications. one method includes providing a workpiece including a contact etch stop layer (cesl) over a device layer, patterning the cesl to expose an upper surface of the device layer in a waveguide target area, and patterning a waveguide from a dielectric film formed over the waveguide target area. the method may further include directing ions into an upper surface of the waveguide using a high-temperature ion implant to decrease a surface roughness of the upper surface of the waveguide.
Inventor(s): Michael Andrew STEARNS of San Jose CA (US) for applied materials, inc., Kartik RAMASWAMY of San Jose CA (US) for applied materials, inc., Carlaton WONG of Sunnyvale CA (US) for applied materials, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/3211
Abstract: embodiments of the present disclosure include an apparatus and methods for the plasma processing of a substrate. some embodiments are directed to a plasma processing chamber. the plasma processing chamber generally includes a planar coil region comprising a plurality of planar coils, a first power supply circuit coupled to at least two of the plurality of planar coils, a concentric coil region at least partially surrounding the planar coil region, and a second power supply circuit coupled to at least two of a plurality of concentric coils. the first power supply circuit may be configured to bias the at least two of the plurality of planar coils to affect a plasma in a center region of the plasma processing chamber, and the second power supply circuit may be configured to bias the at least two of the plurality of concentric coils to affect the plasma in an outer region.
Inventor(s): Wendell Glenn BOYD, JR. of Morgan Hill CA (US) for applied materials, inc., Govinda RAJ of Santa Clara CA (US) for applied materials, inc., Matthew James BUSCHE of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01J37/32, C23C16/458, G01D5/26, G01D11/24, G01L11/02, H01L21/683
CPC Code(s): H01J37/3244
Abstract: embodiments disclosed herein include a substrate support having a sensor assembly, and processing chamber having the same. in one embodiment, a substrate support has a puck. the puck has a workpiece support surface and a gas hole exiting the workpiece support surface. a sensor assembly is disposed in the gas hole and configured to detect a metric indicative of a deflection of a workpiece disposed on the workpiece support surface, wherein the sensor assembly is configured to allow gas to flow past the sensor assembly when positioned in the gas hole.
20240258076. SPRAY-COATED ELECTROSTATIC CHUCK DESIGN_simplified_abstract_(applied materials, inc.)
Inventor(s): Tuck Foong KOH of Singapore (RS) for applied materials, inc., Sarath BABU of Singapore (RS) for applied materials, inc., Yuichi WADA of Chiba (JP) for applied materials, inc.
IPC Code(s): H01J37/32, H01L21/683
CPC Code(s): H01J37/32477
Abstract: embodiments of the disclosure include a substrate support including a metal body with a substrate face, a plurality of lift pin holes formed in the body, and a dielectric coating disposed on the substrate face of the body. each of the plurality lift pin holes includes a through hole and a chamfer face configured to mate with a lift pin sleeve. the dielectric coating includes a substrate supporting surface, a thickness, and a pattern disposed in the substrate supporting surface.
Inventor(s): Aniketnitin PATIL of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, B08B5/00, H01L21/67
CPC Code(s): H01L21/0209
Abstract: a method and apparatus for processing substrates applicable for use in semiconductor manufacturing. the method includes rotating a first shaft having a first perforation where at least a part of the first shaft is disposed within a second shaft. the method further includes flowing a gas through a piping, where the piping is coupled to a second perforation in the second shaft. the method also includes flowing the gas through the second perforation and the first perforation into an interior of the first shaft. the method further includes flowing the gas from the interior of the first shaft to an underside of a substrate disposed within a processing chamber.
Inventor(s): Jiajie Cen of San Jose CA (US) for applied materials, inc., Ge Qu of Sunnyvale CA (US) for applied materials, inc., Shinjae Hwang of Santa Clara CA (US) for applied materials, inc., Zheng Ju of Sunnyvale CA (US) for applied materials, inc., Yang Zhou of Milpitas CA (US) for applied materials, inc., Zhiyuan Wu of San Jose CA (US) for applied materials, inc., Feng Chen of San Jose CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L21/768
CPC Code(s): H01L21/02274
Abstract: embodiments of the disclosure relate to methods for forming electrical interconnects. additional embodiments provide methods of forming and treating barrier and liner layers to improve film and material properties. in some embodiments, the resulting composite layers provide improved resistivity, decrease void formation and improve device reliability.
Inventor(s): Michel Khoury of Mountain View CA (US) for applied materials, inc.
IPC Code(s): H01L21/02, H01L29/20
CPC Code(s): H01L21/0254
Abstract: the present technology includes semiconductor structures. structures include a silicon-containing substrate, a layer of metal nitride overlying the silicon-containing substrate, a structure overlying the layer of the metal nitride, and an oxygen rich layer disposed between the layer of the metal nitride and the structure. the structure is formed from a material that includes a gallium-containing material, and aluminum nitride material, or a combination thereof, where at least about 90 wt. % of the material exhibits a metal-polarity.
Inventor(s): Xi CEN of San Jose CA (US) for applied materials, inc., Kai WU of Palo Alto CA (US) for applied materials, inc., Min-Han LEE of San Jose CA (US) for applied materials, inc., Yang LI of Sunnyvale CA (US) for applied materials, inc., Cheng CHENG of San Jose CA (US) for applied materials, inc., Zhixiu LIANG of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/285, C23C16/02, C23C16/14, C23C16/34
CPC Code(s): H01L21/28568
Abstract: a method of forming a structure on a substrate includes forming an adhesion layer on a substrate. the method further includes forming a tungsten containing layer in-situ with the adhesion layer. the tungsten containing layer is formed by a one-time soak process including soaking the substrate once, and only once, in a first gas, purging the first gas, and soaking the substrate once, and only once, in a second gas. the method further includes removing the tungsten containing layer from the adhesion layer.
Inventor(s): Baiwei Wang of Santa Clara CA (US) for applied materials, inc., Wanxing Xu of Sunnyvale CA (US) for applied materials, inc., Lisa J. Enman of Sunnyvale CA (US) for applied materials, inc., Aaron Dangerfield of Fremont CA (US) for applied materials, inc., Rohan Puligoru Reddy of San Jose CA (US) for applied materials, inc., Xiaolin C. Chen of San Ramon CA (US) for applied materials, inc., Mikhail Korolik of San Jose CA (US) for applied materials, inc., Bhaskar Jyoti Bhuyan of San Jose CA (US) for applied materials, inc., Zhenjiang Cui of San Jose CA (US) for applied materials, inc., Anchuan Wang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/311, H01L21/02
CPC Code(s): H01L21/31122
Abstract: exemplary semiconductor processing methods may include flowing an etchant precursor into a processing region of a semiconductor processing chamber. a substrate may be housed within the processing region. the substrate may define an exposed region of a titanium-containing material. the methods may include contacting the substrate with the etchant precursor. the methods may include removing at least a portion of the titanium-containing material.
Inventor(s): Kirankumar Neelasandra SAVANDAIAH of Bangalore (IN) for applied materials, inc., Srinivasa Rao YEDLA of Bangalore (IN) for applied materials, inc., Thomas BREZOCZKY of Los Gatos CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, C23C14/35, H01L21/677, H01L21/687
CPC Code(s): H01L21/67184
Abstract: embodiments disclosed herein include a substrate processing module and a method of moving a workpiece. the substrate processing module includes a shutter stack and two process stations. the shutter stack is disposed between the process stations. the method of moving a workpiece includes moving a supporting portion from a first location to a shutter stack in a first direction, retrieving the workpiece from the shutter stack, and moving the supporting portion to a second location. the transfer chamber assembly and method allows for moving workpieces to and from the shutter stack to the two process stations. a central transfer robot of the substrate processing module is configured to grip both substrates and shutter discs, allowing for one robot when typically two robots would be required.
Inventor(s): Nir Merry of Mountain View CA (US) for applied materials, inc., Schubert S. Chu of San Francisco CA (US) for applied materials, inc., Sushant S. Koshti of Sunnyvale CA (US) for applied materials, inc., Michael C. Kuchar of Georgetown TX (US) for applied materials, inc., Nyi Oo Myo of San Jose CA (US) for applied materials, inc., Songjae Lee of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/687
CPC Code(s): H01L21/67196
Abstract: a substrate processing system includes a factory interface, a transfer chamber of heptagonal shape and including four first facets and three second facets, each having a width that is narrower than that of each of the four first facets. a processing chamber is attached to one of the four first facets. a first auxiliary chamber attached to a first of the three second facets and is smaller than the first processing chamber. a load lock is attached to a second of the three second facets and to the factory interface. a second auxiliary chamber is attached to a third of the three second facets. the load lock is attached to the transfer chamber between the first and second auxiliary chambers. a robot is attached to a bottom of the transfer chamber and adapted to transfer substrates to/from the first processing chamber, the first auxiliary chamber, and the load lock.
Inventor(s): Paul Zachary Wirth of Kalispell MT (US) for applied materials, inc., Kiyki-Shiy Shang of Mountain House CA (US) for applied materials, inc., Mikhail Taraboukhine of Pleasanton CA (US) for applied materials, inc.
IPC Code(s): H01L21/67
CPC Code(s): H01L21/67248
Abstract: a direct current (dc) power is supplied to a heating element embedded into a substrate support assembly (ssa). a voltage across the heating element and a current through the heating element is measured as the dc power is supplied to the heating element. a resistance of the heating element is determined based on the measured voltage and current. a temperature measurement for the heating element and/or a zone including the heating element is obtained based on signal(s) of a temperature sensor. a temperature model is updated based on the determined resistance and the obtained temperature measurement. the heating element embedded in the ssa and/or an additional heating element embedded in the ssa or in another ssa is controlled based on the updated temperature model during a substrate process.
Inventor(s): Zhepeng CONG of San Jose CA (US) for applied materials, inc., Tao SHENG of Santa Clara CA (US) for applied materials, inc., Nimrod SMITH of Cupertino CA (US) for applied materials, inc., Khokan C. PAUL of Cupertino CA (US) for applied materials, inc., Vinh N. TRAN of San Jose CA (US) for applied materials, inc., Awse MA'AYA of Santa Clara CA (US) for applied materials, inc.
IPC Code(s): H01L21/67, H01L21/677, H01L21/68, H01L21/687
CPC Code(s): H01L21/67259
Abstract: an apparatus, method, and system for calibrating substrate positioning and placement on a substrate support in a process chamber via imaging. in an embodiment, a calibrating substrate is provided. the calibrating substrate generally includes a top surface having a plurality of first marking features and a at least one edge marking feature configured to be detectable relative to the remaining portions of the top surface of the body by an imaging apparatus.
Inventor(s): Joseph Yudovsky of Campbell CA (US) for applied materials, inc., Kaushal Gangakhedkar of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/683, C23C16/455, C23C16/458, C23C16/46, C23C16/50, H01L21/687
CPC Code(s): H01L21/6838
Abstract: described are apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. the wafer is subjected to a pressure differential between the top surface and bottom surface so that sufficient force prevents the wafer from moving during processing, the pressure differential generated by applying a decreased pressure to the back side of the wafer.
Inventor(s): Yong Jin Kim of Albany CA (US) for applied materials, inc., Carmen Leal Cervantes of Mountain View CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc., Xingye Wang of Gilbert AZ (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L23/532
CPC Code(s): H01L21/76831
Abstract: methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. a self-assembled monolayer (sam) is formed on the bottom of the gap which resists degradation when exposed to the ambient atmosphere. a barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. the sam is removed after selectively depositing the barrier layer on the sidewalls.
Inventor(s): Jiajie Cen of San Jose CA (US) for applied materials, inc., Carmen Leal Cervantes of Mountain View CA (US) for applied materials, inc., Yong Jin Kim of Albany CA (US) for applied materials, inc., Kevin Kashefi of San Ramon CA (US) for applied materials, inc., Xiaodong Wang of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L21/768, H01L21/02
CPC Code(s): H01L21/76844
Abstract: methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. a pre-clean process is performed before a self-assembled monolayer (sam) is formed on the bottom of the gap. a barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. the sam is removed after selectively depositing the barrier layer on the sidewalls.
Inventor(s): Ashish Pal of San Ramon CA (US) for applied materials, inc., Pratik B. Vyas of Fremont CA (US) for applied materials, inc., El Mehdi Bazizi of San Jose CA (US) for applied materials, inc., Stephen Weeks of Morrisville VT (US) for applied materials, inc., Ludovico Megalini of Mountain View CA (US) for applied materials, inc., Siddarth Krishnan of San Jose CA (US) for applied materials, inc.
IPC Code(s): H01L29/10, H01L21/04, H01L29/16, H01L29/66
CPC Code(s): H01L29/105
Abstract: a silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. a counter-doped region may be formed at the top of the channel directly underneath the gate oxide. instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm. the transistor may also include pocket regions on one or both sides of the channel. the pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. these improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.
Inventor(s): Mitsutoshi FUKADA of Tokyo (JP) for applied materials, inc.
IPC Code(s): H02N13/00, B23Q3/15
CPC Code(s): H02N13/00
Abstract: embodiments of substrate supports for use in process chambers are provided herein. in some embodiments, a substrate support includes: an electrostatic chuck (esc) having an upper surface and a plurality of mesas extending upward from the upper surface and a plurality of trenches extending downward from the upper surface and into the esc, wherein the esc includes a plurality of backside gas openings extending through the esc and terminating within at least some of the plurality of trenches; and one or more chucking electrodes disposed in the esc.
Applied Materials, Inc. patent applications on August 1st, 2024
- Applied Materials, Inc.
- B24B37/32
- B24B37/005
- B24B37/04
- CPC B24B37/32
- Applied materials, inc.
- B24B57/02
- B24B37/015
- B24B53/017
- CPC B24B57/02
- B67D7/02
- B65D88/74
- B67D7/16
- B67D7/32
- B67D7/36
- B67D7/62
- B67D7/76
- B67D7/78
- B67D7/82
- H05B1/02
- CPC B67D7/02
- C23C16/455
- C23C16/458
- C23C16/46
- CPC C23C16/45502
- C30B25/12
- C30B25/14
- CPC C23C16/45563
- C25D3/38
- C25D5/02
- C25D5/10
- C25D5/34
- C25D7/12
- H01L21/02
- H01L21/768
- CPC C25D3/38
- C30B25/10
- C30B25/08
- CPC C30B25/10
- H01L21/687
- CPC C30B25/14
- C23C16/44
- G02B6/134
- H01L27/144
- CPC G02B6/1347
- H01J37/32
- CPC H01J37/3211
- G01D5/26
- G01D11/24
- G01L11/02
- H01L21/683
- CPC H01J37/3244
- CPC H01J37/32477
- B08B5/00
- H01L21/67
- CPC H01L21/0209
- CPC H01L21/02274
- H01L29/20
- CPC H01L21/0254
- H01L21/285
- C23C16/02
- C23C16/14
- C23C16/34
- CPC H01L21/28568
- H01L21/311
- CPC H01L21/31122
- C23C14/35
- H01L21/677
- CPC H01L21/67184
- CPC H01L21/67196
- CPC H01L21/67248
- H01L21/68
- CPC H01L21/67259
- C23C16/50
- CPC H01L21/6838
- H01L23/532
- CPC H01L21/76831
- CPC H01L21/76844
- H01L29/10
- H01L21/04
- H01L29/16
- H01L29/66
- CPC H01L29/105
- H02N13/00
- B23Q3/15
- CPC H02N13/00
