Apple inc. (20240305303). Clock Frequency Limiter simplified abstract
Contents
Clock Frequency Limiter
Organization Name
Inventor(s)
Jose A. Tierno of Menlo Park CA (US)
Ajay M. Rao of San Jose CA (US)
Clock Frequency Limiter - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240305303 titled 'Clock Frequency Limiter
Simplified Explanation: The patent application describes a receiver circuit that controls the frequency of a clock signal in a computer system. The circuit ensures the clock signal does not exceed a certain threshold frequency by adjusting it accordingly.
- Front-end circuit generates an equalized signal.
- Clock generator circuit creates a clock signal using samples of the equalized signal.
- Measurement circuit monitors the clock signal frequency and activates an indication signal if it exceeds a threshold.
- Clock generator circuit adjusts the frequency of the clock signal in response to the indication signal.
Key Features and Innovation:
- Receiver circuit for controlling clock signal frequency.
- Front-end circuit for equalizing the signal.
- Clock generator circuit using samples of the equalized signal.
- Measurement circuit to monitor and adjust clock signal frequency.
Potential Applications:
- Computer systems.
- Electronic devices requiring precise clock signals.
Problems Solved:
- Preventing clock signal frequency from exceeding a threshold.
- Ensuring stable and accurate clock signal for system operation.
Benefits:
- Improved system performance.
- Prevents errors due to high clock signal frequency.
Commercial Applications: Clock signal control technology for computer hardware manufacturers.
Prior Art: Prior art related to clock signal frequency control circuits in computer systems.
Frequently Updated Research: Ongoing research on clock signal optimization and frequency control in computer systems.
Questions about Clock Signal Frequency Control: 1. How does the receiver circuit ensure the clock signal frequency stays within the desired range? 2. What are the potential implications of inaccurate clock signal frequency in a computer system?
Original Abstract Submitted
a receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. an embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. the measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. in response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.
