Apple inc. (20240273024). Scalable Cache Coherency Protocol simplified abstract

Scalable Cache Coherency Protocol

Organization Name

apple inc.

Inventor(s)

James Vash of San Ramon CA (US)

Gaurav Garg of San Jose CA (US)

Brian P. Lilly of San Francisco CA (US)

Ramesh B. Gunna of San Jose CA (US)

Steven R. Hutsell of San Jose CA (US)

Lital Levy-rubin of Tel Aviv (IL)

Per H. Hammarlund of Sunnyvale CA (US)

Harshavardhan Kaushikkar of Santa Clara CA (US)

Scalable Cache Coherency Protocol - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240273024 titled 'Scalable Cache Coherency Protocol

The abstract describes a scalable cache coherency protocol for systems with multiple coherent agents connected to memory controllers. The memory controller may use a precise directory for cache blocks, allowing multiple outstanding requests and providing expected cache states for snoops and completions to prevent race conditions.

• Memory controllers implement a precise directory for cache blocks
• Multiple requests to a cache block can be outstanding
• Snoops and completions include expected cache states to detect race conditions
• Cache states may include primary shared and secondary shared states
• Support for two types of snoops: snoop forward and snoop back

Potential Applications: - High-performance computing systems - Data centers - Cloud computing environments

Problems Solved: - Race conditions in cache coherency - Efficient handling of multiple outstanding requests - Scalability in systems with multiple coherent agents

Benefits: - Improved system performance - Enhanced cache coherency - Scalability for large-scale systems

Commercial Applications: Title: Scalable Cache Coherency Protocol for High-Performance Computing Systems This technology can be utilized in high-performance computing systems, data centers, and cloud computing environments to enhance cache coherency and improve system performance. It offers scalability for large-scale systems, making it ideal for applications requiring efficient handling of multiple outstanding requests.

Questions about Scalable Cache Coherency Protocol: 1. How does the protocol prevent race conditions in cache coherency? 2. What are the key benefits of using a precise directory for cache blocks in memory controllers?

Original Abstract Submitted

a scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. the memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. in an embodiment, the cache states may include a primary shared and a secondary shared state. the primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. in an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.