Apple inc. (20240192761). High-Speed Multi-Standard Sampler Circuit simplified abstract

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High-Speed Multi-Standard Sampler Circuit

Organization Name

apple inc.

Inventor(s)

Yudong Zhang of San Diego CA (US)

Ming-Shuan Chen of Santa Clara CA (US)

Chen-Yuan Wen of San Francisco CA (US)

Sanjeev K. Maheshwari of Fremont CA (US)

High-Speed Multi-Standard Sampler Circuit - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240192761 titled 'High-Speed Multi-Standard Sampler Circuit

The abstract describes a sampler circuit for a serial communication bus, comprising an amplifier circuit, an isolation circuit, and a latch circuit. The circuit amplifies voltage differences between input signals, integrates the voltage difference, and generates full-rail signals based on the voltage difference.

  • Amplifier circuit amplifies voltage difference between input signals
  • Isolation circuit isolates the amplifier circuit from the latch circuit
  • Latch circuit increases voltage difference on output nodes
  • Integration phase increases voltage difference on output nodes
  • Regeneration phase generates full-rail signals based on voltage difference

Potential Applications: - Industrial automation - Data acquisition systems - Communication equipment

Problems Solved: - Efficient signal sampling on a serial communication bus - Isolation of amplifier circuit from latch circuit - Generation of full-rail signals based on voltage difference

Benefits: - Improved signal processing accuracy - Enhanced data transmission reliability - Simplified circuit design

Commercial Applications: Title: "Advanced Sampler Circuit for Serial Communication Bus" This technology can be utilized in various industries such as telecommunications, automotive, and aerospace for signal processing and data acquisition applications.

Questions about Sampler Circuit for Serial Communication Bus: 1. How does the isolation circuit contribute to the functionality of the sampler circuit? 2. What are the key advantages of using a latch circuit in this context?


Original Abstract Submitted

a sampler circuit for use with a serial communication bus includes an amplifier circuit, an isolation circuit, and a latch circuit. during a first phase, the amplifier circuit amplifies a voltage difference between a first input signal and a second input signal received via the communication bus to generate a voltage difference on output nodes of the latch circuit. during an integration phase, the latch circuit increases the voltage difference on the output nodes. during a regeneration phase, the isolation circuit isolates the amplifier circuit from the latch circuit, which generates full-rail signals based on a voltage difference between the output nodes.