ADVANCED MICRO DEVICES, INC. patent applications on April 4th, 2024
Patent Applications by ADVANCED MICRO DEVICES, INC. on April 4th, 2024
ADVANCED MICRO DEVICES, INC.: 52 patent applications
ADVANCED MICRO DEVICES, INC. has applied for patents in the areas of G06F1/20 (11), G06F12/0862 (6), G06F3/06 (5), G06F12/0811 (5), G06F9/48 (5)
With keywords such as: memory, processing, data, cache, unit, configured, local, device, heat, and processor in patent application abstracts.
Patent Applications by ADVANCED MICRO DEVICES, INC.
Inventor(s): Jeffrey G. Cheng of Markham (CA) for advanced micro devices, inc., Yuping Shen of Orlando FL (US) for advanced micro devices, inc., Mikhail Mironov of Markham (CA) for advanced micro devices, inc., Min Zhang of Markham (CA) for advanced micro devices, inc.
IPC Code(s): A63F13/355, A63F13/358, H04N19/132
Abstract: a remote display synchronization technique preserves the presence of a local display device for a remotely-rendered video stream. a server and a client device cooperate to dynamically determine a target frame rate for a stream of rendered frames suitable for the current capacities of the server and the client device and networking conditions. the server generates from this target frame rate a synchronization signal that serves as timing control for the rendering process. the client device may provide feedback to instigate a change in the target frame rate, and thus a corresponding change in the synchronization signal. in this approach, the rendering frame rate and the encoding frequency may be “synchronized” in a manner consistent with the capacities of the server, the network, and the client device, resulting in generation, encoding, transmission, decoding, and presentation of a stream of frames that mitigates missed encoding of frames while providing acceptable latency.
Inventor(s): CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc., ROBERT EDWARD RADKE of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): G05B19/416, G06F1/20
Abstract: an apparatus for component cooling includes a first heat transfer element configured to be thermally coupled to a heat-generating component and a second heat transfer element configured to be thermally coupled to the heat-generating component. a manifold is configured to receive a single fluid flow of a heat transfer medium and split the single fluid flow into a first split fluid flow provided to the first heat transfer element and a second split fluid flow provided to the second heat transfer element.
20240111343.COOLING DEVICE AWARE PROCESSOR_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): MUSTANSIR M. PRATAPGARHWALA of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): G06F1/20, G06F9/48
Abstract: a method for configuring a processor includes identifying a component cooling device thermally coupled to a processor, and configuring one or more operating parameters of the processor based on the identification of the component cooling device.
Inventor(s): MICHAEL J. AUSTIN of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc., SUKESH SHENOY of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): G06F1/20, H05K7/20
Abstract: an apparatus for component cooling includes a thermoelectric cooling (tec) device configured to be thermally coupled to a first processor, and a controller. the controller is configured to receive at least one first parameter indicative of a first activity level of the first processor; determine a tec power level from among a plurality of tec power levels based on the at least one first parameter; and control providing of power to the tec device at the determined tec power level.
Inventor(s): Ashish Jain of Austin TX (US) for advanced micro devices, inc., Shang Yang of Markham (CA) for advanced micro devices, inc.
IPC Code(s): G06F1/3206
Abstract: a system and method for determining power-performance state transition thresholds in a computing system. a processor comprises several functional blocks and a power manager. each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. the power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (p-state) transition is indicated. the threshold is determined in part on a current p-state of the given functional block. when the current p-state of the given functional block is relatively high, the threshold activity level to transition to a higher p-state is higher than it would be if the current p-state were relatively low. the power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.
Inventor(s): Sergey Blagodurov of Bellevue WA (US) for advanced micro devices, inc., Kevin Y. Cheng of Bellevue WA (US) for advanced micro devices, inc., SeyedMohammad SeyedzadehDelcheh of Bellevue WA (US) for advanced micro devices, inc., Masab Ahmad of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F1/329
Abstract: methods and systems are disclosed for reducing power consumption by a system including a digital unit and an optical unit. techniques disclosed comprise generating a workload signature of an incoming workload to be executed by the system. based on the generated workload signature, techniques disclosed comprise matching the incoming workload with a profile of stored workload profiles. the workload profiles are generated by a trace capture unit. based on the associated profile, a task submission transaction is sent to the optical unit of the system, representative of a request to execute the incoming workload by the optical unit.
Inventor(s): Jagadish B. Kotra of Austin TX (US) for advanced micro devices, inc., John Kalamatianos of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
Abstract: methods, devices, and systems for retrieving information based on cache miss prediction. it is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. a speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. the information is fetched based on the enabled speculative memory request.
Inventor(s): Nathaniel Morris of Austin TX (US) for advanced micro devices, inc., Kevin Yu-Cheng Cheng of Bothell WA (US) for advanced micro devices, inc., Atul Kumar Sujayendra Sandur of Santa Clara CA (US) for advanced micro devices, inc., Sergey Blagodurov of Bellevue WA (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
Abstract: connection modification based on traffic pattern is described. in accordance with the described techniques, a traffic pattern of memory operations across a set of connections between at least one device and at least one memory is monitored. the traffic pattern is then compared to a threshold traffic pattern condition, such as an amount of data traffic in different directions across the connections. a traffic direction of at least one connection of the set of connections is modified based on the traffic pattern corresponding to the threshold traffic pattern condition.
Inventor(s): Jagadish B. Kotra of Austin TX (US) for advanced micro devices, inc., Marko Scrbak of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
Abstract: a method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. the method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.
Inventor(s): Ashish Jain of Austin TX (US) for advanced micro devices, inc., Shang Yang of Markham (CA) for advanced micro devices, inc., Jun Lei of Markham (CA) for advanced micro devices, inc., Gia Tung Phan of Markham (CA) for advanced micro devices, inc., Oswin Hall of Markham (CA) for advanced micro devices, inc., Benjamin Tsien of Santa Clara CA (US) for advanced micro devices, inc., Narendra Kamat of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F3/06
Abstract: systems, apparatuses, and methods for prefetching data by a display controller. from time to time, a performance-state change of a memory are performed. during such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. during the performance-state change, memory accesses may be temporarily blocked. to sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. in order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.
Inventor(s): Michael John Austin of Austin TX (US) for advanced micro devices, inc., Dmitri Tikhostoup of Markham (CA) for advanced micro devices, inc.
IPC Code(s): G06F3/06
Abstract: an apparatus and method for efficiently managing performance among multiple integrated circuits in separate semiconductor chips. in various implementations, a computing system includes at least a first processing node and a second processing node. while processing tasks, the first processing node uses a first memory and the second processing node uses a second memory. a first communication channel transfers data between the first processing node and the second processing node. the first processing node accesses the second memory using a second communication channel different from the first communication channel and supports point-to-point communication. the second memory services access requests from the first and second processing nodes as the access requests are received while foregoing access conflict detection. the first processing node accesses the second memory after determining a particular amount of time has elapsed after reception of an indication from the second processing node specifying that a particular task has begun.
Inventor(s): Onur Kayiran of West Henrietta NY (US) for advanced micro devices, inc., Michael Estlick of Ft. Collins CO (US) for advanced micro devices, inc., Masab Ahmad of Austin TX (US) for advanced micro devices, inc., Gabriel H. Loh of Bellevue WA (US) for advanced micro devices, inc.
IPC Code(s): G06F7/498, G06F7/506
Abstract: a processing unit includes a plurality of adders and a plurality of carry bit generation circuits. the plurality of adders add first and second x bit binary portion values of a first y bit binary value and a second y bit binary value. y is a multiple of x. the plurality of adders further generate first carry bits. the plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. the plurality of carry bit generation circuits generate second carry bits based on the first carry bits. the plurality of adders use the second carry bits to add the first and second x bit binary portions of the first and second y bit binary values, respectively.
Inventor(s): MICHAEL ESTLICK of FORT COLLINS CO (US) for advanced micro devices, inc., ERIC DIXON of FORT COLLINS CO (US) for advanced micro devices, inc., THEODORE CARLSON of FORT COLLINS CO (US) for advanced micro devices, inc., ERIK D. SWANSON of FORT COLLINS CO (US) for advanced micro devices, inc.
IPC Code(s): G06F9/30
Abstract: a data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. in some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. the shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.
Inventor(s): ERIC DIXON of FORT COLLINS CO (US) for advanced micro devices, inc., MICHAEL ESTLICK of FORT COLLINS CO (US) for advanced micro devices, inc., ERIK D. SWANSON of FORT COLLINS CO (US) for advanced micro devices, inc.
IPC Code(s): G06F9/30, G06F9/345
Abstract: an integrated circuit includes a vector data processing unit that employs a cross-lane shuffle unit including multiplexing logic that programmably shuffles packed source lane values, each corresponding to one of a plurality of vector lanes, to different output vector result lane positions over multiple cycles. in certain implementations, in a first cycle, control logic in the cross-shuffle unit controls the multiplexing logic to select source lane values to be placed in a first group of output vector result lane positions for a vector result register; and in at least a second cycle, the same multiplexing logic is reused to select source lane values to be placed in a second group of output vector result lane positions for the vector result register wherein at least one of the selected source lane values is moved to a different result lane position. associated methods are also presented.
Inventor(s): Bin HE of Orlando FL (US) for advanced micro devices, inc., Michael MANTOR of Orlando FL (US) for advanced micro devices, inc., Jiasheng CHEN of Orlando FL (US) for advanced micro devices, inc., Jian HUANG of Orlando FL (US) for advanced micro devices, inc.
IPC Code(s): G06F9/30, G06F9/38, G06F9/54, G06F17/16
Abstract: a processing unit such as a graphics processing unit (gpu) includes a plurality of vector signal processors (vsps) that include multiply/accumulate elements. the processing unit also includes a plurality of registers associated with the plurality of vsps. first portions of first and second matrices are fetched into the plurality of registers prior to a first round that includes a plurality of iterations. the multiply/accumulate elements perform matrix multiplication and accumulation on different combinations of subsets of the first portions of the first and second matrices in the plurality of iterations prior to fetching second portions of the first and second matrices into the plurality of registers for a second round. the accumulated results of multiplying the first portions of the first and second matrices are written into an output buffer in response to completing the plurality of iterations.
Inventor(s): David Kaplan of Austin TX (US) for advanced micro devices, inc., Jelena Ilic of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F9/455, G06F9/48
Abstract: a processor implements a simultaneous multithreading (smt) protection mode that, when enabled, prevents execution of particular software (e.g., a virtual machine) at a processor core when a thread associated with different software (e.g., a different virtual machine or a hypervisor) is currently executing at the processor core. by preventing execution of the software, data, software execution patterns, and other potentially sensitive information is kept protected from unauthorized access or detection. further, in at least some embodiments the smt protection mode is implemented on a per-software basis, so that different software can choose whether to implement the protection mode, thereby allowing the processor to be employed in a wide variety of computing environments.
20240111574.Work Graph Scheduler Implementation_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Matthäus G. Chajdas of Munich (DE) for advanced micro devices, inc., Michael J. Mantor of Orlando FL (US) for advanced micro devices, inc., Rex Eldon McCrary of Orlando FL (US) for advanced micro devices, inc., Christopher J. Brennan of Boxborough MA (US) for advanced micro devices, inc., Robert Martin of Boxborough MA (US) for advanced micro devices, inc., Dominik Baumeister of Munich (DE) for advanced micro devices, inc., Fabian Robert Sebastian Wildgrube of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F11/30
Abstract: systems, apparatuses, and methods for implementing a hierarchical scheduler. in various implementations, a processor includes a global scheduler, and a plurality of independent local schedulers with each of the local schedulers coupled to a plurality of processors. in one implementation, the processor is a graphics processing unit and the processors are computation units. the processor further includes a shared cache that is shared by the plurality of local schedulers. each of the local schedulers also includes a local cache used by the local scheduler and processors coupled to the local scheduler. to schedule work items for execution, the global scheduler is configured to store one or more work items in the shared cache and convey an indication to a first local scheduler of the plurality of local schedulers which causes the first local scheduler to retrieve the one or more work items from the shared cache. subsequent to retrieving the work items, the local scheduler is configured to schedule the retrieved work items for execution by the coupled processors. each of the plurality of local schedulers is configured to schedule work items for execution independent of scheduling performed by other local schedulers.
Inventor(s): Matthäus G. Chajdas of Munich (DE) for advanced micro devices, inc., Michael J. Mantor of Orlando FL (US) for advanced micro devices, inc., Rex Eldon McCrary of Orlando FL (US) for advanced micro devices, inc., Christopher J. Brennan of Boxborough MA (US) for advanced micro devices, inc., Robert Martin of Boxborough MA (US) for advanced micro devices, inc., Dominik Baumeister of Munich (DE) for advanced micro devices, inc., Fabian Robert Sebastian Wildgrube of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06F9/48, G06F9/54
Abstract: systems, apparatuses, and methods for implementing a message passing system to schedule work in a computing system. in various implementations, a processor includes a global scheduler, and a plurality of local schedulers with each of the local schedulers coupled to a plurality of processors. the processor further includes a shared cache that is shared by the plurality of local schedulers. also, a plurality of mailboxes are implemented to enable communication between the local schedulers and the global scheduler. to schedule work items for execution, the global scheduler is configured to store one or more work items in the shared cache and store an indication in a mailbox for a first local scheduler of the plurality of local schedulers. responsive to detecting the message in the mailbox, the first local scheduler identifies a location of the one or more work items in the shared cache and retrieves them for scheduling locally.
20240111578.HIERARCHICAL WORK SCHEDULING_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Matthaeus G. Chajdas of Munich (DE) for advanced micro devices, inc., Christopher J. Brennan of Boxborough MA (US) for advanced micro devices, inc., Michael Mantor of Orlando FL (US) for advanced micro devices, inc., Robert W. Martin of Acton MA (US) for advanced micro devices, inc., Nicolai Haehnle of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06F9/48
Abstract: a method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. consuming the work item produces a set of new work items. subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. if the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.
Inventor(s): Bradford Michael Beckmann of Kirkland WA (US) for advanced micro devices, inc., Sooraj Puthoor of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F9/50, G06F9/30
Abstract: portions of programs, oftentimes referred to as kernels, are written by programmers to target a particular type of compute unit, such as a central processing unit (cpu) core or a graphics processing unit (gpu) core. when executing a kernel, the kernel is separated into multiple parts referred to as workgroups, and each workgroup is provided to a compute unit for execution. usage of one type of compute unit is monitored and, in response to the one type of compute unit being idle, one or more workgroups targeting another type of compute unit are executed on the one type of compute unit. for example, usage of cpu cores is monitored, and in response to the cpu cores being idle, one or more workgroups targeting gpu cores are executed on the cpu cores.
20240111618.MULTI-LEVEL SIGNAL RECEPTION_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Aaron D. Willey of Hayward CA (US) for advanced micro devices, inc., Karthik Gopalakrishnan of Cupertino CA (US) for advanced micro devices, inc., Pradeep Jayaraman of San Jose CA (US) for advanced micro devices, inc., Ramon Mangaser of Arlington MA (US) for advanced micro devices, inc.
IPC Code(s): G06F11/07
Abstract: a method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. the sampled signals are de-serialized to provide sets of symbols. a start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. the sets of symbols are filtered to provide corresponding output symbols based on the start.
Inventor(s): Mohammad Hamed Mousazadeh of Markham (CA) for advanced micro devices, inc., Arpit Patel of Markham (CA) for advanced micro devices, inc., Gabor Sines of Markham (CA) for advanced micro devices, inc., Omer Irshad of Markham (CA) for advanced micro devices, inc., Phillippe John Louis Yu of Markham (CA) for advanced micro devices, inc., Zongjie Yan of Markham (CA) for advanced micro devices, inc., Ian Charles Colbert of San Diego CA (US) for advanced micro devices, inc.
IPC Code(s): G06F11/07, G06K9/62, G06N20/00
Abstract: the disclosed computer-implemented method for generating remedy recommendations for power and performance issues within semiconductor software and hardware. for example, the disclosed systems and methods can apply a rule-based model to telemetry data to generate rule-based root-cause outputs as well as telemetry-based unknown outputs. the disclosed systems and methods can further apply a root-cause machine learning model to the telemetry-based unknown outputs to analyze deep and complex failure patterns with the telemetry-based unknown outputs to ultimately generate one or more root-cause remedy recommendations that are specific to the identified failure and the client computing device that is experiencing that failure.
Inventor(s): Siddharth K. Shah of Austin TX (US) for advanced micro devices, inc., Vilas Sridharan of Boxborough MA (US) for advanced micro devices, inc., Amitabh Mehra of Fort Collins CO (US) for advanced micro devices, inc., Anil Harwani of Austin TX (US) for advanced micro devices, inc., William Fischofer of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F11/07
Abstract: a disclosed method can include (i) reporting, by a microcontroller, detection of a violation of a physical infrastructure constraint to a machine check architecture, (ii) triggering, by the machine check architecture in response to the reporting, a machine-check exception such that the violation of the physical infrastructure constraint is recorded, and (iii) performing a corrective action based on the triggering of the machine-check exception. various other apparatuses, systems, and methods are also disclosed.
Inventor(s): Benjamin Youngjae Cho of Austin TX (US) for advanced micro devices, inc., Armand Bahram Behroozi of Ypsilanti MI (US) for advanced micro devices, inc., Michael L. Chu of Santa Clara CA (US) for advanced micro devices, inc., Ashwin Aji of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/06, G06F12/02
Abstract: a processing system allocates memory to co-locate input and output operands for operations for processing in memory (pim) execution in the same pim-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. the processing system identifies as “super rows” virtual rows that span all the banks of a memory device. each super row has a different bank-interleaving pattern, referred to as a “color”. a group of contiguous super rows that has the same pim-interleaving pattern is referred to as a “color group”. the processing system assigns memory addresses to each operand (e.g., vector) of an operation for pim execution to a super row having a different color within the same color group to co-locate the operands for each pim execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.
20240111674.Data Reuse Cache_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Alok Garg of Maynard MA (US) for advanced micro devices, inc., Neil N Marketkar of Jamaica Plain MA (US) for advanced micro devices, inc., Matthew T. Sobel of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0811, G06F12/0875, G06F12/0884
Abstract: data reuse cache techniques are described. in one example, a load instruction is generated by an execution unit of a processor unit. in response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.
Inventor(s): John Kalamatianos of Boxborough MA (US) for advanced micro devices, inc., Marko Scrbak of Austin TX (US) for advanced micro devices, inc., Gabriel H. Loh of Bellevue WA (US) for advanced micro devices, inc., Akhil Arunkumar of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0862
Abstract: a disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. the processing device is configured to detect a throttling instruction that indicates a start of a throttling region. the computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. various other apparatuses, systems, and methods are also disclosed.
Inventor(s): Gabriel H. Loh of Bellevue WA (US) for advanced micro devices, inc., Marko Scrbak of Austin TX (US) for advanced micro devices, inc., Akhil Arunkumar of Sunnyvale CA (US) for advanced micro devices, inc., John Kalamatianos of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0862, G06F12/0877
Abstract: a method for performing prefetching operations is disclosed. the method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.
Inventor(s): JAGADISH B. KOTRA of AUSTIN TX (US) for advanced micro devices, inc., JOHN KALAMATIANOS of BOXBOROUGH MA (US) for advanced micro devices, inc., PAUL MOYER of FORT COLLINS CO (US) for advanced micro devices, inc., GABRIEL H. LOH of BELLEVUE WA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0862, G06F12/0811
Abstract: systems and methods for pushed prefetching include: multiple core complexes, each core complex having multiple cores and multiple caches, the multiple caches configured in a memory hierarchy with multiple levels; an interconnect device coupling the core complexes to each other and coupling the core complexes to shared memory, the shared memory at a lower level of the memory hierarchy than the multiple caches; and a push-based prefetcher having logic to: monitor memory traffic between caches of a first level of the memory hierarchy and the shared memory; and based on the monitoring, initiate a prefetch of data to a cache of the first level of the memory hierarchy.
Inventor(s): Alexander Joseph Branover of Chestnut Hill MA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0868, G06F12/084
Abstract: selecting between basic and global persistent flush modes is described. in accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.
Inventor(s): Alexander Joseph Branover of Chestnut Hill MA (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0891
Abstract: runtime flushing to persistency in heterogenous systems is described. in accordance with the described techniques, a system may include a persistent memory in electronic communication with at least one cache and a controller configured to command the at least one cache to flush dirty data to the persistent memory in response to a dirtiness of the at least one cache reaching a cache dirtiness threshold.
Inventor(s): Amit Apte of Austin TX (US) for advanced micro devices, inc., Ganesh Balakrishnan of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0895
Abstract: a method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. in the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.
20240111684.MULTI-LEVEL STARVATION WIDGET_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Sankaranarayanan Gurumurthy of Austin TX (US) for advanced micro devices, inc., Anil Harwani of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06F12/0897
Abstract: the disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. the method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. various other methods, systems, and computer-readable media are also disclosed.
20240111688.MEMORY ACCESS ENGINE_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Omar Fakhri Ahmed of Markham (CA) for advanced micro devices, inc., Norman Vernon Douglas Stewart of Markham (CA) for advanced micro devices, inc., Mihir Shaileshbhai Doctor of Santa Clara CA (US) for advanced micro devices, inc., Jason Todd Arbaugh of Austin TX (US) for advanced micro devices, inc., Milind Baburao Kamble of Austin TX (US) for advanced micro devices, inc., Philip Ng of Markham (CA) for advanced micro devices, inc., Xiaojian Liu of Markham (CA) for advanced micro devices, inc.
IPC Code(s): G06F12/109
Abstract: a technique for servicing a memory request is disclosed. the technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.
20240111710.NON-HOMOGENEOUS CHIPLETS_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Matthaeus G. Chajdas of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06F15/80, G06T15/00
Abstract: a semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. an interconnect communicatively couples the semiconductor dies together. commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
Inventor(s): Akila Subramaniam of Allen TX (US) for advanced micro devices, inc., Ying Liu of Mississauga (CA) for advanced micro devices, inc., Tung Chuen Kwong of Richmond Hill (CA) for advanced micro devices, inc., Juanjo Noguera of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): G06K9/62, G06N3/04
Abstract: an electronic device uses a tiling scheme selected from among a set of tiling schemes for processing instances of input data through a neural network. each of the tiling schemes is associated with a different arrangement of portions into which instances of input data are divided for processing in the neural network. in operation, processing circuitry in the electronic device acquires information about a neural network and properties of the processing circuitry. the processing circuitry then selects a given tiling scheme from among a set of tiling schemes based on the information. the processing circuitry next processes instances of input data in the neural network using the given tiling scheme. processing each instance of input data in the neural network includes dividing the instance of input data into portions based on the given tiling scheme, separately processing each of the portions in the neural network, and combining the respective outputs to generate an output for the instance of input data.
Inventor(s): Tung Chuen Kwong of Markham (CA) for advanced micro devices, inc., Ying Liu of Markham (CA) for advanced micro devices, inc., Akila Subramaniam of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G06T1/60
Abstract: methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. the processing device comprises memory and a processor. the processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. the processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.
Inventor(s): David William John Pankratz of Markham (CA) for advanced micro devices, inc., Konstantin I. Shkurko of Oviedo FL (US) for advanced micro devices, inc.
IPC Code(s): G06T15/06, G06T15/50
Abstract: devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.
Inventor(s): Christopher J. Brennan of Boxborough MA (US) for advanced micro devices, inc., Matthaeus G. Chajdas of Munich (DE) for advanced micro devices, inc.
IPC Code(s): G06T15/30
Abstract: in response to receiving a scene description, a processing system generates a set of planes in the scene and a bounding volume representing a partition of the scene. using the set of planes in the scene, a compute unit of an accelerated processing unit performs a spatial test on the bounding volume to determine whether the bounding volume intersects one or more planes of the set of planes in the scene. based on the spatial test, the compute unit generates intersection data indicating whether the bounding volume intersects one or more planes of the set of planes in the scene. the accelerated processing unit then uses the intersection data to render the scene.
Inventor(s): Aaron D Willey of Hayward CA (US) for advanced micro devices, inc., Karthik Gopalakrishnan of Cupertino CA (US) for advanced micro devices, inc., Pradeep Jayaraman of San Jose CA (US) for advanced micro devices, inc.
IPC Code(s): G11C11/4076
Abstract: a memory system includes a phy embodied on an integrated circuit, the phy coupling to a memory over conductive traces on a substrate. the phy includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing ca signals to the memory, and a second group of driver circuits providing dq signals to the memory. a plurality of the conductive traces which carry the dq signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming dq signals.
20240112722.DIRECTED REFRESH MANAGEMENT FOR DRAM_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Kevin M. Brandl of Austin TX (US) for advanced micro devices, inc., James R. Magro of Lakeway TX (US) for advanced micro devices, inc., Kedarnath Balakrishnan of Bangalore (IN) for advanced micro devices, inc., Jing Wang of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): G11C11/4078, G11C11/406
Abstract: a memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. in response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. in response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.
Inventor(s): Tahsin Askar of Round Rock TX (US) for advanced micro devices, inc., Naveen Davanam of Austin TX (US) for advanced micro devices, inc., Kedarnath Balakrishnan of Bangalore (IN) for advanced micro devices, inc., Kevin M. Brandl of Austin TX (US) for advanced micro devices, inc., James R. Magro of Lakeway TX (US) for advanced micro devices, inc.
IPC Code(s): G11C29/10
Abstract: a memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. the test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.
Inventor(s): Patrick James Shyvers of Fort Collins CO (US) for advanced micro devices, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: the disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. the at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. the at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. the at least one processor is also configured to perform a remediation action in response to detecting the mismatch. various other methods, systems, and computer-readable media are also disclosed.
Inventor(s): GABRIEL H. LOH of BELLEVUE WA (US) for advanced micro devices, inc., ERIC J. CHAPMAN of AUSTIN TX (US) for advanced micro devices, inc., RAJA SWAMINATHAN of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): H01L23/498, H01L23/00
Abstract: a semiconductor package assembly includes a package interface. an interposer die has a first surface and a second surface opposite to the first surface, where the first surface of the interposer is die positioned on the package interface. the interposer die includes a plurality of conductive connections between the first surface and second surface. a chiplet includes a connectivity region having conductive pathways, with a first portion of the connectivity region coupled to a conductive connection of the interposer die and a second portion of the connectivity region cantilevered from the interposer die.
20240113022.POWER VIA WITH REDUCED RESISTANCE_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Richard T. Schultz of Fort Collins CO (US) for advanced micro devices, inc., Omid Rowhani of Markham (CA) for advanced micro devices, inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/535, H01L27/118
Abstract: an apparatus and method for efficiently routing power signals across a semiconductor die. in various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (tsv) that traverses through a silicon substrate layer to a backside metal layer. the integrated circuit includes, at a second node that receives the power supply reference, a second micro tsv that physically contacts at least one source region. the integrated circuit includes a first power rail that connects the first micro tsv to the second micro tsv. this power rail replaces contacts between the micro tsvs and a second power rail such as the frontside metal zero (m0) layer. each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.
Inventor(s): CHINTAN BUCH of SANTA CLARA CA (US) for advanced micro devices, inc., RAJA SWAMINATHAN of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065
Abstract: a method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. a die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. one or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. a second wafer is coupled to a top surface of the die. an amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.
20240113875.METHOD AND APPARATUS FOR STORING KEYS_simplified_abstract_(advanced micro devices, inc.)
Inventor(s): Norman Vernon Douglas Stewart of Markham (CA) for advanced micro devices, inc., Mihir Shaileshbhai Doctor of Santa Clara CA (US) for advanced micro devices, inc., Omar Fakhri Ahmed of Markham (CA) for advanced micro devices, inc., Hemaprabhu Jayanna of Santa Clara CA (US) for advanced micro devices, inc., John Traver of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): H04L9/08
Abstract: a method and apparatus for storing keys in a key storage block includes processing a key request. a first key is allocated based upon the key request. the first key is stored in the key storage block, wherein the first key is of a first size and includes a first rule.
Inventor(s): Sriram Sambamurthy of Austin TX (US) for advanced micro devices, inc., Indrani Paul of Austin TX (US) for advanced micro devices, inc., David Boardman Kramer of Austin TX (US) for advanced micro devices, inc., Madhusudan Chilakam of Boxborough MA (US) for advanced micro devices, inc.
IPC Code(s): H04L12/46, H04L49/109
Abstract: an apparatus and method for efficiently performing power management for multiple clients of a semiconductor chip that supports remote manageability. in various implementations, a network interface receives a packet, and sends at least an indication of the packet to a manageability processing circuitry (mpc) of a processing node with multiple clients for processing tasks. the mpc determines whether a client or itself is a destination needed to process the packet. if the destination is the mpc, then packet processing is done by the mpc without involvement from the clients, which can be in an idle state. for example, the mpc can process a remote manageability packet requesting diagnostic information from one or more clients of the processing node. the network interface and the mpc use a sideband communication channel for data transmission, which foregoes lane training for further reduction in latency and power consumption.
Inventor(s): Rajy Meeyakhan Rawther of Santa Clara CA (US) for advanced micro devices, inc.
IPC Code(s): H04N1/60
Abstract: a processing device and method for executing a color twist operation are provided. the processing device comprises memory and a processor configured to convert values of pixels of a frame from a first color domain to a hue, saturation and value (hsv) color domain, adjust hue values and saturation values of the pixels, store the adjusted hue and saturation values in a portion of the memory local to the processor and convert the frame from the hsv color domain to the first color domain using the adjusted hue and saturation values stored in local memory. the adjusted hue and saturation values are generated from pre-adjusted values, which are generated from masked vector values.
Inventor(s): CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): H05K7/20, F25B21/02, G06F1/20
Abstract: an apparatus for sub-cooling components includes a component cooling device, a processor thermally coupled to the component cooling device, an electronic component, a fan configured to direct an airflow across the processor and the electronic component, and a thermoelectric cooling device thermally coupled to the component cooling device. the thermoelectric cooling device is configured to cool the airflow from a first temperature to a second temperature.
Inventor(s): CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc., ROBERT EDWARD RADKE of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): H05K7/20, F25B21/02, G06F1/20
Abstract: an apparatus for component cooling includes a first heat transfer element configured to be thermally coupled to a heat-generating component, and a second heat transfer element. the apparatus further includes a plurality of thermally conductive paths between the first heat transfer element and the second heat transfer element. each of the plurality of thermally conductive paths are configured to provide a separate heat conduction path from the first heat transfer element to the second heat transfer element.
Inventor(s): CHRISTOPHER M. HELBERG of AUSTIN TX (US) for advanced micro devices, inc., CHRISTOPHER M. JAGGERS of AUSTIN TX (US) for advanced micro devices, inc., ROBERT EDWARD RADKE of AUSTIN TX (US) for advanced micro devices, inc., MUSTANSIR M. PRATAPGARHWALA of AUSTIN TX (US) for advanced micro devices, inc., MICHAEL J. AUSTIN of AUSTIN TX (US) for advanced micro devices, inc., SUKESH SHENOY of Austin TX (US) for advanced micro devices, inc.
IPC Code(s): H05K7/20, G06F1/20
Abstract: an apparatus for component cooling includes a first heat transfer element configured to be thermally coupled to a heat-generating electronic component, and a second heat transfer element. the apparatus further includes a plurality of heat transfer paths thermally coupled between the first heat transfer element and the second heat transfer element. each of the plurality of heat transfer paths configured to provide a separate heat conduction path from the first heat transfer element to the second heat transfer element. the apparatus further includes a manifold including a first fluid passage providing a first portion of a heat transfer fluid in thermal contact with the first heat transfer element, and a second fluid passage providing a second portion of the heat transfer fluid in thermal contact with the second heat transfer element.
Inventor(s): ROBERT EDWARD RADKE of AUSTIN TX (US) for advanced micro devices, inc.
IPC Code(s): H05K7/20, F16F1/18, G06F1/20
Abstract: an apparatus for component cooling includes a manifold and a heat transfer element configured to be thermally coupled to a heat-generating component. the apparatus further includes a first spring mechanism between the manifold and the heat transfer element. the first spring mechanism is configured to apply a first force to the heat transfer element.
ADVANCED MICRO DEVICES, INC. patent applications on April 4th, 2024
- ADVANCED MICRO DEVICES, INC.
- A63F13/355
- A63F13/358
- H04N19/132
- Advanced micro devices, inc.
- G05B19/416
- G06F1/20
- G06F9/48
- H05K7/20
- G06F1/3206
- G06F1/329
- G06F3/06
- G06F7/498
- G06F7/506
- G06F9/30
- G06F9/345
- G06F9/38
- G06F9/54
- G06F17/16
- G06F9/455
- G06F11/30
- G06F9/50
- G06F11/07
- G06K9/62
- G06N20/00
- G06F12/06
- G06F12/02
- G06F12/0811
- G06F12/0875
- G06F12/0884
- G06F12/0862
- G06F12/0877
- G06F12/0868
- G06F12/084
- G06F12/0891
- G06F12/0895
- G06F12/0897
- G06F12/109
- G06F15/80
- G06T15/00
- G06N3/04
- G06T1/60
- G06T15/06
- G06T15/50
- G06T15/30
- G11C11/4076
- G11C11/4078
- G11C11/406
- G11C29/10
- G06F11/10
- H01L23/498
- H01L23/00
- H01L23/528
- H01L21/768
- H01L23/535
- H01L27/118
- H01L25/00
- H01L25/065
- H04L9/08
- H04L12/46
- H04L49/109
- H04N1/60
- F25B21/02
- F16F1/18
