20240057317. RECESSED CHANNEL FIN INTEGRATION simplified abstract (Micron Technology, Inc.)
Contents
RECESSED CHANNEL FIN INTEGRATION
Organization Name
Inventor(s)
Sangmin Hwang of Boise ID (US)
RECESSED CHANNEL FIN INTEGRATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240057317 titled 'RECESSED CHANNEL FIN INTEGRATION
Simplified Explanation
The patent application describes an apparatus with a recessed channel FinFET, which includes fin structures between the source and drain regions that are recessed from the top level of the source and drain regions. The gate is also recessed from the top level of the source and drain regions, separated from the tip regions of the fin structures by a gate dielectric defining a channel between the source and drain regions. These recessed channel FinFETs can be structured in the periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.
- Recessed channel FinFET with fin structures between source and drain regions
- Gate recessed from top level of source and drain regions
- Gate separated from tip regions of fin structures by gate dielectric
- Can be structured in the periphery to an array of a memory device
- Fabricated in a process merged with forming access lines to the array
- Potential Applications
- Memory devices - Integrated circuits - High-performance computing
- Problems Solved
- Improved performance and efficiency of FinFET devices - Enhanced control over channel region - Integration with memory devices
- Benefits
- Higher speed and lower power consumption - Increased integration density - Enhanced reliability and stability of devices
Original Abstract Submitted
a variety of applications can include apparatus having a recessed channel finfet. the recessed channel finfet can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. the recessed channel finfet can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. recessed channel finfets can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.
