18976568. ZERO LATENCY PREFETCHING IN CACHES (TEXAS INSTRUMENTS INCORPORATED)
ZERO LATENCY PREFETCHING IN CACHES
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Oluleye Olorode of Garland TX US
Ramakrishnan Venkatasubramanian of Plano TX US
ZERO LATENCY PREFETCHING IN CACHES
This abstract first appeared for US patent application 18976568 titled 'ZERO LATENCY PREFETCHING IN CACHES
Original Abstract Submitted
This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetchs the lower half level two cache line employing fewer resources than an ordinary prefetch.