18893028. PAGE FAULTING AND SELECTIVE PREEMPTION (Intel Corporation)
Contents
PAGE FAULTING AND SELECTIVE PREEMPTION
Organization Name
Inventor(s)
Altug Koker of El Dorado Hills CA US
Ingo Wald of Salt Lake City UT US
Subramaniam M. Maiyuran of Gold River CA US
Prasoonkumar Surti of Folsom CA US
Guei-Yuan Lueh of San Jose CA US
Murali Ramadoss of Folsom CA US
Abhishek R. Appu of El Dorado Hills CA US
PAGE FAULTING AND SELECTIVE PREEMPTION
This abstract first appeared for US patent application 18893028 titled 'PAGE FAULTING AND SELECTIVE PREEMPTION
Original Abstract Submitted
One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.
- Intel Corporation
- Altug Koker of El Dorado Hills CA US
- Ingo Wald of Salt Lake City UT US
- David Puffer of Tempe AZ US
- Subramaniam M. Maiyuran of Gold River CA US
- Prasoonkumar Surti of Folsom CA US
- Balaji Vembu of Folsom CA US
- Guei-Yuan Lueh of San Jose CA US
- Murali Ramadoss of Folsom CA US
- Abhishek R. Appu of El Dorado Hills CA US
- Joydeep Ray of Folsom CA US
- G06T1/20
- G06F9/30
- G06F9/38
- G06F9/46
- G06F9/48
- CPC G06T1/20
