18892965. SEMICONDUCTOR PACKAGE (Samsung Electronics Co., Ltd.)
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Jumyong Park of Yongin-si (KR)
Taehwa Jeong of Hwaseong-si (KR)
Atsushi Fujisaki of Seongnam-si (KR)
SEMICONDUCTOR PACKAGE
This abstract first appeared for US patent application 18892965 titled 'SEMICONDUCTOR PACKAGE
Original Abstract Submitted
A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.
