18757531. PACKAGE STRUCTURE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)
Contents
PACKAGE STRUCTURE
Organization Name
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s)
Ming-Fa Chen of Taichung City (TW)
Sung-Feng Yeh of Taipei City (TW)
Tzuan-Horng Liu of Taoyuan City (TW)
Chao-Wen Shih of Hsinchu County (TW)
PACKAGE STRUCTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18757531 titled 'PACKAGE STRUCTURE
The abstract of the patent application describes a chip structure consisting of two semiconductor chips, with the second chip embedded within the first chip. The first chip includes various layers such as a substrate, interconnection layer, protection layer, gap fill layer, and conductive vias. The second chip also has similar layers and is bonded to the first protection layer.
- The chip structure includes two semiconductor chips, with the second chip embedded within the first chip.
- Various layers such as substrate, interconnection layer, protection layer, gap fill layer, and conductive vias are present in both chips.
- The second chip is bonded to the first protection layer of the first chip.
- This innovative design allows for compact integration of multiple semiconductor chips within a single structure.
- The use of conductive vias enables electrical connections between different layers of the chips.
Potential Applications: - This technology can be used in the development of advanced integrated circuits for various electronic devices. - It can also be applied in the manufacturing of high-performance computing systems and data storage devices.
Problems Solved: - Enables efficient integration of multiple semiconductor chips within a compact structure. - Facilitates improved electrical connectivity between different layers of the chips.
Benefits: - Enhanced performance and functionality of integrated circuits. - Increased efficiency in the design and manufacturing of semiconductor devices.
Commercial Applications: Title: Advanced Chip Structures for Enhanced Performance in Electronic Devices This technology has potential commercial applications in the semiconductor industry for the development of high-performance integrated circuits and electronic devices. It can cater to the growing demand for compact and efficient semiconductor solutions in various sectors such as consumer electronics, telecommunications, and computing.
Questions about the Technology: 1. How does the innovative chip structure improve the performance of electronic devices? - The innovative chip structure allows for efficient integration of multiple semiconductor chips within a compact design, enhancing the overall performance of electronic devices.
2. What are the potential applications of this technology in the semiconductor industry? - This technology can be applied in the development of advanced integrated circuits for various electronic devices, as well as in high-performance computing systems and data storage devices.
Original Abstract Submitted
A chip structure includes first and second semiconductor chips. The first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. The second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.
