18751859. METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES (Tokyo Electron Limited)
Contents
METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES
Organization Name
Inventor(s)
H. Jim Fulford of Marianna FL (US)
Partha Mukhopadhyay of Oviedo FL (US)
Mark I. Gardner of Austin TX (US)
METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES
This abstract first appeared for US patent application 18751859 titled 'METHOD FOR STACKING INTEGRATED CIRCUIT WAFERS AND DIES
Original Abstract Submitted
A method includes receiving a first device wafer comprising a plurality of dies, bonding a first side of a temporary wafer to a first side of the first device wafer to form a combined wafer, and performing a first patterning process on the combined wafer to form first trenches in the combined wafer. The first trenches fully extend through the first device wafer and partially into the temporary wafer from the first side of the temporary wafer. The first trenches separate the plurality of dies from each other. The method further includes placing the combined wafer on a support and applying a force to the combined wafer to separate the temporary wafer into individual temporary regions. Each individual temporary region is bonded to a respective individual die. The method further includes attaching individual dies to a second device wafer and removing the individual temporary regions from the individual dies.
