18733125. MULTI-LEVEL CACHE SECURITY simplified abstract (Texas Instruments Incorporated)
Contents
MULTI-LEVEL CACHE SECURITY
Organization Name
Texas Instruments Incorporated
Inventor(s)
Abhijeet Ashok Chachad of Plano TX (US)
David Matthew Thompson of Dallas TX (US)
Naveen Bhoria of Plano TX (US)
MULTI-LEVEL CACHE SECURITY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18733125 titled 'MULTI-LEVEL CACHE SECURITY
The abstract describes a system with first and second level memories, memory controllers, and a shadow cache. The system responds to read operations with secure codes by checking addresses and secure codes in the shadow cache and cache lines.
- Simplified Explanation: The system described in the patent application includes memories, controllers, and a cache that work together to handle read operations with secure codes.
- Key Features and Innovation:
- Utilizes a shadow cache to store secure code information for efficient read operation handling. - Checks addresses and secure codes to determine cache line hits and perform additional operations accordingly.
- Potential Applications:
- Data security systems - Memory management in computer systems - Cache optimization techniques
- Problems Solved:
- Efficient handling of read operations with secure codes - Improved cache performance and data security
- Benefits:
- Enhanced data security - Optimized memory management - Improved system performance
- Commercial Applications:
- Secure data storage solutions - Memory management software for computer systems - Cache optimization tools for IT infrastructure
- Prior Art:
- Researchers can explore prior patents related to memory management, cache optimization, and data security systems.
- Frequently Updated Research:
- Stay updated on advancements in memory management, cache optimization, and data security technologies.
Questions about the technology: 1. How does the system ensure data security during read operations with secure codes? 2. What are the potential implications of using a shadow cache in memory management systems?
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Original Abstract Submitted
An example system includes first and second level memories and first and second memory controllers respectively coupled thereto. The system also includes a shadow cache associated with the second level memory and coupled to the second memory controller, which is also coupled to the first memory controller. In response to a generated read operation that includes a secure code, the second memory controller determines whether an address of the read operation matches an address that is tagged in the shadow cache; and determine whether the secure code of the read operation matches a secure code of a cache line hit by the read operation. The second memory controller then performs one of two sets of additional operations, depending on whether or not the address of the read operation matches the address tagged in the shadow cache and whether or not the secure code of the read operation matches the secure code of the cache line.
