18680970. SYSTEM DECODER FOR TRAINING ACCELERATORS simplified abstract (Intel Corporation)
Contents
SYSTEM DECODER FOR TRAINING ACCELERATORS
Organization Name
Inventor(s)
Francesc Guim Bernat of Barcelona (ES)
Da-Ming Chiang of San Jose CA (US)
Kshitij A. Doshi of Tempe AZ (US)
Suraj Prabhakaran of Aachen (DE)
Mark A. Schmisseur of Phoenix AZ (US)
SYSTEM DECODER FOR TRAINING ACCELERATORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18680970 titled 'SYSTEM DECODER FOR TRAINING ACCELERATORS
The abstract describes an artificial intelligence system with a first hardware platform, a fabric interface connecting it to a second hardware platform, a processor for AI operations, and a training accelerator with inter-chip links to share data between multiple accelerators without processor intervention.
- The AI system includes a first hardware platform and a fabric interface for communication with a second hardware platform.
- A processor on the first hardware platform is programmed to handle AI tasks.
- A training accelerator is equipped with hardware and inter-chip links to connect with other accelerators on the same and different hardware platforms.
- The system decoder manages the sharing of data between the training accelerators without involving the processor.
Potential Applications: - Deep learning applications - Neural network training - AI model optimization
Problems Solved: - Efficient data sharing between training accelerators - Enhanced performance in AI tasks - Scalability in AI systems
Benefits: - Faster AI model training - Improved accuracy in AI predictions - Cost-effective AI hardware design
Commercial Applications: Title: Advanced AI Training System for Enhanced Performance This technology can be used in industries such as healthcare, finance, and autonomous vehicles for advanced AI model training and optimization, leading to more accurate predictions and improved decision-making processes.
Prior Art: Researchers can explore prior patents related to AI hardware design, inter-chip communication, and accelerator systems to understand the evolution of similar technologies.
Frequently Updated Research: Stay updated on the latest advancements in AI hardware design, inter-chip communication protocols, and training accelerator technologies to enhance the performance of AI systems.
Questions about AI Training Accelerator Systems: 1. How does the fabric interface improve data sharing between training accelerators? 2. What are the key advantages of using inter-chip links in AI hardware design?
Original Abstract Submitted
There is disclosed an example of an artificial intelligence (AI) system, including: a first hardware platform; a fabric interface configured to communicatively couple the first hardware platform to a second hardware platform; a processor hosted on the first hardware platform and programmed to operate on an AI problem; and a first training accelerator, including: an accelerator hardware; a platform inter-chip link (ICL) configured to communicatively couple the first training accelerator to a second training accelerator on the first hardware platform without aid of the processor; a fabric ICL to communicatively couple the first training accelerator to a third training accelerator on a second hardware platform without aid of the processor; and a system decoder configured to operate the fabric ICL and platform ICL to share data of the accelerator hardware between the first training accelerator and second and third training accelerators without aid of the processor.
